cslr_spl.h

来自「dsp在音频处理中的运用」· C头文件 代码 · 共 323 行

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#ifndef _CSLR_SPL_001_H_
#define _CSLR_SPL_001_H_
/*********************************************************************
 * Copyright (C) 2003-2004 Texas Instruments Incorporated. 
 * All Rights Reserved 
 *********************************************************************/
 /** \file cslr_spl_001.h
 * 
 * \brief This file contains the Register Desciptions for SPL
 * 
 *********************************************************************/

#include <cslr.h>

#include <tistdtypes.h>

/**************************************************************************\
* Register Overlay Structure
\**************************************************************************/
typedef struct  {
    volatile Uint16 WAKENCR;
    volatile Uint8 RSVD0[2];
    volatile Uint16 WAKSR;
    volatile Uint8 RSVD1[2];
    volatile Uint16 WAKCNT;
    volatile Uint8 RSVD2[2];
    volatile Uint16 PINCR1;
    volatile Uint8 RSVD3[2];
    volatile Uint16 PINCR2;
    volatile Uint8 RSVD4[2];
    volatile Uint16 GPIO1MUXCR;
    volatile Uint8 RSVD5[2];
    volatile Uint16 SPSCR;
    volatile Uint8 RSVD6[6];
    volatile Uint16 ULPDCNT;
} CSL_SplRegs;


/**
 * Overlay structure typedef definition
 */
typedef volatile CSL_SplRegs * CSL_SplRegsOvly;


/**************************************************************************\
* Field Definition Macros
\**************************************************************************/

/* WAKENCR */

#define CSL_SPL_WAKENCR_SDRPDNREQ_MASK   (0x0200u)
#define CSL_SPL_WAKENCR_SDRPDNREQ_SHIFT  (0x0009u)
#define CSL_SPL_WAKENCR_SDRPDNREQ_RESETVAL (0x0000u)

/*----SDRPDNREQ Tokens----*/
#define CSL_SPL_WAKENCR_SDRPDNREQ_DISABLE (0x0000u)
#define CSL_SPL_WAKENCR_SDRPDNREQ_ENABLE (0x0001u)

#define CSL_SPL_WAKENCR_DCMREQ_MASK      (0x0100u)
#define CSL_SPL_WAKENCR_DCMREQ_SHIFT     (0x0008u)
#define CSL_SPL_WAKENCR_DCMREQ_RESETVAL  (0x0000u)

/*----DCMREQ Tokens----*/
#define CSL_SPL_WAKENCR_DCMREQ_DISABLE   (0x0000u)
#define CSL_SPL_WAKENCR_DCMREQ_ENABLE    (0x0001u)

#define CSL_SPL_WAKENCR_MPURST_MASK      (0x0040u)
#define CSL_SPL_WAKENCR_MPURST_SHIFT     (0x0006u)
#define CSL_SPL_WAKENCR_MPURST_RESETVAL  (0x0001u)

/*----MPURST Tokens----*/
#define CSL_SPL_WAKENCR_MPURST_DISABLE   (0x0000u)
#define CSL_SPL_WAKENCR_MPURST_ENABLE    (0x0001u)

#define CSL_SPL_WAKENCR_RTC_MASK         (0x0020u)
#define CSL_SPL_WAKENCR_RTC_SHIFT        (0x0005u)
#define CSL_SPL_WAKENCR_RTC_RESETVAL     (0x0000u)

/*----RTC Tokens----*/
#define CSL_SPL_WAKENCR_RTC_DISABLE      (0x0000u)
#define CSL_SPL_WAKENCR_RTC_ENABLE       (0x0001u)

#define CSL_SPL_WAKENCR_HECC2_MASK       (0x0010u)
#define CSL_SPL_WAKENCR_HECC2_SHIFT      (0x0004u)
#define CSL_SPL_WAKENCR_HECC2_RESETVAL   (0x0000u)

/*----HECC2 Tokens----*/
#define CSL_SPL_WAKENCR_HECC2_DISABLE    (0x0000u)
#define CSL_SPL_WAKENCR_HECC2_ENABLE     (0x0001u)

#define CSL_SPL_WAKENCR_HECC1_MASK       (0x0008u)
#define CSL_SPL_WAKENCR_HECC1_SHIFT      (0x0003u)
#define CSL_SPL_WAKENCR_HECC1_RESETVAL   (0x0000u)

/*----HECC1 Tokens----*/
#define CSL_SPL_WAKENCR_HECC1_DISABLE    (0x0000u)
#define CSL_SPL_WAKENCR_HECC1_ENABLE     (0x0001u)

#define CSL_SPL_WAKENCR_GPIO1_MASK       (0x0002u)
#define CSL_SPL_WAKENCR_GPIO1_SHIFT      (0x0001u)
#define CSL_SPL_WAKENCR_GPIO1_RESETVAL   (0x0000u)

/*----GPIO1 Tokens----*/
#define CSL_SPL_WAKENCR_GPIO1_DISABLE    (0x0000u)
#define CSL_SPL_WAKENCR_GPIO1_ENABLE     (0x0001u)

#define CSL_SPL_WAKENCR_RESETVAL         (0x0040u)

/* WAKSR */

#define CSL_SPL_WAKSR_POWERON_MASK       (0x8000u)
#define CSL_SPL_WAKSR_POWERON_SHIFT      (0x000Fu)
#define CSL_SPL_WAKSR_POWERON_RESETVAL   (0x0000u)

#define CSL_SPL_WAKSR_32KOSCMODE_MASK    (0x2000u)
#define CSL_SPL_WAKSR_32KOSCMODE_SHIFT   (0x000Du)
#define CSL_SPL_WAKSR_32KOSCMODE_RESETVAL (0x0000u)

/*----32KOSCMODE Tokens----*/
#define CSL_SPL_WAKSR_32KOSCMODE_INTOSCMODE (0x0000u)
#define CSL_SPL_WAKSR_32KOSCMODE_EXTOSCMODE (0x0001u)

#define CSL_SPL_WAKSR_SDRPDNSTAT_MASK    (0x0200u)
#define CSL_SPL_WAKSR_SDRPDNSTAT_SHIFT   (0x0009u)
#define CSL_SPL_WAKSR_SDRPDNSTAT_RESETVAL (0x0000u)

/*----SDRPDNSTAT Tokens----*/
#define CSL_SPL_WAKSR_SDRPDNSTAT_NO      (0x0000u)
#define CSL_SPL_WAKSR_SDRPDNSTAT_YES     (0x0001u)

#define CSL_SPL_WAKSR_DCMSTAT_MASK       (0x0100u)
#define CSL_SPL_WAKSR_DCMSTAT_SHIFT      (0x0008u)
#define CSL_SPL_WAKSR_DCMSTAT_RESETVAL   (0x0000u)

/*----DCMSTAT Tokens----*/
#define CSL_SPL_WAKSR_DCMSTAT_SCM        (0x0000u)
#define CSL_SPL_WAKSR_DCMSTAT_DCM        (0x0001u)

#define CSL_SPL_WAKSR_RESERVED_MASK      (0x0080u)
#define CSL_SPL_WAKSR_RESERVED_SHIFT     (0x0007u)
#define CSL_SPL_WAKSR_RESERVED_RESETVAL  (0x0000u)

#define CSL_SPL_WAKSR_MPURST_MASK        (0x0040u)
#define CSL_SPL_WAKSR_MPURST_SHIFT       (0x0006u)
#define CSL_SPL_WAKSR_MPURST_RESETVAL    (0x0000u)

/*----MPURST Tokens----*/
#define CSL_SPL_WAKSR_MPURST_NO          (0x0000u)
#define CSL_SPL_WAKSR_MPURST_YES         (0x0001u)

#define CSL_SPL_WAKSR_RTC_MASK           (0x0020u)
#define CSL_SPL_WAKSR_RTC_SHIFT          (0x0005u)
#define CSL_SPL_WAKSR_RTC_RESETVAL       (0x0000u)

/*----RTC Tokens----*/
#define CSL_SPL_WAKSR_RTC_NO             (0x0000u)
#define CSL_SPL_WAKSR_RTC_YES            (0x0001u)

#define CSL_SPL_WAKSR_HECC2_MASK         (0x0010u)
#define CSL_SPL_WAKSR_HECC2_SHIFT        (0x0004u)
#define CSL_SPL_WAKSR_HECC2_RESETVAL     (0x0000u)

/*----HECC2 Tokens----*/
#define CSL_SPL_WAKSR_HECC2_NO           (0x0000u)
#define CSL_SPL_WAKSR_HECC2_YES          (0x0001u)

#define CSL_SPL_WAKSR_HECC1_MASK         (0x0008u)
#define CSL_SPL_WAKSR_HECC1_SHIFT        (0x0003u)
#define CSL_SPL_WAKSR_HECC1_RESETVAL     (0x0000u)

/*----HECC1 Tokens----*/
#define CSL_SPL_WAKSR_HECC1_NO           (0x0000u)
#define CSL_SPL_WAKSR_HECC1_YES          (0x0001u)

#define CSL_SPL_WAKSR_GPIO1_MASK         (0x0002u)
#define CSL_SPL_WAKSR_GPIO1_SHIFT        (0x0001u)
#define CSL_SPL_WAKSR_GPIO1_RESETVAL     (0x0000u)

/*----GPIO1 Tokens----*/
#define CSL_SPL_WAKSR_GPIO1_NO           (0x0000u)
#define CSL_SPL_WAKSR_GPIO1_YES          (0x0001u)

#define CSL_SPL_WAKSR_SPSEXIT_MASK       (0x0001u)
#define CSL_SPL_WAKSR_SPSEXIT_SHIFT      (0x0000u)
#define CSL_SPL_WAKSR_SPSEXIT_RESETVAL   (0x0000u)

/*----SPSEXIT Tokens----*/
#define CSL_SPL_WAKSR_SPSEXIT_NO         (0x0000u)
#define CSL_SPL_WAKSR_SPSEXIT_YES        (0x0001u)

#define CSL_SPL_WAKSR_RESETVAL           (0x0000u)

/* WAKCNT */

#define CSL_SPL_WAKCNT_WAKCNT_MASK       (0xFFFFu)
#define CSL_SPL_WAKCNT_WAKCNT_SHIFT      (0x0000u)
#define CSL_SPL_WAKCNT_WAKCNT_RESETVAL   (0x0000u)

#define CSL_SPL_WAKCNT_RESETVAL          (0x0000u)

/* PINCR1 */

#define CSL_SPL_PINCR1_GPIO15MUXSEL_MASK (0x8000u)
#define CSL_SPL_PINCR1_GPIO15MUXSEL_SHIFT (0x000Fu)
#define CSL_SPL_PINCR1_GPIO15MUXSEL_RESETVAL (0x0000u)

/*----GPIO15MUXSEL Tokens----*/
#define CSL_SPL_PINCR1_GPIO15MUXSEL_GPIO15 (0x0000u)
#define CSL_SPL_PINCR1_GPIO15MUXSEL_HECC_XCLK (0x0001u)

#define CSL_SPL_PINCR1_GPIO14MUXSEL_MASK (0x4000u)
#define CSL_SPL_PINCR1_GPIO14MUXSEL_SHIFT (0x000Eu)
#define CSL_SPL_PINCR1_GPIO14MUXSEL_RESETVAL (0x0000u)

/*----GPIO14MUXSEL Tokens----*/
#define CSL_SPL_PINCR1_GPIO14MUXSEL_GPIO14 (0x0000u)
#define CSL_SPL_PINCR1_GPIO14MUXSEL_ADCCEOC (0x0001u)

#define CSL_SPL_PINCR1_GPIO13MUXSEL_MASK (0x2000u)
#define CSL_SPL_PINCR1_GPIO13MUXSEL_SHIFT (0x000Du)
#define CSL_SPL_PINCR1_GPIO13MUXSEL_RESETVAL (0x0000u)

/*----GPIO13MUXSEL Tokens----*/
#define CSL_SPL_PINCR1_GPIO13MUXSEL_GPIO13 (0x0000u)
#define CSL_SPL_PINCR1_GPIO13MUXSEL_CLKOUT32K (0x0001u)

#define CSL_SPL_PINCR1_GPIO12MUXSEL_MASK (0x1000u)
#define CSL_SPL_PINCR1_GPIO12MUXSEL_SHIFT (0x000Cu)
#define CSL_SPL_PINCR1_GPIO12MUXSEL_RESETVAL (0x0000u)

/*----GPIO12MUXSEL Tokens----*/
#define CSL_SPL_PINCR1_GPIO12MUXSEL_GPIO12 (0x0000u)
#define CSL_SPL_PINCR1_GPIO12MUXSEL_BUFRW (0x0001u)

#define CSL_SPL_PINCR1_GPIO11MUXSEL_MASK (0x0800u)
#define CSL_SPL_PINCR1_GPIO11MUXSEL_SHIFT (0x000Bu)
#define CSL_SPL_PINCR1_GPIO11MUXSEL_RESETVAL (0x0000u)

/*----GPIO11MUXSEL Tokens----*/
#define CSL_SPL_PINCR1_GPIO11MUXSEL_GPIO11 (0x0000u)
#define CSL_SPL_PINCR1_GPIO11MUXSEL_GPTIMER5 (0x0001u)

#define CSL_SPL_PINCR1_GPIO10MUXSEL_MASK (0x0400u)
#define CSL_SPL_PINCR1_GPIO10MUXSEL_SHIFT (0x000Au)
#define CSL_SPL_PINCR1_GPIO10MUXSEL_RESETVAL (0x0000u)

/*----GPIO10MUXSEL Tokens----*/
#define CSL_SPL_PINCR1_GPIO10MUXSEL_GPIO10 (0x0000u)
#define CSL_SPL_PINCR1_GPIO10MUXSEL_GPTIMER6 (0x0001u)

#define CSL_SPL_PINCR1_RESETVAL          (0x0000u)

/* PINCR2 */

#define CSL_SPL_PINCR2_PULLGPIO1_MASK    (0x0040u)
#define CSL_SPL_PINCR2_PULLGPIO1_SHIFT   (0x0006u)
#define CSL_SPL_PINCR2_PULLGPIO1_RESETVAL (0x0000u)

/*----PULLGPIO1 Tokens----*/
#define CSL_SPL_PINCR2_PULLGPIO1_ENABLED (0x0000u)
#define CSL_SPL_PINCR2_PULLGPIO1_DISABLED (0x0001u)

#define CSL_SPL_PINCR2_PULLHECC1_MASK    (0x0010u)
#define CSL_SPL_PINCR2_PULLHECC1_SHIFT   (0x0004u)
#define CSL_SPL_PINCR2_PULLHECC1_RESETVAL (0x0000u)

/*----PULLHECC1 Tokens----*/
#define CSL_SPL_PINCR2_PULLHECC1_ENABLED (0x0000u)
#define CSL_SPL_PINCR2_PULLHECC1_DISABLED (0x0001u)

#define CSL_SPL_PINCR2_PULLHECC2_MASK    (0x0008u)
#define CSL_SPL_PINCR2_PULLHECC2_SHIFT   (0x0003u)
#define CSL_SPL_PINCR2_PULLHECC2_RESETVAL (0x0000u)

/*----PULLHECC2 Tokens----*/
#define CSL_SPL_PINCR2_PULLHECC2_ENABLED (0x0000u)
#define CSL_SPL_PINCR2_PULLHECC2_DISABLED (0x0001u)

#define CSL_SPL_PINCR2_DBGMUX_MASK       (0x0003u)
#define CSL_SPL_PINCR2_DBGMUX_SHIFT      (0x0000u)
#define CSL_SPL_PINCR2_DBGMUX_RESETVAL   (0x0000u)

/*----DBGMUX Tokens----*/
#define CSL_SPL_PINCR2_DBGMUX_GPIO1      (0x0000u)
#define CSL_SPL_PINCR2_DBGMUX_GPIO1U8DBGL8 (0x0001u)
#define CSL_SPL_PINCR2_DBGMUX_GPIO1U4OBSL12 (0x0002u)

#define CSL_SPL_PINCR2_RESETVAL          (0x0000u)

/* GPIO1MUXCR */

#define CSL_SPL_GPIO1MUXCR_XBA_MASK      (0xFFFFu)
#define CSL_SPL_GPIO1MUXCR_XBA_SHIFT     (0x0000u)
#define CSL_SPL_GPIO1MUXCR_XBA_RESETVAL  (0x0000u)

/*----xBA Tokens----*/
#define CSL_SPL_GPIO1MUXCR_XBA_GPIO1A    (0x0000u)
#define CSL_SPL_GPIO1MUXCR_XBA_GPIO1B    (0x0001u)

#define CSL_SPL_GPIO1MUXCR_RESETVAL      (0x0000u)

/* SPSCR */

#define CSL_SPL_SPSCR_SPSEN_MASK         (0x0001u)
#define CSL_SPL_SPSCR_SPSEN_SHIFT        (0x0000u)
#define CSL_SPL_SPSCR_SPSEN_RESETVAL     (0x0000u)

/*----SPSEN Tokens----*/
#define CSL_SPL_SPSCR_SPSEN_DISABLE      (0x0000u)
#define CSL_SPL_SPSCR_SPSEN_ENABLE       (0x0001u)

#define CSL_SPL_SPSCR_RESETVAL           (0x0000u)

/* ULPDCNT */

#define CSL_SPL_ULPDCNT_ULPDCNT_MASK     (0xFFFFu)
#define CSL_SPL_ULPDCNT_ULPDCNT_SHIFT    (0x0000u)
#define CSL_SPL_ULPDCNT_ULPDCNT_RESETVAL (0x03FFu)

#define CSL_SPL_ULPDCNT_RESETVAL         (0x03FFu)

#endif

cslr_spl.h - 源码说明

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