cslr_hdq1w.h

dsp在音频处理中的运用

/** ============================================================================
 *   @file  cslr_hdq1w.h
 *
 *   @path  $(CSLPATH)\arm\hdq1w\inc
 *
 *   @desc  This file contains the Register Desciptions for HDQ1W
 *
 */
 
/* =============================================================================
 *   Copyright (c) Texas Instruments Inc 2002, 2003, 2004
 *
 *   Use of this software is controlled by the terms and conditions found in the
 *   license agreement under which this software has been supplied.
 *  ============================================================================
 */

/*  @(#) PSP/CSL 3.00.01.00[5912] (2004-08-03)  */

/* =============================================================================
 *  Revision History
 *  ================
 *  03-Aug-2004 sp File Created.
 *
 * =============================================================================
 */
#ifndef _CSLR_HDQ1W_H_
#define _CSLR_HDQ1W_H_

#include <cslr.h>
#include <tistdtypes.h>

#ifdef __cplusplus
extern "C" {
#endif

/**
 * Register Overlay Structure
 */
typedef struct  {
    volatile Uint32 HDQ1W_TX;
    volatile Uint32 HDQ1W_RX;
    volatile Uint32 HDQ1W_CTRL;
    volatile Uint32 HDQ1W_INTS;
} CSL_Hdq1wRegs;

typedef volatile CSL_Hdq1wRegs* CSL_Hdq1wRegsOvly;

/**
 * Field Definition Macros
 */

/* HDQ1W_TX */
/** Transmit write data field mask*/
#define CSL_HDQ1W_HDQ1W_TX_WD_MASK       (0x000000FFu)
/** Transmit write data field shift*/
#define CSL_HDQ1W_HDQ1W_TX_WD_SHIFT      (0x00000000u)
/** Transmit write data field reset value*/
#define CSL_HDQ1W_HDQ1W_TX_WD_RESETVAL   (0x00000000u)

/** Transmit write data register reset value*/
#define CSL_HDQ1W_HDQ1W_TX_RESETVAL      (0x00000000u)

/* HDQ1W_RX */

/** Receive buffer field mask*/
#define CSL_HDQ1W_HDQ1W_RX_RD_MASK       (0x000000FFu)
/** Receive buffer field shift*/
#define CSL_HDQ1W_HDQ1W_RX_RD_SHIFT      (0x00000000u)
/** Receive buffer field reset value*/
#define CSL_HDQ1W_HDQ1W_RX_RD_RESETVAL   (0x00000000u)

/** Receive buffer register reset value */
#define CSL_HDQ1W_HDQ1W_RX_RESETVAL      (0x00000000u)

/* HDQ1W_CTRL */

/** Single bit mode field mask*/
#define CSL_HDQ1W_HDQ1W_CTRL_SBM_MASK    (0x00000080u)
/** Single bit mode field shift*/
#define CSL_HDQ1W_HDQ1W_CTRL_SBM_SHIFT   (0x00000007u)
/** Single bit mode field reset value*/
#define CSL_HDQ1W_HDQ1W_CTRL_SBM_RESETVAL (0x00000000u)

/*----SBM Tokens----*/
/** Token for 1-Wire byte mode*/
#define CSL_HDQ1W_HDQ1W_CTRL_SBM_BYTE    (0x00000000u)
/** Token for 1-Wire single bit mode*/
#define CSL_HDQ1W_HDQ1W_CTRL_SBM_BIT     (0x00000001u)

/** Interrupt mask field mask*/
#define CSL_HDQ1W_HDQ1W_CTRL_IM_MASK     (0x00000040u)
/** Interrupt mask field shift*/
#define CSL_HDQ1W_HDQ1W_CTRL_IM_SHIFT    (0x00000006u)
/** Interrupt mask field reset value*/
#define CSL_HDQ1W_HDQ1W_CTRL_IM_RESETVAL (0x00000000u)

/*----IM Tokens----*/
/** Token for disabling interrupt mask*/
#define CSL_HDQ1W_HDQ1W_CTRL_IM_DIS      (0x00000000u)
/** Token for enabling interrupt mask*/
#define CSL_HDQ1W_HDQ1W_CTRL_IM_EN       (0x00000001u)

/** Power down mode field mask*/
#define CSL_HDQ1W_HDQ1W_CTRL_PDM_MASK    (0x00000020u)
/** Power down mode field shift*/
#define CSL_HDQ1W_HDQ1W_CTRL_PDM_SHIFT   (0x00000005u)
/** Power down field reset value*/
#define CSL_HDQ1W_HDQ1W_CTRL_PDM_RESETVAL (0x00000000u)

/*----PDM Tokens----*/
/** Token for disabling power down mode*/
#define CSL_HDQ1W_HDQ1W_CTRL_PDM_DIS     (0x00000001u)
/** Token for enabling power down mode*/
#define CSL_HDQ1W_HDQ1W_CTRL_PDM_EN      (0x00000000u)

/** Go bit field mask*/
#define CSL_HDQ1W_HDQ1W_CTRL_GB_MASK     (0x00000010u)
/** Go bit field shift*/
#define CSL_HDQ1W_HDQ1W_CTRL_GB_SHIFT    (0x00000004u)
/** So bit field reset value*/
#define CSL_HDQ1W_HDQ1W_CTRL_GB_RESETVAL (0x00000000u)

/*----GB Tokens----*/
/** Token to indicate that Go bit is cleared*/
#define CSL_HDQ1W_HDQ1W_CTRL_GB_DONE     (0x00000000u)
/** Token to indicate that Go bit is set*/
#define CSL_HDQ1W_HDQ1W_CTRL_GB_GO       (0x00000001u)

/** Slave presence detect field mask*/
#define CSL_HDQ1W_HDQ1W_CTRL_PD_MASK     (0x00000008u)
/** Slave presence detect field shift*/
#define CSL_HDQ1W_HDQ1W_CTRL_PD_SHIFT    (0x00000003u)
/** Slave presence detect field reset value*/
#define CSL_HDQ1W_HDQ1W_CTRL_PD_RESETVAL (0x00000000u)

/** Initialization bit field mask*/
#define CSL_HDQ1W_HDQ1W_CTRL_IP_MASK     (0x00000004u)
/** Initialization bit field shift*/
#define CSL_HDQ1W_HDQ1W_CTRL_IP_SHIFT    (0x00000002u)
/** Initialization bit field reset value*/
#define CSL_HDQ1W_HDQ1W_CTRL_IP_RESETVAL (0x00000000u)

/*----IP Tokens----*/
/** Token to indicate that initialization pulse is sent*/
#define CSL_HDQ1W_HDQ1W_CTRL_IP_DONE     (0x00000000u)
/** Token to send initialization pulse*/
#define CSL_HDQ1W_HDQ1W_CTRL_IP_INITPULSE (0x00000001u)

/** Read/write bit field mask*/
#define CSL_HDQ1W_HDQ1W_CTRL_RWB_MASK    (0x00000002u)
/** Read/write bit field shift*/
#define CSL_HDQ1W_HDQ1W_CTRL_RWB_SHIFT   (0x00000001u)
/** Read/write bit field reset value*/
#define CSL_HDQ1W_HDQ1W_CTRL_RWB_RESETVAL (0x00000000u)

/*----RWB Tokens----*/
/** Token for write mode*/
#define CSL_HDQ1W_HDQ1W_CTRL_RWB_WR      (0x00000000u)
/** Token for read mode*/
#define CSL_HDQ1W_HDQ1W_CTRL_RWB_RD      (0x00000001u)

/** HDQ/1-Wire mode bit field mask*/
#define CSL_HDQ1W_HDQ1W_CTRL_MODE_MASK   (0x00000001u)
/** HDQ/1-Wire mode bit field shift*/
#define CSL_HDQ1W_HDQ1W_CTRL_MODE_SHIFT  (0x00000000u)
/** HDQ/1-Wire mode bit field reset value*/
#define CSL_HDQ1W_HDQ1W_CTRL_MODE_RESETVAL (0x00000000u)

/*----MODE Tokens----*/
/** Token for HDQ mode*/
#define CSL_HDQ1W_HDQ1W_CTRL_MODE_HDQ    (0x00000000u)
/** Token for 1-Wire mode*/
#define CSL_HDQ1W_HDQ1W_CTRL_MODE_1WIRE  (0x00000001u)

/** Control register reset value*/
#define CSL_HDQ1W_HDQ1W_CTRL_RESETVAL    (0x00000000u)

/* HDQ1W_INTS */

/** Transmit complete status field mask*/
#define CSL_HDQ1W_HDQ1W_INTS_TC_MASK     (0x00000004u)
/** Transmit complete status field shift*/
#define CSL_HDQ1W_HDQ1W_INTS_TC_SHIFT    (0x00000002u)
/** Transmit complete status field reset value*/
#define CSL_HDQ1W_HDQ1W_INTS_TC_RESETVAL (0x00000000u)

/** Receive complete status field mask*/
#define CSL_HDQ1W_HDQ1W_INTS_RC_MASK     (0x00000002u)
/** Receive complete status field shift*/
#define CSL_HDQ1W_HDQ1W_INTS_RC_SHIFT    (0x00000001u)
/** Receive complete status field reset value*/
#define CSL_HDQ1W_HDQ1W_INTS_RC_RESETVAL (0x00000000u)

/** Slave detect/read timeout bit field mask*/
#define CSL_HDQ1W_HDQ1W_INTS_DTO_MASK    (0x00000001u)
/** Slave detect/read timeout bit field shift*/
#define CSL_HDQ1W_HDQ1W_INTS_DTO_SHIFT   (0x00000000u)
/** Slave detect/read timeout bit field reset value*/
#define CSL_HDQ1W_HDQ1W_INTS_DTO_RESETVAL (0x00000000u)

/** Interrupt status register reset value*/
#define CSL_HDQ1W_HDQ1W_INTS_RESETVAL    (0x00000000u)

#ifdef __cplusplus
}
#endif

#endif