csl_i2caux.h

dsp在音频处理中的运用

#ifndef _CSL_I2CAUX_H
#define _CSL_I2CAUX_H

#ifdef __cplusplus
extern "C" {
#endif

/* Enable the I2C */
static inline
void
	CSL_i2cEnable (
		CSL_I2cHandle                         hI2c
)
{
	CSL_FINS(hI2c->regs->CON,I2C_CON_I2C_EN, 0x1u);
}

/* Disable the I2C */
static inline
void
	CSL_i2cDisable (
		CSL_I2cHandle                         hI2c
)
{
	CSL_FINS(hI2c->regs->CON,I2C_CON_I2C_EN, 0x0u);
}

/* Software command to the I2C */
static inline
void
	CSL_i2cReset (
		CSL_I2cHandle                         hI2c
)
{

	CSL_FINS(hI2c->regs->SYSC,I2C_SYSC_SRST, 0x1u);
}

/* Clear the status bits. Multiple status bits can be cleared. */
static inline
void
	CSL_i2cClearStatus (
		CSL_I2cHandle                         hI2c,
		Uint16								  mask
)
{
	Uint16 temp_stat=0x0;

	   /* BUG FIX for compilation issues (SDSsq32003). The genarted code
	      causes bus error for certain ioport reads. Now, the STAT reg is
	      read once and written back only once at the end  */

	   if(mask & CSL_I2C_CLEAR_AL)
			temp_stat = temp_stat | CSL_FMK(I2C_STAT_AL, 1) ; /* Writing 1 clears the bit. */
	   if(mask & CSL_I2C_CLEAR_NACK)
			temp_stat = temp_stat | CSL_FMK(I2C_STAT_NACK, 1) ;/* Writing 1 clears the bit. */
	   if(mask & CSL_I2C_CLEAR_ARDY)
  		    temp_stat = temp_stat | CSL_FMK(I2C_STAT_ARDY, 1) ;/* Writing 1 clears the bit. */
	   if(mask & CSL_I2C_CLEAR_RRDY)
			temp_stat = temp_stat | CSL_FMK(I2C_STAT_RRDY, 1) ;/* Writing 1 clears the bit. */
	   if(mask & CSL_I2C_CLEAR_XRDY)
			temp_stat = temp_stat | CSL_FMK(I2C_STAT_XRDY, 1) ;/* Writing 1 clears the bit. */
	   if(mask & CSL_I2C_CLEAR_GC)
			temp_stat = temp_stat | CSL_FMK(I2C_STAT_GC, 1) ;/* Writing 1 clears the bit. */

       hI2c->regs->STAT = temp_stat & 0x3F;
}

/* Set the address of the Slave device  */
static inline
void
	CSL_i2cSlaveAddr (
		CSL_I2cHandle                         hI2c,
		Uint16								  addr
)
{

	hI2c->regs->SA = addr & 0x3FF;
}

/* Set the Data Count */
static inline
void
	CSL_i2cDataCount (
		CSL_I2cHandle                         hI2c,
		Uint16								  count
)
{

	hI2c->regs->CNT = count & 0xFFFF;
}

/* Set the start condition */
static inline
void
	CSL_i2cStart (
		CSL_I2cHandle                         hI2c
)
{
	CSL_FINS(hI2c->regs->CON,I2C_CON_STT, 0x1u);
}

/* Set the stop condition */
static inline
void
	CSL_i2cStop (
		CSL_I2cHandle                         hI2c
)
{
	CSL_FINS(hI2c->regs->CON,I2C_CON_STP, 0x1u);

}

/* Set the transmission mode */
static inline
void
	CSL_i2cTransmitMode (
		CSL_I2cHandle                         hI2c
)
{
	CSL_FINS(hI2c->regs->CON,I2C_CON_TRX,0x1u);
}

/* Set the receiver mode */
static inline
void
	CSL_i2cReceiveMode (
		CSL_I2cHandle                         hI2c
)
{
	CSL_FINS(hI2c->regs->CON,I2C_CON_TRX,0x0u);
}

/* Set the Master mode of operation */
static inline
void
	CSL_i2cMasterMode (
		CSL_I2cHandle                         hI2c
)
{

		CSL_FINS(hI2c->regs->CON,I2C_CON_MST,0x1u);
}

/* Set the Slave mode of operation */
static inline
void
	CSL_i2cSlaveMode (
		CSL_I2cHandle                         hI2c
)
{

		CSL_FINS(hI2c->regs->CON,I2C_CON_MST,0x0u);
}

/* Get current clock setup parameters */
static inline
void
	CSL_i2cGetClockSetup (
		CSL_I2cHandle                         hI2c,
		CSL_I2cClkSetup						 *clksetup
)
{
	clksetup->prescalar = CSL_FEXT(hI2c->regs->PSC,I2C_PSC_PSC);
  	clksetup->clklowdiv = CSL_FEXT(hI2c->regs->SCLL,I2C_SCLL_SCLL);
  	clksetup->clkhighdiv = CSL_FEXT(hI2c->regs->SCLH,I2C_SCLH_SCLH);

}

/* Get the Bus Busy status information */
static inline
Uint16
	CSL_i2cGetBusBusy (
		CSL_I2cHandle                         hI2c
)
{
	return CSL_FEXT(hI2c->regs->STAT,I2C_STAT_BB);
}

/* Get the Receive Ready status information */
static inline
Uint16
	CSL_i2cGetRxReady (
		CSL_I2cHandle                         hI2c
)
{
	return CSL_FEXT(hI2c->regs->STAT,I2C_STAT_RRDY);
}

/* Get the Transmit Ready status information */
static inline
Uint16
	CSL_i2cGetTxReady (
		CSL_I2cHandle                         hI2c
)
{
	return CSL_FEXT(hI2c->regs->STAT,I2C_STAT_XRDY);
}

/* Get the Register Ready status information */
static inline
Uint16
	CSL_i2cGetAccessReady (
		CSL_I2cHandle                         hI2c
)
{
	return CSL_FEXT(hI2c->regs->STAT,I2C_STAT_ARDY);
}

/* Get the Single Byte Data bit information */
static inline
Uint16
	CSL_i2cGetSingleByteData (
		CSL_I2cHandle                         hI2c
)
{
	return CSL_FEXT(hI2c->regs->STAT,I2C_STAT_SBD);
}

/* Get the Receive overflow status information */
static inline
Uint16
	CSL_i2cGetRxOverrun (
		CSL_I2cHandle                         hI2c
)
{
	return CSL_FEXT(hI2c->regs->STAT,I2C_STAT_ROVR);
}

/* Get the Transmit underflow status information */
static inline
Uint16
	CSL_i2cGetTxUnderflow (
		CSL_I2cHandle                         hI2c
)
{
	return CSL_FEXT(hI2c->regs->STAT,I2C_STAT_XUDF);
}

/* Get the Arbitration Lost status information */
static inline
Uint16
	CSL_i2cGetArbLost (
		CSL_I2cHandle                         hI2c
)
{
	return CSL_FEXT(hI2c->regs->STAT,I2C_STAT_AL);
}

/* Get the No Acknowledge status information */
static inline
Uint16
	CSL_i2cGetNoAck (
		CSL_I2cHandle                         hI2c
)
{
	return CSL_FEXT(hI2c->regs->STAT,I2C_STAT_NACK);
}



/* Get the Reset Done status bit information */
static inline
Uint16
	CSL_i2cGetResetDone (
		CSL_I2cHandle                         hI2c
)
{
	return CSL_FEXT(hI2c->regs->SYSS,I2C_SYSS_RDONE);
}

#ifdef __cplusplus
}
#endif


#endif