cslr_cfc.h

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/** ============================================================================
 *   @file  cslr_cfc.h
 *
 *   @path  $(CSLPATH)\arm\cfc\inc
 *
 *   @desc  Register layer header file for CFC CSL
 *
 */
 
/*  ============================================================================
 *   Copyright (c) Texas Instruments Inc 2002, 2003, 2004
 *
 *   Use of this software is controlled by the terms and conditions found in the
 *   license agreement under which this software has been supplied.
 *   ===========================================================================
 */
 
/*  @(#) PSP/CSL 3.00.01.00[5912] (2004-05-15)  */

/* =============================================================================
 *  Revision History
 *  ===============
 *  15-May-2004 sks File Created.
 *
 * =============================================================================
 */

#ifndef _CSLR_CFC_H_
#define _CSLR_CFC_H_

#include <cslr.h>
#include <tistdtypes.h>

/**
 * Register Overlay Structure
 */
typedef struct  {
    /** CFC status register */
    volatile Uint16 STATUS_REG;
    /** CFC configuration register */
    volatile Uint16 CFG_REG1;
    /** CFC control register */
    volatile Uint16 CNTRL_REG;
} CSL_CfcRegs;

/**
 *  This data type is defined as a pointer to an object of type CSL_CfcRegs. 
 *  The data type is used to map CompactFlash Controller registers to a 'C' 
 *  structure. An object of this data type is used to access CompactFlash 
 *  Controller registers.
 */
 typedef volatile CSL_CfcRegs*   CSL_CfcRegsOvly;

/**
 * Register Id's
 */
typedef enum  {
    /** CFC status register ID */
    CSL_CFC_STATUS_REG = 0x0000u,
    /** CFC configuration register ID */
    CSL_CFC_CFG_REG1 = 0x0004u,
    /** CFC control register ID */
    CSL_CFC_CNTRL_REG = 0x0008u
} CSL_CfcRegIds;

/**************************************************************************\
* Field Definition Macros
\**************************************************************************/

/* STATUS_REG */

/** Mask for Last read access bit */
#define CSL_CFC_STATUS_REG_LAST_RD_ACCESS_MASK (0x00000004u)

/** Shift required for Last read access bit */
#define CSL_CFC_STATUS_REG_LAST_RD_ACCESS_SHIFT (0x00000002u)

/** Reset value for Last read access */
#define CSL_CFC_STATUS_REG_LAST_RD_ACCESS_RESETVAL (0x00000001u)

/** Last read access is bad */
#define CSL_CFC_STATUS_REG_LAST_RD_ACCESS_ERR (0x00000000u)

/** Last read access is good */
#define CSL_CFC_STATUS_REG_LAST_RD_ACCESS_OK (0x00000001u)


/** Mask for Last write access bit */
#define CSL_CFC_STATUS_REG_LAST_WR_ACCESS_MASK (0x00000002u)

/** Shift required for Last write access bit */
#define CSL_CFC_STATUS_REG_LAST_WR_ACCESS_SHIFT (0x00000001u)

/** Reset value for Last write access */
#define CSL_CFC_STATUS_REG_LAST_WR_ACCESS_RESETVAL (0x00000001u)

/** Last write access is bad */
#define CSL_CFC_STATUS_REG_LAST_WR_ACCESS_ERR (0x00000000u)

/** Last write access is good */
#define CSL_CFC_STATUS_REG_LAST_WR_ACCESS_OK (0x00000001u)

/** Mask for Card detect bit */
#define CSL_CFC_STATUS_REG_CARD_DETECT_MASK (0x00000001u)

/** Shift required for Card detect bit */
#define CSL_CFC_STATUS_REG_CARD_DETECT_SHIFT (0x00000000u)

/** Reset value for Card detect bit */
#define CSL_CFC_STATUS_REG_CARD_DETECT_RESETVAL (0x00000000u)

/** Card is connceted properly */
#define CSL_CFC_STATUS_REG_CARD_DETECT_SUCCESSFUL (0x00000000u)

/** Card is not connected properly */
#define CSL_CFC_STATUS_REG_CARD_DETECT_FAILURE (0x00000001u)

/** Reset value for CFC Status register */
#define CSL_CFC_STATUS_REG_RESETVAL      (0x0000FFFEu)


/* CFG_REG1 */

/** Mask for Chip Select 3 */
#define CSL_CFC_CFG_REG1_CS3_CFG_MASK    (0x00000008u)

/** Shift for Chip Select 3 */
#define CSL_CFC_CFG_REG1_CS3_CFG_SHIFT   (0x00000003u)

/** Reset value for Chip Select 3*/
#define CSL_CFC_CFG_REG1_CS3_CFG_RESETVAL (0x00000001u)

/** Chip Select 3 is enabled */
#define CSL_CFC_CFG_REG1_CS3_CFG_ENABLED (0x00000000u)

/** Chip Select 3 is disabled */
#define CSL_CFC_CFG_REG1_CS3_CFG_DISABLED (0x00000001u)

/** Mask for Chip Select 2 */
#define CSL_CFC_CFG_REG1_CS2_CFG_MASK    (0x00000004u)

/** Shift for Chip Select 2 */
#define CSL_CFC_CFG_REG1_CS2_CFG_SHIFT   (0x00000002u)

/** Reset value for Chip Select 2 */
#define CSL_CFC_CFG_REG1_CS2_CFG_RESETVAL (0x00000001u)

/** Chip Select 2 is enabled */
#define CSL_CFC_CFG_REG1_CS2_CFG_ENABLED (0x00000000u)

/** Chip Select 2 is disabled */
#define CSL_CFC_CFG_REG1_CS2_CFG_DISABLED (0x00000001u)

/** Mask for Chip Select 1 */
#define CSL_CFC_CFG_REG1_CS1_CFG_MASK    (0x00000002u)

/** Shift for Chip Select 1 */
#define CSL_CFC_CFG_REG1_CS1_CFG_SHIFT   (0x00000001u)

/** Reset value for Chip Select 1 */
#define CSL_CFC_CFG_REG1_CS1_CFG_RESETVAL (0x00000001u)

/** Chip Select 1 is enabled*/
#define CSL_CFC_CFG_REG1_CS1_CFG_ENABLED (0x00000000u)

/** Chip Select 1 is disabled */
#define CSL_CFC_CFG_REG1_CS1_CFG_DISABLED (0x00000001u)

/** Mask for Chip Select 0 */
#define CSL_CFC_CFG_REG1_CS0_CFG_MASK    (0x00000001u)

/** Shift for Chip Select 0 */
#define CSL_CFC_CFG_REG1_CS0_CFG_SHIFT   (0x00000000u)

/** Reset value for Chip Select 0 */
#define CSL_CFC_CFG_REG1_CS0_CFG_RESETVAL (0x00000001u)

/** Chip Select 0 is enabled */
#define CSL_CFC_CFG_REG1_CS0_CFG_ENABLED (0x00000000u)

/** Chip Select 0 is disabled */
#define CSL_CFC_CFG_REG1_CS0_CFG_DISABLED (0x00000001u)

/** Reset value for CFC configuration register */
#define CSL_CFC_CFG_REG1_RESETVAL        (0x0000FFFFu)


/* CNTRL_REG */

/** Mask for card reset bit */
#define CSL_CFC_CNTRL_REG_CARD_RESET_MASK (0x00000001u)

/** Shift for card reset bit */
#define CSL_CFC_CNTRL_REG_CARD_RESET_SHIFT (0x00000000u)

/** Reset value for card reset bit */
#define CSL_CFC_CNTRL_REG_CARD_RESET_RESETVAL (0x00000000u)

/** CompactFlash is held in reset */
#define CSL_CFC_CNTRL_REG_CARD_RESET_ON (0x00000000u)

/** CompactFlash is not in reset */
#define CSL_CFC_CNTRL_REG_CARD_RESET_OFF (0x00000001u)

/** Reset value for CFC control register */
#define CSL_CFC_CNTRL_REG_RESETVAL       (0x00000000u)

#endif /* _CSLR_CFC_H_ */