csl_mmu.h

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/** ============================================================================
 *   @file  csl_mmu.h
 *
 *   @path  $(CSLPATH)\arm\mmu\inc
 *
 *   @desc  API header file for MMU CSL
 *
 */

/*  ============================================================================
 *   Copyright (c) Texas Instruments Inc 2002, 2003, 2004
 *
 *   Use of this software is controlled by the terms and conditions found in the
 *   license agreement under which this software has been supplied.
 *   ===========================================================================
 */
 
/*  @(#) PSP/CSL 3.00.01.00[5912] (2004-04-18)  */

/* =============================================================================
 *  Revision History
 *  ===============
 *  26-Apr-2004 ar File Created.
 *  22-Jun-2004 ar Made modifications to support changes in CSL architecture
 *
 * =============================================================================
 */

#ifndef _CSL_MMU_H_
#define _CSL_MMU_H_

#ifdef __cplusplus
extern "C" {
#endif

#include <csl_error.h>
#include <csl_types.h>
#include <_csl_mmu.h>

/**
 *  MMU global typedef declarations
 */
 
/**
 * @brief   Enumeration of the control commands
 *
 * These are the control commands that could be used with
 * CSL_mmuHwControl(..). Some of the commands expect an
 * argument as documented along-side the description of
 * the command.
 *
 */
typedef enum {
        /**<
         * @brief   Set Translation table base
         * @param   (Uint32 *)
         */
    CSL_MMU_CMD_SET_TTB                                = 0,
        /**<
         * @brief   Enable MMU
         * @param   None
         */
    CSL_MMU_CMD_MMU_ENABLE                             = 1,
        /**<
         * @brief   Disable MMU
         * @param   None
         */
    CSL_MMU_CMD_MMU_DISABLE                            = 2,
        /**<
         * @brief   Enable alignment checking
         * @param   None
         */
    CSL_MMU_CMD_ALIGN_CHECK_ENABLE                     = 3,
        /**<
         * @brief   Disable alignment checking
         * @param   None
         */
    CSL_MMU_CMD_ALIGN_CHECK_DISABLE                    = 4,
        /**<
         * @brief   Set domain access permissions
         * @param   (CSL_MmuDomainAccess *)
         */
    CSL_MMU_CMD_SET_DOMAIN_ACCESS                      = 5,
        /**<
         * @brief   Set Values for protection bits (S and R bits)
         * @param   (CSL_MmuProtectionMode *)
         */                    
    CSL_MMU_CMD_SET_PROTECTION_MODE                    = 6,
        /**<
         * @brief   Invalidate TLB
         * @param   None
         */
    CSL_MMU_CMD_INV_TLB                                = 7,
        /**<
         * @brief   Invalidate TLB entry
         * @param   (Uint32 *)
         */
    CSL_MMU_CMD_INV_TLB_ENTRY                          = 8,
        /**<
         * @brief   TLB lockdown control
         * @param   (CSL_MmuTlbLockDesc *)
         */
    CSL_MMU_CMD_LOCKDOWN_CONTROL                       = 9
} CSL_MmuHwControlCmd;

/**
 * @brief   Enumeration of the queries
 *
 * These are the queries that could be used with CSL_mmuGetHwStatus(..).
 * The queries return a value through the object pointed to by the pointer
 * that it takes as an argument. The argument supported by the query is
 * documented along-side the description of the query.
 */
typedef enum {
        /**<
         * @brief   Query translation table base register
         * @param   (Uint32 *)
         */
    CSL_MMU_QUERY_TTB                          = 0,
        /**<
         * @brief   Query MMU enable/disable status
         * @param   (Bool *)
         */
    CSL_MMU_QUERY_MMU_STATUS                   = 1,
        /**<
         * @brief   Query Alignment check enable/disable status
         * @param   (Bool *)
         */
    CSL_MMU_QUERY_ALIGN_CHECK_STATUS           = 2,
        /**<
         * @brief   Query Data fault status register
         * @param   (Uint32 *)
         */
    CSL_MMU_QUERY_DATA_FAULT_STATUS            = 3,
        /**<
         * @brief   Query instruction fault status register
         * @param   (Uint32 *)
         */
    CSL_MMU_QUERY_INS_FAULT_STATUS             = 4,
        /**<
         * @brief   Query fault address register
         * @param   (Uint32 *)
         */
    CSL_MMU_QUERY_FAULT_ADDRESS                = 5,
        /**<
         * @brief   Query value of protection bits (S and R bits)
         * @param   (CSL_MmuProtectionMode *)
         */
    CSL_MMU_QUERY_PROTECTION_MODE              = 6,
        /**<
         * @brief   Query domain access register
         * @param   (Uint32 *)
         */
    CSL_MMU_QUERY_DOMAIN_ACCESS                = 7
} CSL_MmuHwStatusQuery;

/**
 *  Enumeration for MMU domain access permissions
 */
typedef enum {
    /** No access to the domain */
    CSL_MMU_DOMAIN_ACCESS_NO            = 0,
    /** Permission check needs to be performed to access the domain */
    CSL_MMU_DOMAIN_ACCESS_CLIENT        = 1,
    /** No permission check needed to accessthe domain */
    CSL_MMU_DOMAIN_ACCESS_MANAGER       = 3
} CSL_MmuDomainAccess;

/**
 *  Enumeration for MMU protection modes to set R and S bits
 *  in system control coprocessor control register.When the access
 *  protection field in descriptor has value CSL_MMU_PAGE_ACCESS_MODE_00
 *  the value for S and R bit decides the access to the page based
 *  on the mode(user mode/privileged mode 
 */
typedef enum {
    /** 
	 * R = 0, S =0.
	 * Privileged mode -  No access
	 * User mode       -  No access
	 * 
	 */
    CSL_MMU_PROTECTION_MODE_00          = 0,

   /** 
	 * R = 0, S =1.
	 * Privileged mode -  Read only
	 * User mode       -  No access
	 * 
	 */
    CSL_MMU_PROTECTION_MODE_01          = 1,

   /** 
	 * R = 1, S =0.
	 * Privileged mode - Read only
	 * User mode       - Read only
	 * 
	 */
    CSL_MMU_PROTECTION_MODE_10          = 2,
   /** 
	 * R = 1, S =1.
	 * Privileged mode - Undefined
	 * User mode       - Undefined
	 * 
	 */
    CSL_MMU_PROTECTION_MODE_11          = 3
} CSL_MmuProtectionMode;

/**
 *  Level2 Coarse/Fine Page Table Descriptor Type
 */
typedef enum {
    /** No valid page table entry */
    CSL_MMU_L2_DESC_FAULT             = 0,
    /** Large page base address (64 KB) */
    CSL_MMU_L2_DESC_LP                = 1,
    /** Small page base address (4 KB)*/
    CSL_MMU_L2_DESC_SP                = 2,
    /** Tiny page base address (1KB)*/
    CSL_MMU_L2_DESC_TP                = 3
} CSL_MmuL2DescType;

/** Level1 Translation Table Descriptor Type
 *
 */
typedef enum {
    /** No valid page table entry */
    CSL_MMU_L1_DESC_FAULT             = 0,
    /** Coarse page table base address(256 entry table) */
    CSL_MMU_L1_DESC_CPT               = 1,
    /** Section base address(1MB) */
    CSL_MMU_L1_DESC_SECTION           = 2,
    /** Fine page table base address (1024 entry table)*/
    CSL_MMU_L1_DESC_FPT               = 3
} CSL_MmuL1DescType;

/**
 * Enumeration for page access modes.This value along
 * the value for the S and R bits in system control coprocessor
 * control register (c1)decides the No access/read/write permission
 * in user mode and privileged mode 
 */
typedef enum {
    /** 
	 * No write access, read depends on S and R bits and mode 
	 *      S     R            Privileged mode       User mode  
     *      0     0            No access             No access
	 *      1     0            Read only             No access
	 *      0     1            Read only             Read only      
	 *      1     1            Unpredictable         Unpredictable
	 */
    CSL_MMU_PAGE_ACCESS_MODE_00           = 0,
    /** 
	 * No access/Read/write based on mode, independent of S and R bits
	 * Privileged mode - Read/write
	 * User mode       - No access
	 */
    CSL_MMU_PAGE_ACCESS_MODE_01           = 1,
    /** 
	 * Read/write based on mode, independent of S and R bits 
	 * Privileged mode - Read/write
	 * User mode       - Read only
	 */
    CSL_MMU_PAGE_ACCESS_MODE_10           = 2,
    /** 
	 * 
	 * Read/write in both modes independent of S and R bits 
	 * Privileged mode - Read/write
	 * User mode       - Read/write
	 */
    CSL_MMU_PAGE_ACCESS_MODE_11           = 3
} CSL_MmuPageAccessMode;

/**
 *  Level2 Coarse/Fine Page Table Entry
 */
typedef struct CSL_MmuL2Descriptor {
    /** Start address of level 2page table */
    Uint32                 level2TableAddress;
    /** Physical address corresponding to the entry */
    Uint32                 phyAddr;
    /** Virtual address corresponding to the entry */
    Uint32                 virtualAddr;
    /** Level 1 descriptor type */
    CSL_MmuL2DescType      descType;
    /** Whether the section described by the entry is cacheable */
    Bool                   cacheable;
    /** Whether the section described by the entry is bufferable */
    Bool                   bufferable;
    /** Access permission for the first subpage */
    CSL_MmuPageAccessMode   accessProtection0;
    /** Access permission for the second subpage */
    CSL_MmuPageAccessMode   accessProtection1;
   /** Access permission for the third subpage */
    CSL_MmuPageAccessMode   accessProtection2;
   /** Access permission for the fourth subpage */
    CSL_MmuPageAccessMode   accessProtection3;
} CSL_MmuL2Descriptor;


/**
 *  Level 1 Translation Table Entry
 */
typedef struct CSL_MmuL1Descriptor {
    /** Translation table base address */
    Uint32                 ttbAddr;
    /** Physical address corresponding to the entry */
    Uint32                 phyAddr;
    /** Virtual address corresponding to the entry */
    Uint32                 virtualAddr;
    /** Level 2 descriptor type */
    CSL_MmuL1DescType      descType;
    /** Domain Number */
    Uint16                 domainNumber;
    /** Whether the section described by the entry is cacheable */
    Bool                   cacheable;
    /** Whether the section described by the entry is bufferable */
    Bool                   bufferable;
    /** Access permission for section */
    CSL_MmuPageAccessMode  accessProtection;
} CSL_MmuL1Descriptor;

/**
 *  Structure used as argument to domain access setting command
 */
typedef struct CSL_MmuDomainAccessDesc {
    /** Domain number */
    Uint16                domainNumber;
   /** Access conditon for the domain */
    CSL_MmuDomainAccess   access;
} CSL_MmuDomainAccessDesc;

/**
 *  Structure used as argument to TLB lock command
 */
typedef struct CSL_MmuTlbLockDesc {
    /** Whether to set the preserve bit in the TLB locdown control register */
     Bool           preserve;
    /** victim counter value for the entry */
     Uint16         victim;
} CSL_MmuTlbLockDesc;

/**
 *   MMU data object
 */
/** @brief This object contains the reference to the instance of MMU opened
 *  using the @a CSL_mmuOpen().