csl_dma.h
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LCHP_SHARES_PCH01 = 2, /**< LCh-P dynamically shares PCh-0 and -1 */
LCHPD_ASSIGNED_PCH2 = 7 /**< LCh-PD PCh-2 */
} CSL_DmaLchType;
/** @brief Enumerations for both error and status events
* of a channel
*
*/
typedef enum {
CSL_DMA_TIMEOUT_EVENT = CSL_FMK(DMA_CICR_TIMEOUTIE,1), /**< Time-out in the channel */
CSL_DMA_DROP_EVENT = CSL_FMK(DMA_CICR_DROPIE,1), /**< Sync Event drop during transfer */
CSL_DMA_HALF_FRAME_EVENT = CSL_FMK(DMA_CICR_FIRSTHALFIE,1), /**< First half of current frame transferred */
CSL_DMA_FRAME_EVENT = CSL_FMK(DMA_CICR_FRAMEIE,1), /**< A complete frame has been transferred */
CSL_DMA_LAST_FRAME_EVENT = CSL_FMK(DMA_CICR_LASTIE,1), /**< Transfer of last frame has started */
CSL_DMA_END_BLOCK_EVENT = CSL_FMK(DMA_CICR_BLOCKIE,1) /**< Current transfer in the channel has finished */
} CSL_DmaEvents;
/** @brief Enumerations for End of Programming Status bit of the channel
*
*/
typedef enum {
CSL_DMA_OMAP31_COMPATABILITY = 0, /**< Logical Channel is in OMAP3.0/3.1 compatible mode */
CSL_DMA_OMAP32_COMPATABILITY = 1 /**< Logical Channel is in OMAP3.2 Compatible mode */
} CSL_DmaCompatability;
/** @brief Enumerations for End of Programming Status bit of the channel
*
*/
typedef enum {
CSL_DMA_ENDPROG_DISABLE = 0, /**< When auto-init is set and repeat not set auto-init
delayed till ENDPROG is ENABLED. */
CSL_DMA_ENDPROG_ENABLE = 1 /**< In auto-init mode channel reinitialized after current transfer */
} CSL_DmaEndProg;
/** @brief Enumerations for Repetitive operation of the channel
*
*/
typedef enum {
CSL_DMA_REPEAT_DISABLE = 0, /**< When DMA is in auto-init mode and end_prog=0 channel automatically
reinitializes itself once the current transfer is complete */
CSL_DMA_REPEAT_ENABLE = 1 /**< When DMA is in auto-init mode and end_prog=0 channel automatically
reinitializes itself once the current transfer is complete */
} CSL_DmaRepeat;
/** @brief Enumerations for Auto-Initialization Mode of the channel
*
*/
typedef enum {
CSL_DMA_AUTOINIT_DISABLE = 0, /**< Channel stops at the end of current transfer */
CSL_DMA_AUTOINIT_ENABLE = 1 /**< After current transfer is complete, channel automatically reinitializes
itself if REPEAT or ENDPROG is ENABLE. */
} CSL_DmaAutoInit;
/** @brief Enumerations for Priority of channel
*
*/
typedef enum {
CSL_DMA_PRIORITY_LOW = 0, /**< Logical channel has the lowest priority level */
CSL_DMA_PRIORITY_HIGH = 1 /**< Logical channel has the highest priority level */
} CSL_DmaPriority;
/** @brief Enumerations for Frame Synchronization
*
*/
typedef enum {
CSL_DMA_FS_DISABLE = 0, /**< An entire block is sent if Block_Sync is set
else an element is transferred each time a DMA request is made */
CSL_DMA_FS_ENABLE = 1 /**< An entire frame is transferred each time a DMA request is made */
} CSL_DmaFS;
/** @brief Enumerations for Hardware synchronization
*
*/
typedef enum {
CSL_DMA_SYNC_NONE = 0,
CSL_DMA_MCSI1_TX = 1,
CSL_DMA_SYNC_EVT1 = 1,
CSL_DMA_MCSI1_RX = 2,
CSL_DMA_SYNC_EVT2 = 2,
CSL_DMA_I2C_RX = 3,
CSL_DMA_SYNC_EVT3 = 3,
CSL_DMA_I2C_TX = 4,
CSL_DMA_SYNC_EVT4 = 4,
CSL_DMA_EXT_DMA_NREQ1 = 5,
CSL_DMA_SYNC_EVT5 = 5,
CSL_DMA_EXT_DMA_NREQ2 = 6,
CSL_DMA_SYNC_EVT6 = 6,
CSL_DMA_UWIRE_TX = 7,
CSL_DMA_SYNC_EVT7 = 7,
CSL_DMA_MCBSP1_TX = 8,
CSL_DMA_SYNC_EVT8 = 8,
CSL_DMA_MCBSP1_RX = 9,
CSL_DMA_SYNC_EVT9 = 9,
CSL_DMA_MCBSP3_TX = 10,
CSL_DMA_SYNC_EVT10 = 10,
CSL_DMA_MCBSP3_RX = 11,
CSL_DMA_SYNC_EVT11 = 11,
CSL_DMA_UART1_TX = 12,
CSL_DMA_SYNC_EVT12 = 12,
CSL_DMA_UART1_RX = 13,
CSL_DMA_SYNC_EVT13 = 13,
CSL_DMA_UART2_TX = 14,
CSL_DMA_SYNC_EVT14 = 14,
CSL_DMA_UART2_RX = 15,
CSL_DMA_SYNC_EVT15 = 15,
CSL_DMA_MCBSP2_TX = 16,
CSL_DMA_SYNC_EVT16 = 16,
CSL_DMA_MCBSP2_RX = 17,
CSL_DMA_SYNC_EVT17 = 17,
CSL_DMA_UART3_TX = 18,
CSL_DMA_SYNC_EVT18 = 18,
CSL_DMA_UART3_RX = 19,
CSL_DMA_SYNC_EVT19 = 19,
CSL_DMA_CAM_IF_RX = 20,
CSL_DMA_SYNC_EVT20 = 20,
CSL_DMA_MMCSDIO1_TX = 21,
CSL_DMA_SYNC_EVT21 = 21,
CSL_DMA_MMCSDIO1_RX = 22,
CSL_DMA_SYNC_EVT22 = 22,
CSL_DMA_NAND_FLASH_END_BURST = 23,
CSL_DMA_SYNC_EVT23 = 23,
CSL_DMA_IRQ_LCD_LINE = 24,
CSL_DMA_SYNC_EVT24 = 24,
CSL_DMA_MEMSTICK = 25,
CSL_DMA_SYNC_EVT25 = 25,
CSL_DMA_USB_W2FC_RX0 = 26,
CSL_DMA_SYNC_EVT26 = 26,
CSL_DMA_USB_W2FC_RX1 = 27,
CSL_DMA_SYNC_EVT27 = 27,
CSL_DMA_USB_W2FC_RX2 = 28,
CSL_DMA_SYNC_EVT28 = 28,
CSL_DMA_USB_W2FC_TX0 = 29,
CSL_DMA_SYNC_EVT29 = 29,
CSL_DMA_USB_W2FC_TX1 = 30,
CSL_DMA_SYNC_EVT30 = 30,
CSL_DMA_USB_W2FC_TX2 = 31,
CSL_DMA_SYNC_EVT31 = 31
} CSL_DmaSync;
/** @brief Enumerations for Element size
*
*/
typedef enum {
CSL_DMA_DATASIZE_8BIT = 0, /**< 8 bits scalar */
CSL_DMA_DATASIZE_16BIT = 1, /**< 16 bits scalar */
CSL_DMA_DATASIZE_32BIT = 2 /**< 32 bits scalar */
} CSL_DmaDataType;
/** @brief Enumerations for the Channel Control Setup
*
*/
typedef struct CSL_DmaSetupChaCtrl {
CSL_DmaSync sync; /**< Hardware Synchronization Events */
CSL_DmaFS fs; /**< Frame Synchronization Setting */
CSL_DmaPriority priority; /**< Channel Priority Setting */
CSL_DmaAutoInit autoinit; /**< Channel Auto-Initialization feature */
CSL_DmaEndProg endprog; /**< Channel End Programmation feature */
CSL_DmaRepeat repeat; /**< Channel Repeat feature */
CSL_DmaCompatability compatability; /**< Channel Compatability feature */
}CSL_DmaSetupChaCtrl;
/** @brief Channel Setup Structure
*
*/
typedef struct CSL_DmaSetupChannel {
CSL_DmaDataType datatype; /**< Size of data transferred in the Channels */
Uint16 interruptMask; /**< Bit-wise OR of the @a #CSL_DmaEvents data type */
Uint16 elementCount; /**< Number of elements in a frame */
Uint16 frameCount; /**< Number of frames in a block */
CSL_DmaLchType lchType; /**< Logical Channel assignment relationship to physical channels */
CSL_DmaLchInterleave lchInterleave; /**< Synchronized logical channel interleave mode setting */
CSL_DmaSetupChaCtrl *chaCtrlSetup; /**< Pointer to @a #CSL_DmaSetupChaCtrl structure */
CSL_DmaSetupLchLink *lchLinkSetup; /**< Pointer to @a #CSL_DmaSetupLchLink structure */
CSL_DmaSetupGraphic *graphicSetup; /**< Pointer to @a #CSL_DmaSetupGraphic structure */
} CSL_DmaSetupChannel;
/** @brief Enumerations for Addressing mode
*
*/
typedef enum {
CSL_DMA_AMODE_CONSTANT = 0, /**< Constant Addressing Mode */
CSL_DMA_AMODE_POST_INCREMENT = 1, /**< Post Increment Addressing Mode */
CSL_DMA_AMODE_SINGLE_INDEX = 2, /**< Single Index Addressing Mode */
CSL_DMA_AMODE_DOUBLE_INDEX = 3 /**< Double Index Addressing Mode */
} CSL_DmaAmode;
/** @brief Enumerations for Type of port which is the source or destination port of a channel
*
*/
typedef enum {
CSL_DMA_PORT_SDRAM = 0, /**< SDRAM Port : also aliased as EMIFF Port */
CSL_DMA_PORT_EMIFF = 0, /**< EMIFF Port : also aliased as SDRAM Port */
CSL_DMA_PORT_EMIFS = 1, /**< EMIFS Port */
CSL_DMA_PORT_L3_OCP_T1 = 2, /**< L3 OCP T1 Port : also aliased as IMIF Port */
CSL_DMA_PORT_IMIF = 2, /**< IMIF Port : also aliased as L3 OCP T1 Port */
CSL_DMA_PORT_RHEA = 3, /**< RHEA Port : also aliased as TIPB Port */
CSL_DMA_PORT_TIPB = 3, /**< TIPB Port : also aliased as RHEA Port */
CSL_DMA_PORT_L3_OCP_T2 = 4, /**< L3 OCP T2 Port : also aliased as Local Access Bus Port */
CSL_DMA_PORT_LOCAL_ACCESS_BUS = 4, /**< Local Access Bus Port : also aliased as L3 OCP T2 Port */
CSL_DMA_PORT_RHEA_API = 5, /**< Rhea API port : also aliased as MPUI Port */
CSL_DMA_PORT_MPUI = 5 /**< MPUI Port : also aliased as Rhea API Port */
} CSL_DmaPort;
/** @brief Enumerations for Packing enable/disable
*
*/
typedef enum {
CSL_DMA_PACKED_ACCESS_DISABLE = 0, /**< Disable packed accesses */
CSL_DMA_PACKED_ACCESS_ENABLE = 1 /**< Enable packed accesses */
} CSL_DmaPack;
/** @brief Enumerations for Burst enable/disable
*
*/
typedef enum {
CSL_DMA_SINGLE_ACCESS = 0, /**< Bursting Disabled : Single access */
CSL_DMA_BURST4_ACCESS = 2 /**< Burst of 4*port_width */
} CSL_DmaBurst;
/** @brief Port Control Setup Structure
*
*/
typedef struct CSL_DmaSetupPortCtrl {
CSL_DmaBurst burst; /**< Port burst capability */
CSL_DmaPack pack; /**< Port packing capability */
CSL_DmaPort port; /**< Port Name */
} CSL_DmaSetupPortCtrl;
/** @brief Port Setup Structure
*
*/
typedef struct CSL_DmaSetupPort {
CSL_DmaSetupPortCtrl *portCtrlSetup; /**< Pointer to @a #CSL_DmaSetupPortCtrl structure */
CSL_DmaAmode amode; /**< Port Addressing Mode */
Uint32 startAddr; /**< Address from/to where transfer starts or ends */
Int16 frameIndex; /**< Frame Index */
Int16 elementIndex; /**< Element Index */
} CSL_DmaSetupPort;
/** @brief Setup Source Port
*
*/
typedef struct CSL_DmaSetupPort CSL_DmaSetupSrcPort;
/** @brief Setup Destination Port
*
*/
typedef struct CSL_DmaSetupPort CSL_DmaSetupDstPort;
/** @brief Dma Setup Structure
*
* An object of this type is allocated by the user and
* its address is passed as a parameter to CSL_dmaHwSetup().
*/
typedef struct CSL_DmaHwSetup {
CSL_DmaSetupChannel *channelSetup; /**< Pointer to @a #CSL_DmaSetupChannel structure */
CSL_DmaSetupSrcPort *srcPortSetup; /**< Pointer to @a #CSL_DmaSetupSrcPort structure */
CSL_DmaSetupDstPort *dstPortSetup; /**< Pointer to @a #CSL_DmaSetupDstPort structure */
CSL_DmaSetupGlobal *globalSetup; /**< Pointer to @a #CSL_DmaSetupGlobal structure */
} CSL_DmaHwSetup;
/** @brief This object contains the reference to the instance of DMA opened
* using the @a CSL_dmaOpen().
*
* The pointer to this, is passed to all DMA CSL APIs.
*/
typedef struct CSL_DmaObj {
/** This is a pointer to the global registers of the instance of DMA
* referred to by this object */
CSL_DmaGlobalRegsOvly gRegs;
/** This is the instance of DMA being referred to by this object */
CSL_InstNum perNum;
/** This is a pointer to the channel registers of the instance of DMA channel
* referred to by this object */
CSL_DmaChaRegsOvly regs;
/** This is the instance of DMA channel being referred to by this object */
Int chaNum;
/** Pointer to the Lcd Channel Register Overlay structure */
CSL_DmaLcdChaRegsOvly lcdRegs;
} CSL_DmaObj;
typedef struct CSL_DmaObj *CSL_DmaHandle;
/** @brief This will have the base-address information for the peripheral
* instance
*/
typedef struct {
/** This is a pointer to the global registers of the instance of DMA
* referred to by this object */
CSL_DmaGlobalRegsOvly gRegs;
/** This is a pointer to the channel registers of the instance of DMA channel
* referred to by this object */
CSL_DmaChaRegsOvly regs;
/** Pointer to the Lcd Channel Register Overlay structure */
CSL_DmaLcdChaRegsOvly lcdRegs;
} CSL_DmaBaseAddress;
/** @brief Module specific parameters. Present implementation doesn't have
* any module specific parameters.
*/
typedef struct{
/** Bit mask to be used for module specific parameters.
* The below declaration is just a place-holder for future
* implementation.
*/
CSL_BitMask16 flags;
/**The channel number for DMA is to be specified
*/
Int chaNum;
} CSL_DmaParam;
/** @brief Module specific context information. Present implementation doesn't have
* any Context information.
*/
typedef struct {
/** Context information of DMA.
* The below declaration is just a place-holder for future
* implementation.
*/
Uint16 contextInfo;
} CSL_DmaContext;
/**
* @brief The config-structure
*
* Used to configure the DMA using CSL_dmaHwSetupRaw(..)
*/
typedef struct {
struct channel {
Uint16 CSDP;
Uint16 CCR;
Uint16 CICR;
Uint16 CSSAL;
Uint16 CSSAU;
Uint16 CDSAL;
Uint16 CDSAU;
Uint16 CEN;
Uint16 CFN;
Uint16 CSFI;
Uint16 CSEI;
Uint16 CDEI;
Uint16 CDFI;
Uint16 COLORL;
Uint16 COLORU;
Uint16 CCR2;
Uint16 CLNKCTRL;
Uint16 LCHCTRL;
}channel;
struct global {
Uint16 GCR;
Uint16 GSCR;
Uint16 GRST;
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