csl_dma.h
来自「dsp在音频处理中的运用」· C头文件 代码 · 共 1,072 行 · 第 1/3 页
H
1,072 行
/*****************************************************\
* Copyright 2003, Texas Instruments Incorporated. *
* All rights reserved. *
* Restricted rights to use, duplicate or disclose *
* this code are granted through contract. *
* *
* "@(#) PSP/CSL 3.0.0.0 (2003-09-30) *
\*****************************************************/
/** @mainpage System DMA
*
* @section Introduction
*
* @subsection xxx Purpose and Scope
* The purpose of this document is to detail the CSL APIs for the
* DMA Module.
*
* @subsection aaa Terms and Abbreviations
* -# CSL: Chip Support Library
* -# API: Application Programmer Interface
* -# DMA: Direct Memory Access
*
* @subsection References
* -# CSL 3.x Technical Requirements Specifications Version 0.5, dated
* May 14th, 2003
* -# Chapter 8 of the OMAP1610 TRM. Please refer to System DMA section.
*
* @subsection Assumptions
* The abbreviations DMA, dma and Dma have been used throughout this
* document to refer to Direct Memory Access.
*/
/** @file csl_dma.h
*
* @brief Header file for functional layer CSL of DMA
*
* Description
* - The different enumerations, structure definitions
* and function declarations
*
*/
#ifndef _CSL_DMA_H_
#define _CSL_DMA_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <cslr_dma.h>
#include <csl.h>
#include <csl_dma_global.h>
/**************************************************************************\
* DMA global macro declarations
\**************************************************************************/
/** The default value for @a CSL_DmaSetupPortCtrl structure */
#define CSL_DMA_SETUPPORTCTRL_DEFAULTS { \
CSL_DMA_SINGLE_ACCESS, \
CSL_DMA_PACKED_ACCESS_DISABLE, \
CSL_DMA_PORT_EMIFF \
}
/** The default value for @a CSL_DmaSetupSrcPort structure */
#define CSL_DMA_SETUPSRCPORT_DEFAULTS { \
NULL, \
CSL_DMA_AMODE_CONSTANT, \
( ( (CSL_DMA_CSSAU_CSSAU_RESETVAL) << 16) + \
(CSL_DMA_CSSAL_CSSAL_RESETVAL) ), \
CSL_DMA_CSFI_CSFI_RESETVAL, \
CSL_DMA_CSEI_CSEI_RESETVAL \
}
/** The default value for @a CSL_DmaSetupDstPort structure */
#define CSL_DMA_SETUPDSTPORT_DEFAULTS { \
NULL, \
CSL_DMA_AMODE_CONSTANT, \
( ( (CSL_DMA_CDSAU_CDSAU_RESETVAL) << 16) + \
(CSL_DMA_CDSAL_CDSAL_RESETVAL) ), \
CSL_DMA_CDFI_CDFI_RESETVAL, \
CSL_DMA_CDEI_CDEI_RESETVAL \
}
/** The default value for @a CSL_DmaSetupChaCtrl structure */
#define CSL_DMA_SETUPCHACTRL_DEFAULTS { \
CSL_DMA_SYNC_NONE, \
CSL_DMA_FS_DISABLE, \
CSL_DMA_PRIORITY_LOW, \
CSL_DMA_AUTOINIT_DISABLE, \
CSL_DMA_ENDPROG_DISABLE, \
CSL_DMA_REPEAT_DISABLE, \
CSL_DMA_OMAP31_COMPATABILITY, \
}
/** The default value for @a CSL_DmaSetupChannel structure */
#define CSL_DMA_SETUPCHANNEL_DEFAULTS { \
CSL_DMA_DATASIZE_8BIT, \
( (CSL_DMA_TIMEOUT_EVENT | \
CSL_DMA_DROP_EVENT ) \
& (~(CSL_DMA_HALF_FRAME_EVENT | \
CSL_DMA_FRAME_EVENT | \
CSL_DMA_LAST_FRAME_EVENT | \
CSL_DMA_END_BLOCK_EVENT ) ) ), \
CSL_DMA_CEN_CEN_RESETVAL, \
CSL_DMA_CFN_CFN_RESETVAL, \
LCH2D_SHARES_PCH01, \
CSL_DMA_LCH_INTERLEAVE_ENABLE, \
NULL, \
NULL, \
NULL \
}
/** The default value for @a CSL_DmaSetupLchLink structure */
#define CSL_DMA_SETUPLCHLINK_DEFAULTS { \
CSL_DMA_LCH_LINK_DISABLE, \
CSL_DMA_LCH_STOP_LINK_DISABLE, \
CSL_DMA_CHA0 \
}
/** The default value for @a CSL_DmaSetupGraphic structure */
#define CSL_DMA_SETUPGRAPHIC_DEFAULTS { \
CSL_DMA_BLOCK_SYNC_DISABLE, \
CSL_DMA_TRANSPARENT_COPY_DISABLE, \
CSL_DMA_CONSTANT_FILL_DISABLE, \
0 \
}
/** @brief DMA channels
*
* There are 16 generic DMA channels and one dedicate LCD channel in the DMA.
* If the user wants to acquire a dedicated LCD channel he passes CSL_DMA_LCDCHA0.
* This is passed as a parameter in @a CSL_dmaOpen() to indicate the
* channel instance that the user wants to acquire.
*/
/**< Channel 0 */
#define CSL_DMA_CHA0 0
/**< Channel 1 */
#define CSL_DMA_CHA1 1
/**< Channel 2 */
#define CSL_DMA_CHA2 2
/**< Channel 3 */
#define CSL_DMA_CHA3 3
/**< Channel 4 */
#define CSL_DMA_CHA4 4
/**< Channel 5 */
#define CSL_DMA_CHA5 5
/**< Channel 6 */
#define CSL_DMA_CHA6 6
/**< Channel 7 */
#define CSL_DMA_CHA7 7
/**< Channel 8 */
#define CSL_DMA_CHA8 8
/**< Channel 9 */
#define CSL_DMA_CHA9 9
/**< Channel 10 */
#define CSL_DMA_CHA10 10
/**< Channel 11*/
#define CSL_DMA_CHA11 11
/**< Channel 12*/
#define CSL_DMA_CHA12 12
/**< Channel 13*/
#define CSL_DMA_CHA13 13
/**< Channel 14*/
#define CSL_DMA_CHA14 14
/**< Channel 15*/
#define CSL_DMA_CHA15 15
/**< Dedicated LCD Channel */
#define CSL_DMA_LCDCHA0 16
/** @brief Enumerations for DMA operations
*
* The DMA Operations are split, currently, into 3 groups of 16 each
* The groups being Port Commands,Channel Commands and Global Commands
* There might not be 16 commands for each group. The gaps are left
* for future use for addition of new port,channel or global command
*
* These enums are passed as parameters to @a CSL_dmaHwControl() to indicate
* the action to be performed. The comments on the right of the enum
* value indicate the data type to be allocated by the user for the
* corresponding command. The address of the allocated data type
* should be passed as a parameter to @a CSL_dmaHwControl()
*/
typedef enum {
/** Port Commands */
CSL_DMA_CMD_CHANGE_SRC_PORT_CTRL_SETUP = 0, /**< @a CSL_DmaSetupPortCtrl */
CSL_DMA_CMD_CHANGE_DST_PORT_CTRL_SETUP = 1, /**< @a CSL_DmaSetupPortCtrl */
CSL_DMA_CMD_CHANGE_SRC_AMODE = 2, /**< @a #CSL_DmaAmode */
CSL_DMA_CMD_CHANGE_DST_AMODE = 3, /**< @a #CSL_DmaAmode */
CSL_DMA_CMD_CHANGE_SRC_START_ADDR = 4, /**< @a Uint32 */
CSL_DMA_CMD_CHANGE_DST_START_ADDR = 5, /**< @a Uint32 */
CSL_DMA_CMD_CHANGE_SRC_FRAME_INDEX = 6, /**< @a Int16 */
CSL_DMA_CMD_CHANGE_DST_FRAME_INDEX = 7, /**< @a Int16 */
CSL_DMA_CMD_CHANGE_SRC_ELEMENT_INDEX = 8, /**< @a Int16 */
CSL_DMA_CMD_CHANGE_DST_ELEMENT_INDEX = 9, /**< @a Int16 */
/** Channel Commands */
CSL_DMA_CMD_CHANGE_DATATYPE = 16, /**< @a CSL_DmaDataType */
CSL_DMA_CMD_CHANGE_CHANNEL_CTRL_SETUP = 17, /**< @a CSL_DmaSetupChaCtrl */
CSL_DMA_CMD_ENABLE_INT = 18, /**< @a Uint16 : bit-vector formed by bit-wise OR of @a #CSL_DmaEvents data type */
CSL_DMA_CMD_DISABLE_INT = 19, /**< @a Uint16 : bit-vector formed by bit-wise OR of @a #CSL_DmaEvents data type */
CSL_DMA_CMD_CHANGE_ELEMENT_COUNT = 20, /**< @a Uint16 */
CSL_DMA_CMD_CHANGE_FRAME_COUNT = 21, /**< @a Uint16 */
CSL_DMA_CMD_CHANGE_LCH_TYPE = 22, /**< @a #CSL_DmaLchType */
CSL_DMA_CMD_CHANGE_LCH_INTERLEAVE = 23, /**< @a #CSL_DmaLchInterleave */
CSL_DMA_CMD_CHANGE_LCH_LINK_SETUP = 24, /**< @a CSL_DmaSetupLchLink */
CSL_DMA_CMD_CHANGE_GRAPHIC_SETUP = 25, /**< @a CSL_DmaSetupGraphic */
CSL_DMA_CMD_ENABLE_CHANNEL = 26, /**< @a NULL */
CSL_DMA_CMD_DISABLE_CHANNEL = 27, /**< @a NULL */
/** @verbatim Global Commands *
* @endverbatim
*/
CSL_DMA_CMD_CHANGE_GLOBAL_CONTROL_SETUP = 32, /**< @a CSL_DmaSetupGlobalControl */
CSL_DMA_CMD_CHANGE_COMPAT_MODE = 33, /**< @a #CSL_DmaOmapCompatMode */
CSL_DMA_CMD_GLOBAL_RESET = 34 /**< @a #CSL_DmaSwReset */
} CSL_DmaControlCmd;
/** @brief Enumerations for DMA Status Query operations
*
* The DMA Operations are split, currently, into 3 groups of 16 each
* The groups being Port Queries, Channel Queries and Global Queries
* There might not be 16 queries for each group. The gaps are left
* for future use for addition of new port,channel or global Queries
*
* These enums are passed as parameters to @a CSL_dmaGetHwStatus() to indicate
* the action to be performed. The comments on the right of the enum
* value indicate the data type to be allocated by the user for the
* corresponding command. The address of the allocated data type
* should be passed as a parameter to @a CSL_dmaGetHwStatus()
*/
typedef enum {
/* Port Queries */
CSL_DMA_QUERY_SRC_PORT_CTRL_SETUP = 0, /**< @a CSL_DmaSetupPortCtrl */
CSL_DMA_QUERY_DST_PORT_CTRL_SETUP = 1, /**< @a CSL_DmaSetupPortCtrl */
CSL_DMA_QUERY_SRC_PORT_SETUP = 2, /**< @a CSL_DmaSetupPort */
CSL_DMA_QUERY_DST_PORT_SETUP = 3, /**< @a CSL_DmaSetupPort */
/* Channel Queries */
CSL_DMA_QUERY_CHANNEL_SETUP = 16, /**< @a CSL_DmaSetupChannel */
CSL_DMA_QUERY_CHA_CTRL_SETUP = 17, /**< @a CSL_DmaSetupChaCtrl */
CSL_DMA_QUERY_LCH_LINK_SETUP = 18, /**< @a CSL_DmaSetupLchLink */
CSL_DMA_QUERY_GRAPHIC_SETUP = 19, /**< @a CSL_DmaSetupGraphic */
CSL_DMA_QUERY_STATUS = 20, /**< @a CSL_DmaStatus */
CSL_DMA_QUERY_INTERRUPT_STATUS = 21, /**< @a Uint16 : it is a bit-wise OR of the @a #CSL_DmaEvents data type */
CSL_DMA_QUERY_SYNC_STATUS = 22, /**< @a CSL_DmaSyncStatus */
CSL_DMA_QUERY_CONFIG_STATUS = 23, /**< @a CSL_DmaConfigStatus */
CSL_DMA_QUERY_SRC_ADDR_CNT = 24, /**< @a Uint16 */
CSL_DMA_QUERY_DST_ADDR_CNT = 25, /**< @a Uint16 */
/* Global Queries */
CSL_DMA_QUERY_GLOBAL_SETUP = 32, /**< @a CSL_DmaSetupGlobal */
CSL_DMA_QUERY_PCH_STATUS = 33, /**< @a CSL_DmaPchStatus */
CSL_DMA_QUERY_GLOBAL_ID = 34, /**< @a CSL_DmaGlobalId */
CSL_DMA_QUERY_GLOBAL_CONTROL_SETUP = 35, /**< @a CSL_DmaSetupGlobalControl */
CSL_DMA_QUERY_CAPABILITY = 37 /**< @a CSL_DmaCapability */
} CSL_DmaHwStatusQuery;
/** @brief Enumeration for the status of whether a channel
programmation set can be modified */
typedef enum {
CSL_DMA_FREE_TO_PROG_LCH = 0, /**< Channel Programmation Set of Registers can be modified */
CSL_DMA_WAIT_TO_PROG_LCH = 1 /**< Wait to modify Channel Programmation set of Registers */
} CSL_DmaConfigStatus;
/** @brief Enumeration for the status of whether a channel
is servicing a Synchronization request or not */
typedef enum {
CSL_DMA_SYNC_REQUEST_NOT_IN_SERVICE = 0, /**< Channel is not servicing synchronized DMA Request */
CSL_DMA_SYNC_REQUEST_IN_SERVICE = 1 /**< Channel is servicing synchronized DMA Request */
} CSL_DmaSyncStatus;
/** @brief Channel Status configurations
*
*/
typedef struct CSL_DmaStatus {
Uint16 interruptStatus; /**< Bit-wise OR of the @a #CSL_DmaEvents data type */
CSL_DmaSyncStatus syncStatus; /**< Status of Channel's Sync Request servicing */
CSL_DmaConfigStatus configStatus; /**< Status of Channel's programmation set modification permissions */
Uint16 srcAddressCounter; /**< Snapshot of source Address generated by Channel's Source Address Counter */
Uint16 dstAddressCounter; /**< Snapshot of destination Address generated by Channel's Destination Address Counter */
} CSL_DmaStatus;
/** @brief Enumeration for the Block Sync Enable/Disable feature
*
*/
typedef enum {
CSL_DMA_BLOCK_SYNC_DISABLE = 0, /**< Disable block sync for a synchronized transfer */
CSL_DMA_BLOCK_SYNC_ENABLE = 1 /**< Enable block sync for a synchronized transfer */
} CSL_DmaBlockSync;
/** @brief Enumeration for the Constant Fill Enable/Disable feature
*
*/
typedef enum {
CSL_DMA_CONSTANT_FILL_DISABLE = 0, /**< Disable the Constant fill operation */
CSL_DMA_CONSTANT_FILL_ENABLE = 1 /**< Enable the Constant Fill operation */
} CSL_DmaConstantFill;
/** @brief Enumeration of the Transparent Copy Enable/Disable feature
*
*/
typedef enum {
CSL_DMA_TRANSPARENT_COPY_DISABLE = 0, /**< Disable the Transparent Copy operation */
CSL_DMA_TRANSPARENT_COPY_ENABLE = 1 /**< Enable the Transparent Copy operation */
} CSL_DmaTransparentCopy;
/** @brief Channel Graphic related features
*
*/
typedef struct CSL_DmaSetupGraphic {
CSL_DmaBlockSync blockSync; /**< Block Synchronization feature */
CSL_DmaTransparentCopy transparentCopy; /**< Transparent Copy feature */
CSL_DmaConstantFill constantFill; /**< Constant Fill Feature */
Uint32 colour; /**< BLT Foreground Colour */
} CSL_DmaSetupGraphic;
/** @brief Enumerations for disabling the logical channel in a linked queue
*
*/
typedef enum {
CSL_DMA_LCH_STOP_LINK_DISABLE = 0, /**< No logical channel in chain is disabled */
CSL_DMA_LCH_STOP_LINK_ENABLE = 1 /**< Disable the logical channel on channel linked queue */
} CSL_DmaLchStopLink;
/** @brief Enumerations for the logical channel enable linking
*
*/
typedef enum {
CSL_DMA_LCH_LINK_DISABLE = 0, /**< No logical channel is chained after current logical channel */
CSL_DMA_LCH_LINK_ENABLE = 1 /**< Enable the next logical channel after current channel transfer */
} CSL_DmaLchLink;
/** @brief Logical Channel Chaining/Linking related features
*
*/
typedef struct CSL_DmaSetupLchLink {
CSL_DmaLchLink lchLink; /**< Defines the logical channel is on channel linked queue */
CSL_DmaLchStopLink lchStopLink; /**< Disables the logical channel on channel linked queue */
Uint16 nextLch; /**< Next logical channel used to build logical channel chaining queue */
}CSL_DmaSetupLchLink;
/** @brief Enumerations for the logical channel interleave
*
*/
typedef enum {
CSL_DMA_LCH_INTERLEAVE_ENABLE = 0, /**< Enables synchronized logical channel interleave mode */
CSL_DMA_LCH_INTERLEAVE_DISABLE = 1 /**< Disables synchronized logical channel interleave mode */
} CSL_DmaLchInterleave;
/** @brief Enumerations of the logical channel assignment relationship to
* physical channels and associated features
*
*/
typedef enum {
LCH2D_SHARES_PCH01 = 0, /**< LCh-2D dynamically shares PCh-0 and -1 */
LCHG_SHARES_PCH01 = 1, /**< LCh-G dynamically shares PCh-0 and -1 */
⌨️ 快捷键说明
复制代码Ctrl + C
搜索代码Ctrl + F
全屏模式F11
增大字号Ctrl + =
减小字号Ctrl + -
显示快捷键?