cslr_pwt.h

dsp在音频处理中的运用

/** ============================================================================
 *   @file  cslr_pwt.h
 *
 *   @path  $(CSLPATH)\arm\pwt\src
 *
 *   @desc  Register layer header file for PWT CSL
 *
 */
 
/*  ============================================================================
 *   Copyright (c) Texas Instruments Inc 2002, 2003, 2004
 *
 *   Use of this software is controlled by the terms and conditions found in the
 *   license agreement under which this software has been supplied.
 *   ===========================================================================
 */

/*  @(#) PSP/CSL 3.00.01.00[5912] (2004-06-01) */

/* =============================================================================
 *  Revision History
 *  ===============
 *  09-Jul-2004 sp    Modifications done according to new CSL architecture  
 *  01-Jun-2004 Shiva File Created.
 *
 * =============================================================================
 */
 
#ifndef _CSLR_PWT_H_
#define _CSLR_PWT_H_

#ifdef __cplusplus
extern "C" {
#endif

#include <cslr.h>
/**
  * Register Overlay Structure
  */
typedef struct  {
    /** Frequency control register */
    volatile Uint8 FRC;
    /** Reserved */
    const char RSVD0[3];
    /** Volume control register */
    volatile Uint8 VRC;
    /** Reserved */
    const char RSVD1[3];
    /** General control register */
    volatile Uint8 GCR;
} CSL_PwtRegs;

typedef volatile CSL_PwtRegs  * CSL_PwtRegsOvly;

/**
  * Register Id's
  */
typedef enum  {
   /** Frequency control register offset */
   CSL_PWT_FRC = 0x0000u,
   /** Volume control register offset */
   CSL_PWT_VRC = 0x0004u,
   /** General control register offset */
   CSL_PWT_GCR = 0x0008u
} CSL_PwtRegIds;

/**
  * Field Definition Macros
  */

/** FRC */

/** Frequency selection mask */
#define CSL_PWT_FRC_FRQ_MASK             (0x0000003Cu)
/** Frequency selection shift */
#define CSL_PWT_FRC_FRQ_SHIFT            (0x00000002u)

/** Frequency selection reset value */
#define CSL_PWT_FRC_FRQ_RESETVAL         (0x00000000u)

/** Frequency selection value zero */
#define CSL_PWT_FRC_FRQ_ZERO            (0x00000000u)
/** Frequency selection value one */
#define CSL_PWT_FRC_FRQ_ONE             (0x00000001u)
/** Frequency selection value two */
#define CSL_PWT_FRC_FRQ_TWO             (0x00000002u)
/** Frequency selection value three */
#define CSL_PWT_FRC_FRQ_THREE           (0x00000003u)
/** Frequency selection value four */
#define CSL_PWT_FRC_FRQ_FOUR            (0x00000004u)
/** Frequency selection value five */
#define CSL_PWT_FRC_FRQ_FIVE            (0x00000005u)
/** Frequency selection value six */
#define CSL_PWT_FRC_FRQ_SIX             (0x00000006u)
/** Frequency selection value seven */
#define CSL_PWT_FRC_FRQ_SEVEN           (0x00000007u)
/** Frequency selection value eight */
#define CSL_PWT_FRC_FRQ_EIGHT           (0x00000008u)
/** Frequency selection value nine */
#define CSL_PWT_FRC_FRQ_NINE            (0x00000009u)
/** Frequency selection value ten */
#define CSL_PWT_FRC_FRQ_TEN             (0x0000000Au)
/** Frequency selection value eleven */
#define CSL_PWT_FRC_FRQ_ELEVEN          (0x0000000Bu)

/** Octave selection */
#define CSL_PWT_FRC_OCTV_MASK            (0x00000003u)
/** Octave selection mask */
#define CSL_PWT_FRC_OCTV_SHIFT           (0x00000000u)
/** Octave selection shift */
#define CSL_PWT_FRC_OCTV_RESETVAL        (0x00000000u)
/** First octave  */
#define CSL_PWT_FRC_OCTV_FIRST           (0x00000000u)
/** Second octave */
#define CSL_PWT_FRC_OCTV_SECOND          (0x00000001u)
/** Third octave */
#define CSL_PWT_FRC_OCTV_THIRD           (0x00000002u)
/** Fourth octave */
#define CSL_PWT_FRC_OCTV_FOURTH          (0x00000003u)

/** Frequency control register reset value */
#define CSL_PWT_FRC_RESETVAL             (0x00000000u)

/** VRC */
/** Volume control mask */
#define CSL_PWT_VRC_VOL_MASK             (0x0000007Eu)
/** Volume control shift */
#define CSL_PWT_VRC_VOL_SHIFT            (0x00000001u)
/** Volume control reset value */
#define CSL_PWT_VRC_VOL_RESETVAL         (0x00000000u)

/** Tone switch ON/OFF mask */
#define CSL_PWT_VRC_ONOFF_MASK           (0x00000001u)
/** Tone switch ON/OFF shift */
#define CSL_PWT_VRC_ONOFF_SHIFT          (0x00000000u)
/** Tone switch ON/OFF reset value */
#define CSL_PWT_VRC_ONOFF_RESETVAL       (0x00000000u)
/** Tone switch ON/OFF OFF */
#define CSL_PWT_VRC_ONOFF_OFF            (0x00000000u)
/** Tone switch ON/OFF ON */
#define CSL_PWT_VRC_ONOFF_ON             (0x00000001u)

/** Volume control register reset value */
#define CSL_PWT_VRC_RESETVAL             (0x00000000u)

/** GCR */
/** Divider 1/154 switch ON/OFF mask */
#define CSL_PWT_GCR_TESTIN_MASK          (0x00000002u)
/** Divider 1/154 switch ON/OFF shift */
#define CSL_PWT_GCR_TESTIN_SHIFT         (0x00000001u)
/** Divider 1/154 switch ON/OFF reset value */
#define CSL_PWT_GCR_TESTIN_RESETVAL      (0x00000000u)
/** Divider 1/154 switch ON/OFF ON */
#define CSL_PWT_GCR_TESTIN_ON            (0x00000000u)
/** Divider 1/154 switch ON/OFF OFF */
#define CSL_PWT_GCR_TESTIN_OFF           (0x00000001u)

/** PWT clock enable mask */
#define CSL_PWT_GCR_CLK_EN_MASK          (0x00000001u)
/** PWT clock enable shift */
#define CSL_PWT_GCR_CLK_EN_SHIFT         (0x00000000u)
/** PWT clock enable reset value */
#define CSL_PWT_GCR_CLK_EN_RESETVAL      (0x00000000u)
/** PWT clock disable */
#define CSL_PWT_GCR_CLK_EN_DIS           (0x00000000u)
/** PWT clock enable */
#define CSL_PWT_GCR_CLK_EN_EN            (0x00000001u)

/** General control register reset value */
#define CSL_PWT_GCR_RESETVAL             (0x00000000u)

#ifdef __cplusplus
}
#endif

#endif  /* CSLR_PWT_H_ */