cslr_intc1.h

来自「dsp在音频处理中的运用」· C头文件代码 · 共 510 行 · 第 1/2 页
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/*****************************************************\ *  Copyright 2003, Texas Instruments Incorporated.  * *  All rights reserved.                             * *  Restricted rights to use, duplicate or disclose  * *  this   code   are  granted   through  contract.  * *                                                   * * "@(#) PSP/CSL  3.0.0.0  (2003-09-30)              *\*****************************************************/#ifndef _CSLR_INTC1_001_H_#define _CSLR_INTC1_001_H_#include <cslr.h>#include <tistdtypes.h>/**************************************************************************\* Register Overlay Structure\**************************************************************************/typedef struct  {    Uint32 ITR;    Uint32 MIR;    const Uint8 PAD0[8];    Uint32 SIR;    Uint32 SFR;    Uint32 ICR;    Uint32 ILR[32];    Uint32 ISR;    Uint32 ECR;} CSL_Intc1Regs;/**************************************************************************\* Overlay structure typedef definition\**************************************************************************/typedef volatile CSL_Intc1Regs  * CSL_Intc1RegsOvly;/**************************************************************************\* Field Definition Macros\**************************************************************************/  /* CSL_INTC1_ITR */#define CSL_INTC1_ITR_IRQ0_MASK       (0x80000000u)#define CSL_INTC1_ITR_IRQ0_SHIFT      (0x0000001Fu)#define CSL_INTC1_ITR_IRQ0_RESETVAL   (0x00000000u)#define CSL_INTC1_ITR_IRQ1_MASK       (0x40000000u)#define CSL_INTC1_ITR_IRQ1_SHIFT      (0x0000001Eu)#define CSL_INTC1_ITR_IRQ1_RESETVAL   (0x00000000u)#define CSL_INTC1_ITR_IRQ2_MASK       (0x20000000u)#define CSL_INTC1_ITR_IRQ2_SHIFT      (0x0000001Du)#define CSL_INTC1_ITR_IRQ2_RESETVAL   (0x00000000u)#define CSL_INTC1_ITR_IRQ3_MASK       (0x10000000u)#define CSL_INTC1_ITR_IRQ3_SHIFT      (0x0000001Cu)#define CSL_INTC1_ITR_IRQ3_RESETVAL   (0x00000000u)#define CSL_INTC1_ITR_IRQ4_MASK       (0x08000000u)#define CSL_INTC1_ITR_IRQ4_SHIFT      (0x0000001Bu)#define CSL_INTC1_ITR_IRQ4_RESETVAL   (0x00000000u)#define CSL_INTC1_ITR_IRQ5_MASK       (0x04000000u)#define CSL_INTC1_ITR_IRQ5_SHIFT      (0x0000001Au)#define CSL_INTC1_ITR_IRQ5_RESETVAL   (0x00000000u)#define CSL_INTC1_ITR_IRQ6_MASK       (0x02000000u)#define CSL_INTC1_ITR_IRQ6_SHIFT      (0x00000019u)#define CSL_INTC1_ITR_IRQ6_RESETVAL   (0x00000000u)#define CSL_INTC1_ITR_IRQ7_MASK       (0x01000000u)#define CSL_INTC1_ITR_IRQ7_SHIFT      (0x00000018u)#define CSL_INTC1_ITR_IRQ7_RESETVAL   (0x00000000u)#define CSL_INTC1_ITR_IRQ8_MASK       (0x00800000u)#define CSL_INTC1_ITR_IRQ8_SHIFT      (0x00000017u)#define CSL_INTC1_ITR_IRQ8_RESETVAL   (0x00000000u)#define CSL_INTC1_ITR_IRQ9_MASK       (0x00400000u)#define CSL_INTC1_ITR_IRQ9_SHIFT      (0x00000016u)#define CSL_INTC1_ITR_IRQ9_RESETVAL   (0x00000000u)#define CSL_INTC1_ITR_IRQ10_MASK      (0x00200000u)#define CSL_INTC1_ITR_IRQ10_SHIFT     (0x00000015u)#define CSL_INTC1_ITR_IRQ10_RESETVAL  (0x00000000u)#define CSL_INTC1_ITR_IRQ11_MASK      (0x00100000u)#define CSL_INTC1_ITR_IRQ11_SHIFT     (0x00000014u)#define CSL_INTC1_ITR_IRQ11_RESETVAL  (0x00000000u)#define CSL_INTC1_ITR_IRQ12_MASK      (0x00080000u)#define CSL_INTC1_ITR_IRQ12_SHIFT     (0x00000013u)#define CSL_INTC1_ITR_IRQ12_RESETVAL  (0x00000000u)#define CSL_INTC1_ITR_IRQ13_MASK      (0x00040000u)#define CSL_INTC1_ITR_IRQ13_SHIFT     (0x00000012u)#define CSL_INTC1_ITR_IRQ13_RESETVAL  (0x00000000u)#define CSL_INTC1_ITR_IRQ14_MASK      (0x00020000u)#define CSL_INTC1_ITR_IRQ14_SHIFT     (0x00000011u)#define CSL_INTC1_ITR_IRQ14_RESETVAL  (0x00000000u)#define CSL_INTC1_ITR_IRQ15_MASK      (0x00010000u)#define CSL_INTC1_ITR_IRQ15_SHIFT     (0x00000010u)#define CSL_INTC1_ITR_IRQ15_RESETVAL  (0x00000000u)#define CSL_INTC1_ITR_IRQ16_MASK      (0x00008000u)#define CSL_INTC1_ITR_IRQ16_SHIFT     (0x0000000Fu)#define CSL_INTC1_ITR_IRQ16_RESETVAL  (0x00000000u)#define CSL_INTC1_ITR_IRQ17_MASK      (0x00004000u)#define CSL_INTC1_ITR_IRQ17_SHIFT     (0x0000000Eu)#define CSL_INTC1_ITR_IRQ17_RESETVAL  (0x00000000u)#define CSL_INTC1_ITR_IRQ18_MASK      (0x00002000u)#define CSL_INTC1_ITR_IRQ18_SHIFT     (0x0000000Du)#define CSL_INTC1_ITR_IRQ18_RESETVAL  (0x00000000u)#define CSL_INTC1_ITR_IRQ19_MASK      (0x00001000u)#define CSL_INTC1_ITR_IRQ19_SHIFT     (0x0000000Cu)#define CSL_INTC1_ITR_IRQ19_RESETVAL  (0x00000000u)#define CSL_INTC1_ITR_IRQ20_MASK      (0x00000800u)#define CSL_INTC1_ITR_IRQ20_SHIFT     (0x0000000Bu)#define CSL_INTC1_ITR_IRQ20_RESETVAL  (0x00000000u)#define CSL_INTC1_ITR_IRQ21_MASK      (0x00000400u)#define CSL_INTC1_ITR_IRQ21_SHIFT     (0x0000000Au)#define CSL_INTC1_ITR_IRQ21_RESETVAL  (0x00000000u)#define CSL_INTC1_ITR_IRQ22_MASK      (0x00000200u)#define CSL_INTC1_ITR_IRQ22_SHIFT     (0x00000009u)#define CSL_INTC1_ITR_IRQ22_RESETVAL  (0x00000000u)#define CSL_INTC1_ITR_IRQ23_MASK      (0x00000100u)#define CSL_INTC1_ITR_IRQ23_SHIFT     (0x00000008u)#define CSL_INTC1_ITR_IRQ23_RESETVAL  (0x00000000u)#define CSL_INTC1_ITR_IRQ24_MASK      (0x00000080u)#define CSL_INTC1_ITR_IRQ24_SHIFT     (0x00000007u)#define CSL_INTC1_ITR_IRQ24_RESETVAL  (0x00000000u)#define CSL_INTC1_ITR_IRQ25_MASK      (0x00000040u)#define CSL_INTC1_ITR_IRQ25_SHIFT     (0x00000006u)#define CSL_INTC1_ITR_IRQ25_RESETVAL  (0x00000000u)#define CSL_INTC1_ITR_IRQ26_MASK      (0x00000020u)#define CSL_INTC1_ITR_IRQ26_SHIFT     (0x00000005u)#define CSL_INTC1_ITR_IRQ26_RESETVAL  (0x00000000u)#define CSL_INTC1_ITR_IRQ27_MASK      (0x00000010u)#define CSL_INTC1_ITR_IRQ27_SHIFT     (0x00000004u)#define CSL_INTC1_ITR_IRQ27_RESETVAL  (0x00000000u)#define CSL_INTC1_ITR_IRQ28_MASK      (0x00000008u)#define CSL_INTC1_ITR_IRQ28_SHIFT     (0x00000003u)#define CSL_INTC1_ITR_IRQ28_RESETVAL  (0x00000000u)#define CSL_INTC1_ITR_IRQ29_MASK      (0x00000004u)#define CSL_INTC1_ITR_IRQ29_SHIFT     (0x00000002u)#define CSL_INTC1_ITR_IRQ29_RESETVAL  (0x00000000u)#define CSL_INTC1_ITR_IRQ30_MASK      (0x00000002u)#define CSL_INTC1_ITR_IRQ30_SHIFT     (0x00000001u)#define CSL_INTC1_ITR_IRQ30_RESETVAL  (0x00000000u)#define CSL_INTC1_ITR_IRQ31_MASK      (0x00000001u)#define CSL_INTC1_ITR_IRQ31_SHIFT     (0x00000000u)#define CSL_INTC1_ITR_IRQ31_RESETVAL  (0x00000000u)#define CSL_INTC1_ITR_RESETVAL        (0x00000000u)  /* CSL_INTC1_MIR */#define CSL_INTC1_MIR_IRQ0_MASK       (0x80000000u)#define CSL_INTC1_MIR_IRQ0_SHIFT      (0x0000001Fu)#define CSL_INTC1_MIR_IRQ0_RESETVAL   (0x00000001u)#define CSL_INTC1_MIR_IRQ1_MASK       (0x40000000u)#define CSL_INTC1_MIR_IRQ1_SHIFT      (0x0000001Eu)#define CSL_INTC1_MIR_IRQ1_RESETVAL   (0x00000001u)#define CSL_INTC1_MIR_IRQ2_MASK       (0x20000000u)#define CSL_INTC1_MIR_IRQ2_SHIFT      (0x0000001Du)#define CSL_INTC1_MIR_IRQ2_RESETVAL   (0x00000001u)#define CSL_INTC1_MIR_IRQ3_MASK       (0x10000000u)#define CSL_INTC1_MIR_IRQ3_SHIFT      (0x0000001Cu)#define CSL_INTC1_MIR_IRQ3_RESETVAL   (0x00000001u)#define CSL_INTC1_MIR_IRQ4_MASK       (0x08000000u)#define CSL_INTC1_MIR_IRQ4_SHIFT      (0x0000001Bu)#define CSL_INTC1_MIR_IRQ4_RESETVAL   (0x00000001u)#define CSL_INTC1_MIR_IRQ5_MASK       (0x04000000u)#define CSL_INTC1_MIR_IRQ5_SHIFT      (0x0000001Au)#define CSL_INTC1_MIR_IRQ5_RESETVAL   (0x00000001u)#define CSL_INTC1_MIR_IRQ6_MASK       (0x02000000u)#define CSL_INTC1_MIR_IRQ6_SHIFT      (0x00000019u)#define CSL_INTC1_MIR_IRQ6_RESETVAL   (0x00000001u)#define CSL_INTC1_MIR_IRQ7_MASK       (0x01000000u)#define CSL_INTC1_MIR_IRQ7_SHIFT      (0x00000018u)#define CSL_INTC1_MIR_IRQ7_RESETVAL   (0x00000001u)#define CSL_INTC1_MIR_IRQ8_MASK       (0x00800000u)#define CSL_INTC1_MIR_IRQ8_SHIFT      (0x00000017u)#define CSL_INTC1_MIR_IRQ8_RESETVAL   (0x00000001u)#define CSL_INTC1_MIR_IRQ9_MASK       (0x00400000u)#define CSL_INTC1_MIR_IRQ9_SHIFT      (0x00000016u)#define CSL_INTC1_MIR_IRQ9_RESETVAL   (0x00000001u)#define CSL_INTC1_MIR_IRQ10_MASK      (0x00200000u)#define CSL_INTC1_MIR_IRQ10_SHIFT     (0x00000015u)#define CSL_INTC1_MIR_IRQ10_RESETVAL  (0x00000001u)#define CSL_INTC1_MIR_IRQ11_MASK      (0x00100000u)#define CSL_INTC1_MIR_IRQ11_SHIFT     (0x00000014u)#define CSL_INTC1_MIR_IRQ11_RESETVAL  (0x00000001u)#define CSL_INTC1_MIR_IRQ12_MASK      (0x00080000u)#define CSL_INTC1_MIR_IRQ12_SHIFT     (0x00000013u)#define CSL_INTC1_MIR_IRQ12_RESETVAL  (0x00000001u)#define CSL_INTC1_MIR_IRQ13_MASK      (0x00040000u)#define CSL_INTC1_MIR_IRQ13_SHIFT     (0x00000012u)#define CSL_INTC1_MIR_IRQ13_RESETVAL  (0x00000001u)#define CSL_INTC1_MIR_IRQ14_MASK      (0x00020000u)#define CSL_INTC1_MIR_IRQ14_SHIFT     (0x00000011u)#define CSL_INTC1_MIR_IRQ14_RESETVAL  (0x00000001u)#define CSL_INTC1_MIR_IRQ15_MASK      (0x00010000u)#define CSL_INTC1_MIR_IRQ15_SHIFT     (0x00000010u)#define CSL_INTC1_MIR_IRQ15_RESETVAL  (0x00000001u)#define CSL_INTC1_MIR_IRQ16_MASK      (0x00008000u)#define CSL_INTC1_MIR_IRQ16_SHIFT     (0x0000000Fu)#define CSL_INTC1_MIR_IRQ16_RESETVAL  (0x00000001u)#define CSL_INTC1_MIR_IRQ17_MASK      (0x00004000u)#define CSL_INTC1_MIR_IRQ17_SHIFT     (0x0000000Eu)#define CSL_INTC1_MIR_IRQ17_RESETVAL  (0x00000001u)#define CSL_INTC1_MIR_IRQ18_MASK      (0x00002000u)#define CSL_INTC1_MIR_IRQ18_SHIFT     (0x0000000Du)#define CSL_INTC1_MIR_IRQ18_RESETVAL  (0x00000001u)#define CSL_INTC1_MIR_IRQ19_MASK      (0x00001000u)#define CSL_INTC1_MIR_IRQ19_SHIFT     (0x0000000Cu)#define CSL_INTC1_MIR_IRQ19_RESETVAL  (0x00000001u)#define CSL_INTC1_MIR_IRQ20_MASK      (0x00000800u)#define CSL_INTC1_MIR_IRQ20_SHIFT     (0x0000000Bu)
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