csl_emiff.h

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/** @mainpage EMIFF CSL 3.x
 *
 * @section Introduction
 *
 * @subsection xxx Purpose and Scope
 * The purpose of this document is to identify a set of common CSL APIs for the
 * EMIFF module across various devices. The CSL developer is expected to refer to
 * this document while designing APIs for these modules. Some of the listed APIs
 * may not be applicable to a given EMIFF module. While in other cases this list
 * of APIs may not be sufficient to cover all the features of a particular EMIFF
 * Module. The CSL developer should use his discretion in designing new APIs or
 * extending the existing ones to cover these.
 *
 * @subsection aaa Terms and Abbreviations
 *   -# CSL:  Chip Support Library
 *   -# API:  Application Programmer Interface
 *
 * @subsection References
 *    -# CSL-001-DES, CSL 3.x Design Specification DocumentVersion 1.03
 *    -# OMAP3.2_122, OMAP3.2 SDRAM Interface Controller Specification, Ver 1.16
 *
 */

/** @file csl_emiff.h
 *
 *  @brief    Header file for functional layer of CSL
 *
 *  Description
 *    - The different* @brief Enumerations, structure definitions
 *      and function declarations
 *
 *  Modification 2
 *    - modified on: 02/04/2004
 *    - reason: Doxygenation of the comments to enable document generation
 *
 *  Modification 1
 *    - modified on: 29/03/2004
 *    - reason: Created the initail file from OMAP5905 CSL release on 7th Oct 2003
 *
 *  @date 29th March, 2004
 *  @author Prakash V. Gudnavar.
 */

#ifndef _CSL_EMIFF_H_
#define _CSL_EMIFF_H_


#ifdef __cplusplus
extern "C" {
#endif

#include <csl.h>
#include <cslr_emiff.h>

/**************************************************************************\
* EMIFF global macro declarations
\**************************************************************************/

/**************************************************************************\
* EMIFF global typedef declarations
\**************************************************************************/
/** @brief Enumeration for SDRAM clock enable/disable */
typedef enum {
    /** Enable clock to external SDRAM */
    CSL_EMIFF_SDRAMCLOCKEN_ENABLE	 =		    0,
    /** Disable clock to external SDRAM. AUTOCLK should be enabled */
    CSL_EMIFF_SDRAMCLOCKEN_DISABLE	 =		    1
} CSL_EmiffSdramClockEn;

/** @brief Enumeration for power down enable/disable */
typedef enum {
    /** Disable power down mode */
    CSL_EMIFF_SDRAMPWRDOWNEN_DISABLE	=		   0,
    /** Put SDRAM into power down mode */
    CSL_EMIFF_SDRAMPWRDOWNEN_ENABLE	=		   1
} CSL_EmiffSdramPwrDownEn;

/** @brief Enumeration for self refresh enable/disable */
typedef enum {
    /** Disable self refresh mode */
    CSL_EMIFF_SDRAMSELFREFRESHEN_DISABLE  =		     0,
    /** Enable self refresh mode */
    CSL_EMIFF_SDRAMSELFREFRESHEN_ENABLE   =		     1
} CSL_EmiffSdramSelfRefreshEn;

/** @brief Enumeration for auto clock enable/disable */
typedef enum {
     /** Disable auto clock mode */
    CSL_EMIFF_SDRAMAUTOCLOCKEN_DISABLE	    =		       0,
    /** Enable auto clock mode(suspend internal clocks) */
    CSL_EMIFF_SDRAMAUTOCLOCKEN_ENABLE	    =		       1
} CSL_EmiffSdramAutoClockEn;

/** @brief Enumeration for self refresh enable/disable during reset */
typedef enum {
     /** No SDRAM self refresh when in reset */
    CSL_EMIFF_SDRAMSELFREFRESHRESET_NO	   =		      0,
    /** Place the SDRAM into self refresh when in reset */
    CSL_EMIFF_SDRAMSELFREFRESHRESET_YES    =		      1
} CSL_EmiffSdramSelfRefreshReset;

/** @brief Enumeration for self refresh enable/disable during reset */
typedef enum {
     /** No SDRAM self refresh when in standby mode */
    CSL_EMIFF_SDRAMSELFREFRESHSTANDBY_NO   =		      0,
    /** Place the SDRAM into self refresh when in standby mode */
    CSL_EMIFF_SDRAMSELFREFRESHSTANDBY_YES  =		      1
} CSL_EmiffSdramSelfRefreshStandBy;

/** @brief Enumeration for QFC enable/disable */
typedef enum {
    /** Disable QFC */
    CSL_EMIFF_SDRAMQFCEN_DISABLE	  =		     0,
    /** Enable QFC */
    CSL_EMIFF_SDRAMQFCEN_ENABLE 	  =		     1
} CSL_EmiffSdramQfcEn;

/** @brief Enumeration for DS driver strength bit value */
typedef enum {
    /** DS driver strength at normal */
    CSL_EMIFF_SDRAMDSDRIVERSTRENGTH_NORMAL	      = 		 0,
    /** DS driver strength at reduced mode */
    CSL_EMIFF_SDRAMDSDRIVERSTRENGTH_REDUCED	      = 		 1
} CSL_EmiffSdramDsDriverStrength;

/** @brief Enumeration for DLL enable/disable */
typedef enum {
    /** Enable DLL */
    CSL_EMIFF_SDRAMDLLEN_ENABLE     =		       0,
    /** Disable DLL */
    CSL_EMIFF_SDRAMDLLEN_DISABLE    =		       1
} CSL_EmiffSdramDllEn;

/** @brief Enumeration for different SDRAM frequency ranges */
typedef enum {
    /** Frequency range SDF0 (default) */
    CSL_EMIFF_SDRAMFREQ_SDF0	  =		     0,
    /** Frequency range SDF1 */
    CSL_EMIFF_SDRAMFREQ_SDF1	  =		     1,
    /** Frequency range SDF2 */
    CSL_EMIFF_SDRAMFREQ_SDF2	  =		     2,
    /** Frequency range SDF3 */
    CSL_EMIFF_SDRAMFREQ_SDF3	  =		     3
} CSL_EmiffSdramFreq;

/** @brief Enumeration for SDRAM Auto refresh modes */
typedef enum {
    /** No auto refresh */
    CSL_EMIFF_SDRAMAUTOREFRESH_DISABLE =		  0,
    /** One command every 14.7 micro seconds */
    CSL_EMIFF_SDRAMAUTOREFRESH_ENABLE = 		 1,
    /** Auto refresh by burst of 4 commands */
    CSL_EMIFF_SDRAMAUTOREFRESH_BURST4 = 		 2,
    /** Auto refresh bu burst of 8 commands  */
    CSL_EMIFF_SDRAMAUTOREFRESH_BURST8 = 		 3
} CSL_EmiffSdramAutoRefresh;

/** @brief Enumeration for SDRAM Memory Sizes(in MBits) */
typedef enum {
    /** 16 MBit memory */
    CSL_EMIFF_SDRAMMEMSIZE_16	 =		    0,
    /** 64 MBit memory */
    CSL_EMIFF_SDRAMMEMSIZE_64	 =		    1,
    /** 128 MBit memory */
    CSL_EMIFF_SDRAMMEMSIZE_128	 =		    2,
    /** 258 MBit memory */
    CSL_EMIFF_SDRAMMEMSIZE_256	 =		    3,
    /** 512 MBit memory */
    CSL_EMIFF_SDRAMMEMSIZE_512	 =		    4,
    /** 1024 MBit memory */
    CSL_EMIFF_SDRAMMEMSIZE_1024  =		    8
} CSL_EmiffSdramMemSize;

/** @brief Enumeration for various SDRAM Manual commands */
typedef enum {
    /** NOP Command */
    CSL_EMIFF_SDRAMCMD_NOP		=		   0,
    /** Precharge Command */
    CSL_EMIFF_SDRAMCMD_PRECHARGE	=		   1,
    /** Auto Refresh Command */
    CSL_EMIFF_SDRAMCMD_AUTOREFRESH	=		   2,
    /** Enter Deep Sleep Command */
    CSL_EMIFF_SDRAMCMD_DEEPSLEEP_ENTER		=		   3,
    /** Exit Deep Sleep Command */
    CSL_EMIFF_SDRAMCMD_DEEPSLEEP_EXIT		=		   4,
    /** Set CKE signal high */
    CSL_EMIFF_SDRAMCMD_CKE_HIGH 	=		   7,
    /** Set CKE signal low */
    CSL_EMIFF_SDRAMCMD_CKE_LOW		=		   8
} CSL_EmiffSdramCmd;

/** @brief Enumeration for various SDRAM data-bus sizes(in bits) */
typedef enum {
    /** Data bus size = 8 */
    CSL_EMIFF_SDRAMDATABUSSIZE_8 =		    0,
    /** Data bus size = 16 */
    CSL_EMIFF_SDRAMDATABUSSIZE_16 =		     1
} CSL_EmiffSdramDataBusSize;

/** @brief Enumeration for number of banks */
typedef enum {
    /** Number of banks = 2 */
    CSL_EMIFF_SDRAMBANKCNT_2	=		   0,
    /** Number of banks = 4 */
    CSL_EMIFF_SDRAMBANKCNT_4	=		   1
} CSL_EmiffSdramBankCnt;

/** @brief Enumeration for supported CAS latencies */
typedef enum {
    /** CAS latency = 2 */
    CSL_EMIFF_SDRAMCASLATENCY_2  =		    2,
    /** CAS latency = 3 (default) */
    CSL_EMIFF_SDRAMCASLATENCY_3  =		    3
} CSL_EmiffSdramCasLatency;

/** @brief Enumeration for maximum temperatures for Temperature Compensated Self-Refresh */
typedef enum {
    /** 70 C max temperature for 128 MBit device */
    CSL_EMIFF_SDRAMTCSR_0	  =		     0,
    /** 45 C max temperature for 128 MBit device */
    CSL_EMIFF_SDRAMTCSR_1	  =		     1,
    /** 15 C max temperature for 128 MBit device */
    CSL_EMIFF_SDRAMTCSR_2	  =		     2,
    /** 85 C max temperature for 128 MBit device */
    CSL_EMIFF_SDRAMTCSR_3	  =		     3
} CSL_EmiffSdramTcsr;

/** @brief Enumeration for Partial Array Self-Refresh modes */
typedef enum {
    /** All banks  */
    CSL_EMIFF_SDRAMPASR_ALLBANKS  =		     0,
    /** 1/2 array */
    CSL_EMIFF_SDRAMPASR_1BY2ARRAY =		     1,
     /** 1/4 array */
    CSL_EMIFF_SDRAMPASR_1BY4ARRAY =		     2,
    /** 1/8 array */
    CSL_EMIFF_SDRAMPASR_1BY8ARRAY =		     5,
    /** 1/16 array */
    CSL_EMIFF_SDRAMPASR_1BY16ARRAY =		 6
} CSL_EmiffSdramPasr;

/** @brief Enumeration for types of SDRAM devices supported. */
typedef enum {
    /** Standard Single Data Rate SDRAM */
    CSL_EMIFF_SDRAMDEVTYPE_STANDARD_SDR =		   0,
    /** Standard Double Data Rate SDRAM */
    CSL_EMIFF_SDRAMDEVTYPE_STANDARD_DDR =		   1,
    /** Mobile Single Data Rate SDRAM */
    CSL_EMIFF_SDRAMDEVTYPE_MOBILE_SDR	=		   2,
    /** Mobile Double Data Rate SDRAM */
    CSL_EMIFF_SDRAMDEVTYPE_MOBILE_DDR	=		   3
} CSL_EmiffSdramDevType;

/** @brief Enumeration for SDRAM operation modes */
typedef enum {
    /** Low Power Mode */
    CSL_EMIFF_SDRAMOPMODE_LPLB	  =		     0,
    /** High Power/High Bandwidth Mode */
    CSL_EMIFF_SDRAMOPMODE_HPHB	  =		     1,
    /** Programmable Operating Mode */
    CSL_EMIFF_SDRAMOPMODE_POM0	  =		     2
} CSL_EmiffSdramOpMode;

/** @brief Enumeration for Nominal digitally controlled delay */
typedef enum {
    /** Nominal Digitally Controlled Delay:20% of the clock period */
    CSL_EMIFF_DLLPHASE_72	   =		      0,
    /** Nominal Digitally Controlled Delay:25% of the clock period */
    CSL_EMIFF_DLLPHASE_90	   =		      1
} CSL_EmiffDllPhase;

/** @brief Enumeration for DLL enable/Disable */
typedef enum {
    /** Low Power Mode */
    CSL_EMIFF_DLLEN_DISABLE	     =			0,
    /** High Power/High Bandwidth Mode     */
    CSL_EMIFF_DLLEN_ENABLE	     =			1
} CSL_EmiffDllEn;

/** @brief Enumerations for EMIFF operations
 *
 * This enumeration is used to select the control command that has to be
 * passed to the CSL_emiffHwControl function.
 */
typedef enum {
    /** Executre a manual SDRAM command */
    CSL_EMIFF_CMD_SDRAMCMD,
    /** Put EMIFF into power down mode */
    CSL_EMIFF_CMD_DEEPPOWERDOWNENABLE
} CSL_EmiffHwControlCmd;

/** @brief Enumerations for h/w status query
 *
 * This enumeration is used to select the hardware status query that has to be
 * passed to the CSL_emiffGetHwStatus function.
 */
typedef enum {
    /** Get abort status of a transaction */
    CSL_EMIFF_QUERY_ABORTSTATUS,
    /** Get DLL status */
    CSL_EMIFF_QUERY_DLLSTATUS
} CSL_EmiffHwStatusQuery;


/** @brief Default values for CSL_EmiffSdramConfig setup structure */
#define CSL_EMIFF_DEFAULTS_SDRAMCONFIG	{ \
	    (CSL_EmiffSdramSelfRefreshEn)CSL_EMIFF_CR_SLRF_RESETVAL, \
	    (CSL_EmiffSdramAutoRefresh)CSL_EMIFF_CR_ARE_RESETVAL, \
	    (CSL_EmiffSdramMemSize)CSL_EMIFF_SDRAMMEMSIZE_16, \
	    (CSL_EmiffSdramDataBusSize)CSL_EMIFF_SDRAMDATABUSSIZE_8, \
	    (CSL_EmiffSdramBankCnt)CSL_EMIFF_SDRAMBANKCNT_2, \
	    (Uint16)CSL_EMIFF_CR_ARCV_RESETVAL, \
	    (CSL_EmiffSdramFreq)CSL_EMIFF_CR_SDRFRQ_RESETVAL, \
	    (CSL_EmiffSdramPwrDownEn)CSL_EMIFF_CR_PWD_RESETVAL, \
	    (CSL_EmiffSdramClockEn)CSL_EMIFF_CR_CLK_RESETVAL, \
	    (CSL_EmiffSdramAutoClockEn)CSL_EMIFF_CR2_AUTOCLK_RESETVAL, \
	    (CSL_EmiffSdramSelfRefreshReset)CSL_EMIFF_CR2_RFRST_RESETVAL, \
	    (CSL_EmiffSdramSelfRefreshStandBy)CSL_EMIFF_CR2_RFSTDBY_RESETVAL, \
	    (CSL_EmiffSdramCasLatency)CSL_EMIFF_MRS_CASL_RESETVAL, \
	    (Uint8)CSL_EMIFF_MRS_PGBL_RESETVAL, \
	    (CSL_EmiffSdramQfcEn)CSL_EMIFF_EMRS0_QFC_RESETVAL, \
	    (CSL_EmiffSdramDsDriverStrength)CSL_EMIFF_EMRS0_DS_RESETVAL, \
	    (CSL_EmiffSdramDllEn)CSL_EMIFF_EMRS0_DLL_RESETVAL, \
	    (CSL_EmiffSdramTcsr)CSL_EMIFF_EMRS1_TCSR_RESETVAL, \
	    (CSL_EmiffSdramPasr)CSL_EMIFF_EMRS1_PASR_RESETVAL \
	}

/** @brief Default values for CSL_EmiffSdramOperation setup structure */
#define CSL_EMIFF_DEFAULTS_SDRAMOPERATION   { \
	(Uint8)CSL_EMIFF_OPR_TOB1_RESETVAL,\
	(Uint8)CSL_EMIFF_OPR_TOB2_RESETVAL,\
	(Uint8)CSL_EMIFF_OPR_TOB3_RESETVAL,\
	(Uint8)CSL_EMIFF_OPR_TOB4_RESETVAL,\
	(CSL_EmiffSdramOpMode)CSL_EMIFF_OPR_OPMODE_RESETVAL\
       }

/** @brief Default values for CSL_EmiffConsecAccess setup structure */
#define CSL_EMIFF_DEFAULTS_CONSECACCESS { \
	(Uint8)CSL_EMIFF_PR_OCPI_RESETVAL,\
	(Uint8)CSL_EMIFF_PR_DMA_RESETVAL,\
	(Uint8)CSL_EMIFF_PR_DSP_RESETVAL,\
	(Uint8)CSL_EMIFF_PR_ARM_RESETVAL\
       }

/** @brief Default values for CSL_EmiffDynPriTimeout setup structure */
#define CSL_EMIFF_DEFAULTS_DYNPRITIMEOUT  { \
	(Uint8)CSL_EMIFF_DAPTR3_OCPI_RESETVAL,\
	(Uint8)CSL_EMIFF_DAPTR2_LCD_RESETVAL,\