cslr_ssw.h

来自「dsp在音频处理中的运用」· C头文件 代码 · 共 233 行

H
233 行
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#ifndef _CSLR_SSW_001_H_
#define _CSLR_SSW_001_H_

#include <cslr.h>

#include <tistdtypes.h>

/**************************************************************************\
* Register Overlay Structure
\**************************************************************************/
typedef struct  {
    volatile Uint32 UART1_CFGREG;
    const char RSVD0[28];
    volatile Uint32 UART2_CFGREG;
    const char RSVD1[28];
    volatile Uint32 UART3_CFGREG;
    const char RSVD2[76];
    volatile Uint32 MCBSP2_CFGREG;
    const char RSVD3[12];
    volatile Uint32 I2C_CFGREG;
    const char RSVD4[12];
    volatile Uint32 SPI_CFGREG;
    const char RSVD5[12];
    volatile Uint32 GPTIMER1_CFGREG;
    const char RSVD6[12];
    volatile Uint32 GPTIMER2_CFGREG;
    const char RSVD7[12];
    volatile Uint32 GPTIMER3_CFGREG;
    const char RSVD8[12];
    volatile Uint32 GPTIMER4_CFGREG;
    const char RSVD9[12];
    volatile Uint32 GPTIMER5_CFGREG;
    const char RSVD10[12];
    volatile Uint32 GPTIMER6_CFGREG;
    const char RSVD11[28];
    volatile Uint32 GPTIMER7_CFGREG;
    const char RSVD12[12];
    volatile Uint32 GPTIMER8_CFGREG;
    const char RSVD13[28];
    volatile Uint32 MMCSD2_CFGREG;
} CSL_SswRegs;

/**************************************************************************\* Overlay structure typedef definition\**************************************************************************/typedef volatile CSL_SswRegs  * CSL_SswRegsOvly;/**************************************************************************\
* Field Definition Macros
\**************************************************************************/

/* UART1_CFGREG */

#define CSL_SSW_UART1_CFGREG_DSPSW_MASK  (0x00000002u)
#define CSL_SSW_UART1_CFGREG_DSPSW_SHIFT (0x00000001u)
#define CSL_SSW_UART1_CFGREG_DSPSW_RESETVAL (0x00000000u)

#define CSL_SSW_UART1_CFGREG_MCUSW_MASK  (0x00000001u)
#define CSL_SSW_UART1_CFGREG_MCUSW_SHIFT (0x00000000u)
#define CSL_SSW_UART1_CFGREG_MCUSW_RESETVAL (0x00000001u)

#define CSL_SSW_UART1_CFGREG_RESETVAL    (0x00000001u)

/* UART2_CFGREG */

#define CSL_SSW_UART2_CFGREG_DSPSW_MASK  (0x00000002u)
#define CSL_SSW_UART2_CFGREG_DSPSW_SHIFT (0x00000001u)
#define CSL_SSW_UART2_CFGREG_DSPSW_RESETVAL (0x00000000u)

#define CSL_SSW_UART2_CFGREG_MCUSW_MASK  (0x00000001u)
#define CSL_SSW_UART2_CFGREG_MCUSW_SHIFT (0x00000000u)
#define CSL_SSW_UART2_CFGREG_MCUSW_RESETVAL (0x00000001u)

#define CSL_SSW_UART2_CFGREG_RESETVAL    (0x00000001u)

/* UART3_CFGREG */

#define CSL_SSW_UART3_CFGREG_DSPSW_MASK  (0x00000002u)
#define CSL_SSW_UART3_CFGREG_DSPSW_SHIFT (0x00000001u)
#define CSL_SSW_UART3_CFGREG_DSPSW_RESETVAL (0x00000000u)

#define CSL_SSW_UART3_CFGREG_MCUSW_MASK  (0x00000001u)
#define CSL_SSW_UART3_CFGREG_MCUSW_SHIFT (0x00000000u)
#define CSL_SSW_UART3_CFGREG_MCUSW_RESETVAL (0x00000001u)

#define CSL_SSW_UART3_CFGREG_RESETVAL    (0x00000001u)

/* MCBSP2_CFGREG */

#define CSL_SSW_MCBSP2_CFGREG_DSPSW_MASK (0x00000002u)
#define CSL_SSW_MCBSP2_CFGREG_DSPSW_SHIFT (0x00000001u)
#define CSL_SSW_MCBSP2_CFGREG_DSPSW_RESETVAL (0x00000000u)

#define CSL_SSW_MCBSP2_CFGREG_MCUSW_MASK (0x00000001u)
#define CSL_SSW_MCBSP2_CFGREG_MCUSW_SHIFT (0x00000000u)
#define CSL_SSW_MCBSP2_CFGREG_MCUSW_RESETVAL (0x00000001u)

#define CSL_SSW_MCBSP2_CFGREG_RESETVAL   (0x00000001u)

/* I2C_CFGREG */

#define CSL_SSW_I2C_CFGREG_DSPSW_MASK    (0x00000002u)
#define CSL_SSW_I2C_CFGREG_DSPSW_SHIFT   (0x00000001u)
#define CSL_SSW_I2C_CFGREG_DSPSW_RESETVAL (0x00000000u)

#define CSL_SSW_I2C_CFGREG_MCUSW_MASK    (0x00000001u)
#define CSL_SSW_I2C_CFGREG_MCUSW_SHIFT   (0x00000000u)
#define CSL_SSW_I2C_CFGREG_MCUSW_RESETVAL (0x00000001u)

#define CSL_SSW_I2C_CFGREG_RESETVAL      (0x00000001u)

/* SPI_CFGREG */

#define CSL_SSW_SPI_CFGREG_DSPSW_MASK    (0x00000002u)
#define CSL_SSW_SPI_CFGREG_DSPSW_SHIFT   (0x00000001u)
#define CSL_SSW_SPI_CFGREG_DSPSW_RESETVAL (0x00000000u)

#define CSL_SSW_SPI_CFGREG_MCUSW_MASK    (0x00000001u)
#define CSL_SSW_SPI_CFGREG_MCUSW_SHIFT   (0x00000000u)
#define CSL_SSW_SPI_CFGREG_MCUSW_RESETVAL (0x00000001u)

#define CSL_SSW_SPI_CFGREG_RESETVAL      (0x00000001u)

/* GPTIMER1_CFGREG */

#define CSL_SSW_GPTIMER1_CFGREG_DSPSW_MASK (0x00000002u)
#define CSL_SSW_GPTIMER1_CFGREG_DSPSW_SHIFT (0x00000001u)
#define CSL_SSW_GPTIMER1_CFGREG_DSPSW_RESETVAL (0x00000000u)

#define CSL_SSW_GPTIMER1_CFGREG_MCUSW_MASK (0x00000001u)
#define CSL_SSW_GPTIMER1_CFGREG_MCUSW_SHIFT (0x00000000u)
#define CSL_SSW_GPTIMER1_CFGREG_MCUSW_RESETVAL (0x00000001u)

#define CSL_SSW_GPTIMER1_CFGREG_RESETVAL (0x00000001u)

/* GPTIMER2_CFGREG */

#define CSL_SSW_GPTIMER2_CFGREG_DSPSW_MASK (0x00000002u)
#define CSL_SSW_GPTIMER2_CFGREG_DSPSW_SHIFT (0x00000001u)
#define CSL_SSW_GPTIMER2_CFGREG_DSPSW_RESETVAL (0x00000000u)

#define CSL_SSW_GPTIMER2_CFGREG_MCUSW_MASK (0x00000001u)
#define CSL_SSW_GPTIMER2_CFGREG_MCUSW_SHIFT (0x00000000u)
#define CSL_SSW_GPTIMER2_CFGREG_MCUSW_RESETVAL (0x00000001u)

#define CSL_SSW_GPTIMER2_CFGREG_RESETVAL (0x00000001u)

/* GPTIMER3_CFGREG */

#define CSL_SSW_GPTIMER3_CFGREG_DSPSW_MASK (0x00000002u)
#define CSL_SSW_GPTIMER3_CFGREG_DSPSW_SHIFT (0x00000001u)
#define CSL_SSW_GPTIMER3_CFGREG_DSPSW_RESETVAL (0x00000000u)

#define CSL_SSW_GPTIMER3_CFGREG_MCUSW_MASK (0x00000001u)
#define CSL_SSW_GPTIMER3_CFGREG_MCUSW_SHIFT (0x00000000u)
#define CSL_SSW_GPTIMER3_CFGREG_MCUSW_RESETVAL (0x00000001u)

#define CSL_SSW_GPTIMER3_CFGREG_RESETVAL (0x00000001u)

/* GPTIMER4_CFGREG */

#define CSL_SSW_GPTIMER4_CFGREG_DSPSW_MASK (0x00000002u)
#define CSL_SSW_GPTIMER4_CFGREG_DSPSW_SHIFT (0x00000001u)
#define CSL_SSW_GPTIMER4_CFGREG_DSPSW_RESETVAL (0x00000000u)

#define CSL_SSW_GPTIMER4_CFGREG_MCUSW_MASK (0x00000001u)
#define CSL_SSW_GPTIMER4_CFGREG_MCUSW_SHIFT (0x00000000u)
#define CSL_SSW_GPTIMER4_CFGREG_MCUSW_RESETVAL (0x00000001u)

#define CSL_SSW_GPTIMER4_CFGREG_RESETVAL (0x00000001u)

/* GPTIMER5_CFGREG */

#define CSL_SSW_GPTIMER5_CFGREG_DSPSW_MASK (0x00000002u)
#define CSL_SSW_GPTIMER5_CFGREG_DSPSW_SHIFT (0x00000001u)
#define CSL_SSW_GPTIMER5_CFGREG_DSPSW_RESETVAL (0x00000000u)

#define CSL_SSW_GPTIMER5_CFGREG_MCUSW_MASK (0x00000001u)
#define CSL_SSW_GPTIMER5_CFGREG_MCUSW_SHIFT (0x00000000u)
#define CSL_SSW_GPTIMER5_CFGREG_MCUSW_RESETVAL (0x00000001u)

#define CSL_SSW_GPTIMER5_CFGREG_RESETVAL (0x00000001u)

/* GPTIMER6_CFGREG */

#define CSL_SSW_GPTIMER6_CFGREG_DSPSW_MASK (0x00000002u)
#define CSL_SSW_GPTIMER6_CFGREG_DSPSW_SHIFT (0x00000001u)
#define CSL_SSW_GPTIMER6_CFGREG_DSPSW_RESETVAL (0x00000000u)

#define CSL_SSW_GPTIMER6_CFGREG_MCUSW_MASK (0x00000001u)
#define CSL_SSW_GPTIMER6_CFGREG_MCUSW_SHIFT (0x00000000u)
#define CSL_SSW_GPTIMER6_CFGREG_MCUSW_RESETVAL (0x00000001u)

#define CSL_SSW_GPTIMER6_CFGREG_RESETVAL (0x00000001u)

/* GPTIMER7_CFGREG */

#define CSL_SSW_GPTIMER7_CFGREG_DSPSW_MASK (0x00000002u)
#define CSL_SSW_GPTIMER7_CFGREG_DSPSW_SHIFT (0x00000001u)
#define CSL_SSW_GPTIMER7_CFGREG_DSPSW_RESETVAL (0x00000000u)

#define CSL_SSW_GPTIMER7_CFGREG_MCUSW_MASK (0x00000001u)
#define CSL_SSW_GPTIMER7_CFGREG_MCUSW_SHIFT (0x00000000u)
#define CSL_SSW_GPTIMER7_CFGREG_MCUSW_RESETVAL (0x00000001u)

#define CSL_SSW_GPTIMER7_CFGREG_RESETVAL (0x00000001u)

/* GPTIMER8_CFGREG */

#define CSL_SSW_GPTIMER8_CFGREG_DSPSW_MASK (0x00000002u)
#define CSL_SSW_GPTIMER8_CFGREG_DSPSW_SHIFT (0x00000001u)
#define CSL_SSW_GPTIMER8_CFGREG_DSPSW_RESETVAL (0x00000000u)

#define CSL_SSW_GPTIMER8_CFGREG_MCUSW_MASK (0x00000001u)
#define CSL_SSW_GPTIMER8_CFGREG_MCUSW_SHIFT (0x00000000u)
#define CSL_SSW_GPTIMER8_CFGREG_MCUSW_RESETVAL (0x00000001u)

#define CSL_SSW_GPTIMER8_CFGREG_RESETVAL (0x00000001u)

/* MMCSD2_CFGREG */

#define CSL_SSW_MMCSD2_CFGREG_DSPSW_MASK (0x00000002u)
#define CSL_SSW_MMCSD2_CFGREG_DSPSW_SHIFT (0x00000001u)
#define CSL_SSW_MMCSD2_CFGREG_DSPSW_RESETVAL (0x00000000u)

#define CSL_SSW_MMCSD2_CFGREG_MCUSW_MASK (0x00000001u)
#define CSL_SSW_MMCSD2_CFGREG_MCUSW_SHIFT (0x00000000u)
#define CSL_SSW_MMCSD2_CFGREG_MCUSW_RESETVAL (0x00000001u)

#define CSL_SSW_MMCSD2_CFGREG_RESETVAL   (0x00000001u)

#endif

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