csl_ulpd.h

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/** @mainpage ULPD CSL 3.x
 *
 * @section Introduction
 *
 * @subsection xxx Purpose and Scope
 * The purpose of this document is to identify a set of common CSL APIs for
 * the ULPD module across various devices. The CSL developer is expected to
 * refer to this document while designing APIs for these modules. Some of the
 * listed APIs may not be applicable to a given ULPD module. While in other
 * cases this list of APIs may not be sufficient to cover all the features of
 * a particular ULPD Module. The CSL developer should use his discretion in
 * designing new APIs or extending the existing ones to cover these.
 *
 * @subsection aaa Terms and Abbreviations
 *   -# CSL :  Chip Support Library
 *   -# API :  Application Programmer Interface
 *   -# ULPD:  Ultra Low Power Device
 *
 * @subsection References
 *    -# CSL-001-DES, CSL 3.x Design Specification DocumentVersion 1.02
 *    -# SWPU062A (1610 Technical Reference Manual) Specification Document.
 *
 */


/** @file csl_ulpd.h
 *
 *    @brief    Header file for functional layer of CSL
 *
 *  Description
 *    - The different enumerations, structure definitions
 *      and function declarations
 *
 *  Modification 1
 *    - modified on: 30/01/2004
 *    - reason: Created the sources
 *
 *  Modification 2
 *    - modified on: 23/02/2004
 *    - reason: Made changes as per review comments.
 *  @date 23rd Feb, 2004
 *  @author Amruth Tadas.
 */
#ifndef _CSL_ULPD_H_
#define _CSL_ULPD_H_

#ifdef __cplusplus
extern "C" {
#endif

#include <csl.h>
#include <cslr_ulpd.h>

/**************************************************************************\
* ULPD global macro declarations
\**************************************************************************/

/** Flag for indicating PLL lock condition. */
#define CSL_ULPD_PLL_LOCK_ON            1

/**************************************************************************\
* ULPD global typedef declarations
\**************************************************************************/

/** @brief Enumeration for ULPD PLL clock
 *
 * This is used for specifying the PLL clock.
 *
 */
typedef enum {
	/** Set the PLL clock to 19.2Mhz  */
	CSL_ULPD_PLL_19MHZ_CLK=0,
	/** Set the PLL clock to 13Mhz 	  */
	CSL_ULPD_PLL_13MHZ_CLK=2,
	/** Set the PLL clock to 12Mhz    */
	CSL_ULPD_PLL_12MHZ_CLK=3
}CSL_UlpdPllCtrl;

/** @brief Enumeration for Sleep status flags
 *
 *  This is used to get the Sleep status of ULPD.
 *
 */
typedef enum {
	/** ULPD is in Big Sleep	 */
    CSL_ULPD_BIG_SLEEP       = CSL_ULPD_SLEEP_STATUS_BIG_SLEEP_MASK,
    /** ULPD is in Deep Sleep    */
    CSL_ULPD_DEEP_SLEEP      = CSL_ULPD_SLEEP_STATUS_DEEP_SLEEP_MASK
} CSL_UlpdSleep;


/** @brief Enumeration for interrupt status bits.
 *
 * This is used for interrupt status bits
 *
 */
typedef enum {
	/** Wakeup interrupt from USB	 */
    CSL_ULPD_INT_USBWKUP                   = CSL_ULPD_IT_STATUS_REG_IT_WAKEUP_USB_MASK,
    /** Interrupt because of 32-Khz counter Overflow           */
    CSL_ULPD_INT_ULPD_OVFL32               = CSL_ULPD_IT_STATUS_REG_OVERFLOW_32_MASK,
    /** Interrupt because of hi-frequency counter overflow     */
    CSL_ULPD_INT_ULPD_OVFLHIFREQ           = CSL_ULPD_IT_STATUS_REG_OVERFLOW_HI_FREQ_MASK,
    /** Interrupt because of gauging completion                */
    CSL_ULPD_INT_ULPD_ITGAUGING            = CSL_ULPD_IT_STATUS_REG_IT_GAUGING_MASK
}CSL_UlpdIntStat;


/** @brief Enumeration for reset status
 *
 * This is used for reset status bits
 *
 */
typedef enum {
	/** 32-Khz watch-dog timeout.	    */
    CSL_ULPD_RESET_WDT32K                    = CSL_ULPD_RESET_STATUS_32KWD_TIMEOUT_MASK,
    /** Security violation event        */
    CSL_ULPD_RESET_SECVIOLATE                = CSL_ULPD_RESET_STATUS_SECU_VIOLA_MASK,
    /** Secure watch-dog timeout event  */
    CSL_ULPD_RESET_WDTT32K_SECURE            = CSL_ULPD_RESET_STATUS_SECURE_WDTIMEOUT_MASK,
    /** Power-on reset                  */
    CSL_ULPD_RESET_PWRON                     = CSL_ULPD_RESET_STATUS_POWER_ON_RESET_MASK
} CSL_UlpdRstSrc;

/** @brief Enumeration for software requests for clock
 *
 * This is used for specifying the various S/W requests for clock.
 * This is also used for enabling/disabling the S/W requests.
 *
 * Note: A single enumeration is used to reduce code and to avoid having multiple
 * macros for same request type. As the position of bits for each request is not same in
 * request register(SOFT_REQ_REG) and en/disable register(SOFT_DISABLE_REQ_REG),
 * the request register(SOFT_REQ_REG) bit position has been used. This simplifies the
 * control command code size for @a CSL_ULPD_CMD_SOFTCLK_REQ_ACTIVE and
 * @a CSL_ULPD_CMD_SOFTCLK_REQ_INACTIVE.
 *
 */
typedef enum {
	/** ULPD_PLL clock request             */
	CSL_ULPD_DPLL_REQ=0x1,
	/** System clock request for USB host  */
	CSL_ULPD_USB_MCLK_REQ=0x8,
	/** System clock request for UART2     */
	CSL_ULPD_PERIPH_NREQ=0x20,
	/** ULPD_PLL clock request for USB OTG */
	CSL_ULPD_USB_OTG_DPLL_REQ=0x100,
	/** ULPD_PLL clock request for UART1   */
	CSL_ULPD_UART1_DPLL_REQ=0x200,
	/** ULPD_PLL clock request for UART2   */
	CSL_ULPD_UART2_DPLL_REQ=0x400,
	/** ULPD_PLL clock request for UART3   */
	CSL_ULPD_UART3_DPLL_REQ=0x800,
	/** ULPD_PLL clock request for MMC     */
	CSL_ULPD_MMC_DPLL_REQ=0x1000
} CSL_UlpdSoftReq;


/** @brief Enumeration for status information for software requests for clock
 *
 *  This is used for indicating the status of various S/W requests for clock.
 *
 */
typedef enum {
	/** Sleep request from OMAP                */
	CSL_ULPD_CHIP_IDLE_MASK =0x1,
	/** System clock request from OMAP         */
	CSL_ULPD_WAKEUP_NREQ_MASK=0x2,
	/** System clock request from UART2        */
	CSL_ULPD_PERIPH_NREQ_MASK=0x4,
	/** System clock request from USB client   */
	CSL_ULPD_USB_MCLK_REQ_MASK=0x20,
	/** ULPD_PLL clock request from USB client */
	CSL_ULPD_USB_DPLL_MCLK_REQ_MASK=0x40,
	/** ULPD_PLL clock request from USB host   */
	CSL_ULPD_USB_HOST_DPLL_REQ_MASK=0x100,
	/** ULPD_PLL clock request from UART1      */
	CSL_ULPD_UART1_DPLL_REQ_MASK= 0x200,
	/** ULPD_PLL clock request from UART2      */
	CSL_ULPD_UART2_DPLL_REQ_MASK= 0x400,
	/** ULPD_PLL clock request from UART3      */
	CSL_ULPD_UART3_DPLL_REQ_MASK= 0x800,
	/** ULPD_PLL clock request from MMC        */
	CSL_ULPD_MMC_DPLL_REQ_MASK = 0x1000
}CSL_UlpdStsReq;

/** @brief Enumeration for The frequency on the BCLK SDW_CLK_DIV_CTRL_SEL.
 *
 * This is used to Select the frequency to be configured for the divider ratio feild
 * which is applied to the APLL output clock to generate BCLK..
 */
 typedef enum {
     CSL_ULPD_SDW_DIV_RATIO_48MHZ   = 0x0000,
     CSL_ULPD_SDW_DIV_RATIO_32MHZ   = 0x0001,
     CSL_ULPD_SDW_DIV_RATIO_24MHZ   = 0x0002,
     CSL_ULPD_SDW_DIV_RATIO_19P2MHZ = 0x0003,
     CSL_ULPD_SDW_DIV_RATIO_16MHZ   = 0x0004,
     CSL_ULPD_SDW_DIV_RATIO_13P7MHZ = 0x0005,
     CSL_ULPD_SDW_DIV_RATIO_12MHZ   = 0x0006,
     CSL_ULPD_SDW_DIV_RATIO_9P6MHZ  = 0x0007,
     CSL_ULPD_SDW_DIV_RATIO_8MHZ    = 0x0008,
     CSL_ULPD_SDW_DIV_RATIO_6P9MHZ  = 0x0009,
     CSL_ULPD_SDW_DIV_RATIO_3MHZ    = 0x0012,
     CSL_ULPD_SDW_DIV_RATIO_1MHZ    = 0x0032
 }CSL_UlpdBclkFreq;

 /** @brief Enumeration for The frequency on the MCLK COM_CLK_DIV_CTRL_SEL.
 *
 * This is used to Select the frequency to be configured for the divider ratio feild
 * which is applied to the APLL output clock to generate MCLK..
 */
 typedef enum {
     CSL_ULPD_COM_DIV_RATIO_48MHZ   = 0x0000,
     CSL_ULPD_COM_DIV_RATIO_32MHZ   = 0x0001,
     CSL_ULPD_COM_DIV_RATIO_24MHZ   = 0x0002,
     CSL_ULPD_COM_DIV_RATIO_19P2MHZ = 0x0003,
     CSL_ULPD_COM_DIV_RATIO_16MHZ   = 0x0004,
     CSL_ULPD_COM_DIV_RATIO_13P7MHZ = 0x0005,
     CSL_ULPD_COM_DIV_RATIO_12MHZ   = 0x0006,
     CSL_ULPD_COM_DIV_RATIO_9P6MHZ  = 0x0007,
     CSL_ULPD_COM_DIV_RATIO_8MHZ    = 0x0008,
     CSL_ULPD_COM_DIV_RATIO_6P9MHZ  = 0x0009,
     CSL_ULPD_COM_DIV_RATIO_3MHZ    = 0x0012,
     CSL_ULPD_COM_DIV_RATIO_1MHZ    = 0x0032
 }CSL_UlpdMclkFreq;


/** @brief Enumeration for queries passed to @a CSL_ulpdHwControl()
 *
 * This is used to select the commands to control the operations
 * existing setup of ULPD. The arguments to be passed with each
 * enumeration if any are specified next to the enumeration
 */
typedef enum {
	/** Enable gauging : no argument	  */
	CSL_ULPD_CMD_GAUGE_EN = 0,
	/** Disable gauging : no argument	  */
	CSL_ULPD_CMD_GAUGE_DIS,
	/** Select auxiliary gauging clock : no argument	 */
	CSL_ULPD_CMD_GAUGE_AUX_CLK,
	/** Select 12-Mhz clock : no argument */
	 CSL_ULPD_CMD_GAUGE_12MHZ_CLK,
	/** Software request active for clock : argument type CSL_UlpdSoftReq */
	CSL_ULPD_CMD_SOFTCLK_REQ_ACTIVE,
	/** Inactivate software request for clock : argument type @a CSL_UlpdSoftReq
     */
	CSL_ULPD_CMD_SOFTCLK_REQ_INACTIVE,
	/** Low power request  : no argument  */
	CSL_ULPD_CMD_LOW_PWR_REQ,
	/** Clear Low power request  : no argument	 */
	CSL_ULPD_CMD_LOW_PWR_REQ_CLEAR,
	/** Deep Sleep transition is enabled : no argument.	 */
	CSL_ULPD_CMD_DEEP_SLEEP_TRAN_EN,
	/** Deep sleep transition is disabled : no argument	 */
	CSL_ULPD_CMD_DEEP_SLEEP_TRAN_DIS,
	/** Low power modes are enabled : no argument.  	 */
	CSL_ULPD_CMD_LOW_POWER_EN  ,
	/** Low power modes are disabled : no argument.      */
	CSL_ULPD_CMD_LOW_POWER_DIS ,
	/** Disable the H/W Clock request from Software : argument @a CSL_UlpdSoftReq */
	CSL_ULPD_CMD_HWCLK_REQ_DIS,
	/** Enable the H/W Clock request from Software : argument @a CSL_UlpdSoftReq  */
	CSL_ULPD_CMD_HWCLK_REQ_EN,
	/** Clear the reset status bits : argument @a CSL_UlpdRstSrc */
	CSL_ULPD_CMD_CLEAR_RESET_STATUS,
     
    /*------------------------*/

    /** @brief   Set divider ratio to the APLL output clock to generate BCLK. */
    CSL_ULPD_CMD_SDW_RATIO_SEL,
    
    /** @brief   BCLK clock software request active */
    CSL_ULPD_CMD_SDW_ULPD_PLL_CLK_REQ_ACTIVE,
    /** @brief   BCLK clock software request inactive */
    CSL_ULPD_CMD_SDW_ULPD_PLL_CLK_REQ_INACTIVE,

    /** @brief   BCLK is SYSTEM_CLOCK */
    CSL_ULPD_CMD_SDW_SYSCLK_SEL,
    /** @brief   BCLK is APLL output clock */
    CSL_ULPD_CMD_SDW_PLLCLK_SEL,

    /** @brief   Set divider ratio to the APLL output clock to generate MCLK. */
    CSL_ULPD_CMD_COM_RATIO_SEL,
    
    /** @brief   MCLK clock software request active */
    CSL_ULPD_CMD_COM_ULPD_PLL_CLK_REQ_ACTIVE,
    /** @brief   MCLK clock software request inactive */
    CSL_ULPD_CMD_COM_ULPD_PLL_CLK_REQ_INACTIVE,

    /** @brief   MCLK is SYSTEM_CLOCK */
    CSL_ULPD_CMD_COM_SYSCLK_SEL,
    /** @brief   MCLK is APLL output clock */
    CSL_ULPD_CMD_COM_PLLCLK_SEL,
    /** @brief Clock enable of the system clock for GPIO modules */
    CSL_ULPD_CMD_SYSTEM_CLK_EN,
    /** @brief   Clock disable of the system clock for GPIO modules */
    CSL_ULPD_CMD_SYSTEM_CLK_DIS,
    
    /** @brief   CAM.CLKOUT is the system clock */
    CSL_ULPD_CMD_CAM_CLK_DIV_SYSCLK,
    /** @brief   CAM.CLKOUT is the system clock */
    CSL_ULPD_CMD_CAM_CLK_DIV_EXTCLK,
    
    /** @brief   Enable of the CAM.CLKOUT */
    CSL_ULPD_CMD_CAM_CLOCK_EN,
    /** @brief   Disable of the CAM.CLKOUT */
    CSL_ULPD_CMD_CAM_CLOCK_DIS
  
} CSL_UlpdHwControlCmd;

/** @brief Enumeration for queries passed to @a CSL_ulpdGetHwStatus()
 *
 *  This is used to get the status of different operations or to get the
 *  existing setup of ULPD. The status information is returned with argument
 *  next to the enumeration
 */
 typedef enum {
	/** Get the Interrupt status information. response type @ CSL_UlpdIntStat
       *  (bit mask)
	 */
	CSL_ULPD_QUERY_INT_STATUS  = 1,
	/** Clock request status information : response type @a CSL_UlpdStsReq. */
	CSL_ULPD_QUERY_CLOCK_REQ_STATUS,
	/** ULPD PLL lock status. response type Uint16.	 */
	CSL_ULPD_QUERY_LOCK_STATUS,
	/** Sleep status. response type Uint16.	 */
	CSL_ULPD_QUERY_SLEEP_STATUS,
	/** Get the cause for reset. response type @a CSL_UlpdRstSrc (bit mask)	 */
	CSL_ULPD_QUERY_RESET_EVENT,
	/** Get the number of clock cycles of 32-Khz clock during Gauging time
	 *  : response type Uint32
	 */
	CSL_ULPD_QUERY_CNTR_32KHZ,
	/** Get the number of clock cycles of high freq clock during Gauging time
	 *  : response type Uint32
 	 */
	CSL_ULPD_QUERY_CNTR_HIGH_FREQ,

    /** Get divider ratio applied to the APLL output clock to generate BCLK
	 *  : response type @a CSL_UlpdBclkFreq
 	 */
    CSL_ULPD_QUERY_SDW_RATIO_SEL,
    /** Get BCLK clock software request Status */
    CSL_ULPD_QUERY_SDW_ULPD_PLL_CLK_REQ,
    /** Get clock selection for BCLK*/
    CSL_ULPD_QUERY_SDW_SYSCLK_PLLCLK_SEL,

    /** Get divider ratio applied to the APLL output clock to generate MCLK
	 *  : response type @a CSL_UlpdMclkFreq
 	 */
    CSL_ULPD_QUERY_COM_RATIO_SEL,
    /** Get MCLK clock software request Status */
    CSL_ULPD_QUERY_COM_ULPD_PLL_CLK_REQ,
    /** Get clock selection for MCLK*/
    CSL_ULPD_QUERY_COM_SYSCLK_PLLCLK_SEL,

    /** Get Clock enable status of the system clock for GPIO modules*/
    CSL_ULPD_QUERY_SYSTEM_CLK_EN,
    /** to Get the clock chosen as CAM.CLKOUT */
    CSL_ULPD_QUERY_CAM_CLK_DIV,
    /** Get CAM.CLKOUT status */
    CSL_ULPD_QUERY_CAM_CLOCK_EN

}CSL_UlpdHwStatusQuery;

/* @brief   The config-structure
 *
 * Used to configure the ULPD using CSL_ulpdHwSetupRaw(..)
 */
typedef struct {
	Uint16 GAUGING_CTRL_REG;
	Uint16 SETUP_ANALOG_CELL3_REG;
	Uint16 SETUP_ANALOG_CELL2_REG;
	Uint16 SETUP_ANALOG_CELL1_REG;
	Uint16 CLOCK_CTRL_REG;
	Uint16 SOFT_REQ_REG;
	Uint16 COUNTER_32_FIQ_REG;
 	Uint16 PLL_DIV_REG;
	Uint16 ULPD_PLL_CTRL_STATUS;
	Uint16 POWER_CTRL_REG;
	Uint16 SETUP_ANALOG_CELL4_REG;
	Uint16 SETUP_ANALOG_CELL5_REG;
	Uint16 SETUP_ANALOG_CELL6_REG;
	Uint16 SOFT_DISABLE_REQ_REG;
	Uint16 RESET_STATUS;
	Uint16 SDW_CLK_DIV_CTRL_SEL;
	Uint16 COM_CLK_DIV_CTRL_SEL;
	Uint16 CAM_CLK_CTRL;
	Uint16 SOFT_REQ_REG2;
}CSL_UlpdConfig;

/**
 * @brief   Default values for the config-structure
 */
#define CSL_ULPD_CONFIG_DEFAULTS {              \
	CSL_ULPD_GAUGING_CTRL_REG_RESETVAL,\
	CSL_ULPD_SETUP_ANALOG_CELL3_REG_RESETVAL,\
	CSL_ULPD_SETUP_ANALOG_CELL2_REG_RESETVAL,\
	CSL_ULPD_SETUP_ANALOG_CELL1_REG_RESETVAL,\
	CSL_ULPD_CLOCK_CTRL_REG_RESETVAL,\
	CSL_ULPD_SOFT_REQ_REG_RESETVAL,\
	CSL_ULPD_COUNTER_32_FIQ_REG_RESETVAL,\
 	CSL_ULPD_PLL_DIV_REG_RESETVAL,\
	CSL_ULPD_ULPD_PLL_CTRL_STATUS_RESETVAL,\
	CSL_ULPD_POWER_CTRL_REG_RESETVAL,\
	CSL_ULPD_SETUP_ANALOG_CELL4_REG_RESETVAL,\
	CSL_ULPD_SETUP_ANALOG_CELL5_REG_RESETVAL,\
	CSL_ULPD_SETUP_ANALOG_CELL6_REG_RESETVAL,\
	CSL_ULPD_SOFT_DISABLE_REQ_REG_RESETVAL,\
	CSL_ULPD_RESET_STATUS_RESETVAL,\
	CSL_ULPD_SDW_CLK_DIV_CTRL_SEL_RESETVAL,\
	CSL_ULPD_COM_CLK_DIV_CTRL_SEL_RESETVAL,\
	CSL_ULPD_CAM_CLK_CTRL_RESETVAL,\
	CSL_ULPD_SOFT_REQ_REG2_RESETVAL\
	}