📄 csl_dspmmu.h
字号:
/** ============================================================================
* @file csl_dspmmu.h
*
* @path $(CSLPATH)\arm\dspmmu\inc
*
* @desc API header file for DSP MMU CSL
*
*/
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ===========================================================================
*/
/* @(#) PSP/CSL 3.00.01.00[5912] (2004-04-18) */
/* =============================================================================
* Revision History
* ===============
* 22-June-2004 anj Incorporated CSL Arch changes.
* 22-Apr-2004 anj File Created.
*
* =============================================================================
*/
#ifndef _CSL_DSPMMU_H_
#define _CSL_DSPMMU_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <cslr_dspmmu.h>
#include <csl.h>
/**************************************************************************\
* DSP MMU global macro declarations
\**************************************************************************/
/** Constants for configuring entries in translation table,
* coarse page table and fine page table. These macros are
* used for defining the level1 and level2 descriptors.
*/
/** Shift to place index from virtual addr into Level2 descriptor */
#define CSL_DSPMMU_L2ENTRY_INDEX_SHIFT 2
/** Large page offset bits */
#define CSL_DSPMMU_LP_OFFSET_BITS 16
/** Large page base address mask */
#define CSL_DSPMMU_LP_BASE_ADDR_MASK \
(0xFFFFFFFF - ((1 << CSL_DSPMMU_LP_OFFSET_BITS) - 1))
/** Small page offset bits */
#define CSL_DSPMMU_SP_OFFSET_BITS 12
/** Small page base address mask */
#define CSL_DSPMMU_SP_BASE_ADDR_MASK \
(0xFFFFFFFF - ((1 << CSL_DSPMMU_SP_OFFSET_BITS) - 1))
/** Tiny page offset bits */
#define CSL_DSPMMU_TP_OFFSET_BITS 10
/** Tiny page base address mask */
#define CSL_DSPMMU_TP_BASE_ADDR_MASK \
(0xFFFFFFFF - ((1 << CSL_DSPMMU_TP_OFFSET_BITS) - 1))
/** Shift to place access permission field in Level2 descriptor */
#define CSL_DSPMMU_L2ENTRY_AP_SHIFT 4
/** Coarse page table entry bits */
#define CSL_DSPMMU_CPT_ENTRIES_BITS 8
/** Coarse page table base address mask*/
#define CSL_DSPMMU_CPT_BASE_ADDR_MASK \
(0xFFFFFFFF - ((1 << (CSL_DSPMMU_CPT_ENTRIES_BITS + 2)) - 1))
/** Section offset bits */
#define CSL_DSPMMU_SECTION_OFFSET_BITS 20
/** Section base address mask */
#define CSL_DSPMMU_SECTION_BASE_ADDR_MASK \
(0xFFFFFFFF - ((1 << CSL_DSPMMU_SECTION_OFFSET_BITS) - 1))
/** Fine page table entry bits */
#define CSL_DSPMMU_FPT_ENTRIES_BITS 10
/** Fine page table entry bits */
#define CSL_DSPMMU_FPT_BASE_ADDR_MASK \
(0xFFFFFFFF - ((1 << (CSL_DSPMMU_FPT_ENTRIES_BITS + 2)) - 1))
/** Translation table base mask */
#define CSL_DSPMMU_TTB_MASK \
((CSL_DSPMMU_TTB_H_REG_TTB_H_REG_MASK << 16 ) | \
(CSL_DSPMMU_TTB_L_REG_TTB_L_REG_MASK))
/** Shift to place access permission in level 1 descriptor */
#define CSL_DSPMMU_L1ENTRY_AP_SHIFT 10
/** Shift to place index from virtual addr in level 1 descriptor */
#define CSL_DSPMMU_L1ENTRY_INDEX_SHIFT 2
/** Shift to extract the MSB of physical address */
#define CSL_DSPMMU_PHY_ADDR_MSB_SHIFT 16
/** Shift to extract the LSB of physical address */
#define CSL_DSPMMU_PHY_ADDR_LSB_SHIFT 10
/** Shift to extract the index from virtual addr for Level 1 descriptor */
#define CSL_DSPMMU_VADDR_L1_SHIFT 20
/** Shift to extract the index for Level 2 descriptor */
#define CSL_DSPMMU_VADDR_L2_SHIFT 10
/**
* Shift to extract the index for Level 2 descriptor
* related to coarse page table
*/
#define CSL_DSPMMU_VADDR_L2CP_SHIFT 12
/**
* Mask to extract the index for Level 2 descriptor
* related to coarse page table
*/
#define CSL_DSPMMU_VADDR_L2CP_MASK 0xFF
/** Shift to extract the index for Level 2 descriptor related to
* fine page table.
*/
#define CSL_DSPMMU_VADDR_L2FP_SHIFT CSL_DSPMMU_VADDR_L2_SHIFT
/** Mask to extract the index for Level 2 descriptor related to
* fine page table.
*/
#define CSL_DSPMMU_VADDR_L2FP_MASK 0x3FF
/**
* Shift to extract the Level 1 index related
* to TLB CAM entry
*/
#define CSL_DSPMMU_VADDR_L1_H_SHIFT 2
/**
* Mask to extract the Level 1 index related
* to TLB CAM entry
*/
#define CSL_DSPMMU_VADDR_L1_L_MASK 0x3
/** Mask to check the permission fault */
#define CSL_PERMISSION_FAULT 0x4
/**
* DSP MMU global typedef declarations
*/
/**
* Enumeration for Hardware Walking Table Logic setting
*/
typedef enum {
/** Disables Walking Table Logic */
CSL_DSPMMU_WLKLGC_DISABLE = 0,
/** Enables Walking Table Logic */
CSL_DSPMMU_WLKLGC_ENABLE = 1
} CSL_DspmmuWlktblLogic;
/**
* Enumeration for DSP MMU Reset
*/
typedef enum {
/** Enables reset mode */
CSL_DSPMMU_RSTMODE_ENABLE = 0,
/** Disables reset mode */
CSL_DSPMMU_RSTMODE_DISABLE = 1
} CSL_DspmmuRstMode;
/**
* Enumeration for DSP MMU Power-down setting
*/
typedef enum {
/** Disables power-down mode */
CSL_DSPMMU_PWRDWNMODE_DISABLE = 0,
/** Enables power-down mode */
CSL_DSPMMU_PWRDWNMODE_ENABLE = 1
} CSL_DspmmuPwrDwnMode;
/**
* Enumeration for DSP MMU Autogating setting
*/
typedef enum {
/** Disables autogating */
CSL_DSPMMU_AUTOGTNG_DISABLE = 0,
/** Enables autogating */
CSL_DSPMMU_AUTOGTNG_ENABLE = 1
} CSL_DspmmuAutoGtng;
/**
* Enumeration for DSP MMU Control commands
*/
typedef enum {
/**
* @brief Enable Walking Table Logic
* @param NULL
*/
CSL_DSPMMU_CMD_ENABLEWTL = 0,
/**
* @brief Disable Walking Table Logic
* @param NULL
*/
CSL_DSPMMU_CMD_DISABLEWTL = 1,
/**
* @brief Enable DSP MMU
* @param NULL
*/
CSL_DSPMMU_CMD_ENABLEMMU = 2,
/**
* @brief Disable DSP MMU
* @param NULL
*/
CSL_DSPMMU_CMD_DISABLEMMU = 3,
/**
* @brief Reset DSP MMU
* @param NULL
*/
CSL_DSPMMU_CMD_RESETMMU = 4,
/**
* @brief Release DSP MMU from reset
* @param NULL
*/
CSL_DSPMMU_CMD_RESETRELEASEMMU = 5,
/**
* @brief Acknowledge the fault interrupt
* @param NULL
*/
CSL_DSPMMU_CMD_ACKINTR = 6,
/**
* @brief Set Translation Table Base
* @param Uint32
*/
CSL_DSPMMU_CMD_SETTTB = 7,
/**
* @brief Configure the base value field in lock register
* @param Uint8 *
*/
CSL_DSPMMU_CMD_CONFIGLOCKBASEVAL = 8,
/**
* @brief Perform global flush
* @param NULL
*/
CSL_DSPMMU_CMD_GLOBALFLUSH = 9,
/**
* @brief Flush one TLB entry
* @param Uint32 *
*/
CSL_DSPMMU_CMD_FLUSHTLBENTRY = 10,
/**
* @brief Configure the victim field in lock register
* @param Uint8 *
*/
CSL_DSPMMU_CMD_CONFIGLOCKVICTIM = 11
} CSL_DspmmuHwControlCmd;
/**
* Enumeration for DSP MMU Query commands
*/
typedef enum {
/**
* @brief Check whether WTL is active
* @param CSL_DspmmuWlktblLogic *
*/
CSL_DSPMMU_QUERY_ISWTLWORKING = 0,
/**
* @brief Check whether prefetch is active
* @param CSL_DspmmuPrefetchStatus *
*/
CSL_DSPMMU_QUERY_ISPREFETCHON = 1,
/**
* @brief Get the fault information
* @param CSL_DspmmuFltInfo *
*/
CSL_DSPMMU_QUERY_FAULTINFO = 2,
/**
* @brief Get cam ram values
* @param CSL_DspmmuQueryCamramEntry *
*/
CSL_DSPMMU_QUERY_CAMRAMENTRY = 3
} CSL_DspmmuHwStatusQuery;
/**
* Enumeration for DSP MMU Prefetch Status
*/
typedef enum {
/** Prefetch is over */
CSL_DSPMMU_PREFETCH_OVER = 0,
/** Prefetch is going on */
CSL_DSPMMU_PREFETCH_ON = 1
} CSL_DspmmuPrefetchStatus;
/**
* Page Type
*/
typedef enum {
/** Section page type (1MB) */
CSL_DSPMMU_PAGE_SECTION = CSL_DSPMMU_CAM_L_REG_SLST_SECTION,
/** Large page type (64KB) */
CSL_DSPMMU_PAGE_LARGE = CSL_DSPMMU_CAM_L_REG_SLST_LARGE,
/** Small page type (4KB) */
CSL_DSPMMU_PAGE_SMALL = CSL_DSPMMU_CAM_L_REG_SLST_SMALL,
/** Tiny page type (1KB) */
CSL_DSPMMU_PAGE_TINY = CSL_DSPMMU_CAM_L_REG_SLST_TINY
} CSL_DspmmuPageType;
/**
* Access Permissions
*/
typedef enum {
/** No Access */
CSL_DSPMMU_ACCESS_NONE = CSL_DSPMMU_RAM_L_REG_AP_NOACCESS,
/** Read only access */
CSL_DSPMMU_ACCESS_READONLY = CSL_DSPMMU_RAM_L_REG_AP_READONLY,
/** Full access */
CSL_DSPMMU_ACCESS_FULL = CSL_DSPMMU_RAM_L_REG_AP_FULLACCESS
} CSL_DspmmuAccessType;
/**
* Preserved Bit
*/
typedef enum {
/** Preserved bit not set */
CSL_DSPMMU_NOT_PRESERVED = 0,
/** Preserved bit set*/
CSL_DSPMMU_PRESERVED = 1
} CSL_DspmmuPreservedBit;
/**
* Valid Bit
*/
typedef enum {
/** Not a valid entry */
CSL_DSPMMU_NOT_VALID = 0,
/** valid entry */
CSL_DSPMMU_VALID = 1
} CSL_DspmmuValidBit;
/**
* Level2 Coares/Fine Page Table Descriptor Type
*/
typedef enum {
/** Invalid descriptor type*/
CSL_DSPMMU_L2DESC_FAULT = 0,
/** Large page descriptor type */
CSL_DSPMMU_L2DESC_LP = 1,
/** Small page descriptor type */
CSL_DSPMMU_L2DESC_SP = 2,
/** Tiny page descriptor type */
CSL_DSPMMU_L2DESC_TP = 3
} CSL_DspmmuL2DescType;
/** Level1 Translation Table Descriptor Type
*
*/
typedef enum {
/** Invalid level-1 descriptor type */
CSL_DSPMMU_L1DESC_FAULT = 0,
/** Coarse page table descriptor type */
CSL_DSPMMU_L1DESC_CPT = 1,
/** Section descriptor type */
CSL_DSPMMU_L1DESC_SECTION = 2,
/** Fine page table descriptor type */
CSL_DSPMMU_L1DESC_FPT = 3
} CSL_DspmmuL1DescType;
/**
* Level2 Coarse/Fine Page Table Entry
*/
typedef struct CSL_DspmmuL2ptEntry {
/** Start address of level-2 page table */
void *ptStartAddr;
/** Physical address corresponding to the entry */
void *phyAddr;
/** Virtual address corresponding to the entry */
Uint32 virtualAddr;
/** Page size */
CSL_DspmmuL2DescType descType;
/** Access permission for the page*/
CSL_DspmmuAccessType apBit;
} CSL_DspmmuL2ptEntry;
/**
* Translation Table Entry
*/
typedef struct CSL_DspmmuTtbEntry {
/** Translation table start address */
void *ttbAddr;
/** Physical address corresponding to the entry */
void *phyAddr;
/** Virtual address corresponding to the entry */
Uint32 virtualAddr;
/** Page type */
CSL_DspmmuL1DescType descType;
/** Access permission for the page*/
CSL_DspmmuAccessType access;
} CSL_DspmmuTtbEntry;
/**
* Translation Look Aside Buffer Entry
*/
typedef struct CSL_DspmmuTlbEntry {
/** Physical address corresponding to the entry*/
void *phyAddr;
/** Virtual address corresponding to the entry*/
Uint32 virtualAddr;
/** Page size defined by the entry*/
CSL_DspmmuPageType slstBit;
/** Access permissions for the page*/
CSL_DspmmuAccessType apBit;
/** Preserve the entry */
CSL_DspmmuPreservedBit pBit;
/** Validity of the entry */
CSL_DspmmuValidBit valid;
/** Base value to specify locked entries*/
Uint8 baseValue;
/** Current location where the entry has to be placed*/
Uint8 victim;
} CSL_DspmmuTlbEntry;
/**
* Fault related information
*/
typedef struct CSL_DspmmuFltInfo {
/** Logical address that generated fault*/
Uint32 faultAddr;
/** Cause of the fault*/
Uint16 faultEventType;
} CSL_DspmmuFltInfo;
/**
* CAM RAM Entry corresponding to TLB
*/
typedef struct CSL_DspmmuCamramEntry {
/** CAM entry of the TLB*/
Uint32 CAMentry;
/** RAM entry of the TLB*/
Uint32 RAMentry;
} CSL_DspmmuCamramEntry;
/**
* Structure used to setup DSP MMU
*/
typedef struct CSL_DspmmuHwSetup {
/** Ability to enable the walking table logic*/
CSL_DspmmuWlktblLogic walkingTableLogic;
/** Range of TLB entries to be locked*/
Uint8 lockTlbRange;
/** Reset Mode*/
CSL_DspmmuRstMode swResetMode;
/** Power-down Mode*/
CSL_DspmmuPwrDwnMode powerDownMode;
/** Autogating setting*/
CSL_DspmmuAutoGtng autoGating;
} CSL_DspmmuHwSetup;
/** structure to be passed to the CAM RAM entry query */
typedef struct CSL_DspmmuQueryCamramEntry {
/** TLB index - to be passed by the application */
Uint8 index;
/** CAM RAM entry of the TLB - return argument */
CSL_DspmmuTlbEntry tlbEntry;
} CSL_DspmmuQueryCamramEntry;
/** The default value for CSL_DspmmuHwSetup structure */
#define CSL_DSPMMU_HWSETUP_DEFAULTS { \
CSL_DSPMMU_WLKLGC_ENABLE, \
0x00000000, \
CSL_DSPMMU_RSTMODE_DISABLE, \
CSL_DSPMMU_PWRDWNMODE_DISABLE, \
CSL_DSPMMU_AUTOGTNG_ENABLE \
}
/**
* Structure used for raw setup of DSP MMU
*/
typedef struct CSL_DspmmuConfig {
/** Prefetch register */
Uint32 PREFETCH_REG;
/** Control register */
Uint32 CNTL_REG;
/** It acknowledge register */
Uint32 IT_ACK_REG;
/** MSB ttb register */
Uint32 TTB_H_REG;
/** LSB ttb register */
Uint32 TTB_L_REG;
/** Lock counter register */
Uint32 LOCK_REG;
/** TLB Load entry register */
Uint32 LD_TLB_REG;
/** CAM MSB register */
Uint32 CAM_H_REG;
/** CAM LSB register */
Uint32 CAM_L_REG;
/** RAM MSB register */
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -