csl_emifs.h

来自「dsp在音频处理中的运用」· C头文件 代码 · 共 880 行 · 第 1/2 页

/** @mainpage EMIFS CSL 3.x
 *
 * @section Introduction
 *
 * @subsection xxx Purpose and Scope
 * The purpose of this document is to identify a set of common CSL APIs for the
 * EMIFS module across various devices. The CSL developer is expected to refer to
 * this document while designing APIs for these modules. Some of the listed APIs
 * may not be applicable to a given EMIFS module. While in other cases this list
 * of APIs may not be sufficient to cover all the features of a particular EMIFS
 * Module. The CSL developer should use his discretion in designing new APIs or
 * extending the existing ones to cover these.
 *
 * @subsection aaa Terms and Abbreviations
 *   -# CSL:  Chip Support Library
 *   -# API:  Application Programmer Interface
 *
 * @subsection References
 *    -# CSL-001-DES, CSL 3.x Design Specification DocumentVersion 1.03
 *    -# OMAP3.2_121, OMAP3 EMIFS Specification, Ver 1.4
 *
 */

/** @file csl_dpll.h
 *
 *  @brief    Header file for functional layer of CSL
 *
 *  Description
 *    - The different* @brief Enumerations, structure definitions
 *      and function declarations
 *
 *  Modification 2
 *    - modified on: 30/03/2004
 *    - reason: Doxygenation of the comments to enable document generation
 *
 *  Modification 1
 *    - modified on: 29/03/2004
 *    - reason: Created the initail file from OMAP5905 CSL release on 7th Oct 2003
 *
 *  @date 29th March, 2004
 *  @author Prakash V. Gudnavar.
 */

#ifndef _CSL_EMIFS_H_
#define _CSL_EMIFS_H_

#ifdef __cplusplus
extern "C" {
#endif

#include <csl.h>
#include <cslr_emifs.h>

/**************************************************************************\
* EMIFS global macro declarations
\**************************************************************************/

#define CSL_EMIFS_MAX_CS	  4
/**************************************************************************\
* EMIFS global typedef declarations
\**************************************************************************/

/** @brief Enumeration for address increment mode for second 16 bit write
 * with 32 bit writes to 16 bit memories
 */
typedef enum {
    /** Address is incremented for second 16 bit write with 32 bit writes to
    16 bit memories */
    CSL_EMIFS_WRT32ADDRMODE_INCR      = 		 0,
    /** Address NOT incremented for second 16 bit write with 32 bit writes
    to 16 bit memories */
    CSL_EMIFS_WRT32ADDRMODE_CONST     = 		 1
} CSL_EmifsWrt32AddrMode;

/** @brief Enumeration for length of Address Valid pulse. */
typedef enum {
    /** Address Valid length is 1 clock cycle */
    CSL_EMIFS_ADVHOLD_1 	  =		     0,
    /** Address Valid length is 2 clock cycles */
    CSL_EMIFS_ADVHOLD_2 	  =		     1
} CSL_EmifsAdvHold;

/** @brief Enumeration for Bus Transition mode. */
typedef enum {
    /** Bus turn around cycles are inserted between each read operation to
    any transaction to avoid data contention. */
    CSL_EMIFS_BUSTRANSMODE_RDONLY	 =		    0,
    /** Bus Turn around cycles are inserted between WR -> RD and WR -> WR
    apart from the RD to any  transaction */
    CSL_EMIFS_BUSTRANSMODE_RDWRT	 =		    1
} CSL_EmifsBusTransMode;

/** @brief Enumeration for Flash Clock Divide Value */
typedef enum {
    /** Divide by 1 */
    CSL_EMIFS_FLASHCLKDIV_1	  =		     0,
    /** Divide by 2 */
    CSL_EMIFS_FLASHCLKDIV_2	  =		     1,
    /** Divide by 4 */
    CSL_EMIFS_FLASHCLKDIV_4	  =		     2,
    /** Divide by 6 */
    CSL_EMIFS_FLASHCLKDIV_6	  =		     3
} CSL_EmifsFlashClkDiv;

/** @brief Enumeration for handshake mode */
typedef enum {
    /** Full hand shaking protocol mode */
    CSL_EMIFS_HANDSHAKEMODE_FULL       =		  0,
    /** Non-full handshaking protocol mode */
    CSL_EMIFS_HANDSHAKEMODE_NONFULL    =		  1
} CSL_EmifsHandshakeMode;

/** @brief Enumeration for data retime ON/OFF */
typedef enum {
    /** Retime the data coming from the external bus with CLK */
    CSL_EMIFS_DATARETIME_ON	  =		     1,
    /** Do not retime the data. */
    CSL_EMIFS_DATARETIME_OFF	  =		     0
} CSL_EmifsDataRetime;

/** @brief Enumeration for dyanamic wait state */
typedef enum {
    /** Enable dynamic wait states */
    CSL_EMIFS_DYNWAITSTATE_ENABLE   =		       0,
    /** Disable dynamic wait states */
    CSL_EMIFS_DYNWAITSTATE_DISABLE  =		       1
} CSL_EmifsDynWaitState;

/** @brief Enumeration for Read Modes. Read mode is specific to protocol and is set as a part of Boot Configuration. */
typedef enum {
    /** Asynchronous read */
    CSL_EMIFS_BOOTRDMODE_ASYNC	  =		     0,
    /** Page Mode Read - 4 words per page */
    CSL_EMIFS_BOOTRDMODE_PAGEMD4 =		    1,
    /** Page Mode Read - 8 words per page */
    CSL_EMIFS_BOOTRDMODE_PAGEMD8 =		    2,
    /** Page Mode Read - 16 words per page (Default when flash sync boot is
    active) */
    CSL_EMIFS_BOOTRDMODE_PAGEMD16 =		     3,
    /** Synchronous Burst Read - TI burst protocol */
    CSL_EMIFS_BOOTRDMODE_TIBURST =		    4,
    /** Synchronous Burst Read - Intel Smart3 protocol */
    CSL_EMIFS_BOOTRDMODE_INTELSMART3 =			5,
    /** Synchronous Burst Read - TI ACE ROM */
    CSL_EMIFS_BOOTRDMODE_TIACEROM =		     7
} CSL_EmifsBootRdMode;

/** @brief Enumeration for address/data bus multiplexing */
typedef enum {
    /** Address/data bus multiplexed */
    CSL_EMIFS_ADBUSMUX_TRUE	  =		     1,
    /** Address/data bus not multiplexed */
    CSL_EMIFS_ADBUSMUX_FALSE	  =		     0
} CSL_EmifsADBusMux;

/** @brief Enumeration for databus width */
typedef enum {
    /** Data bus width 16 bits */
    CSL_EMIFS_DATABUSSIZE_16	  =		     0,
    /** Data bus width 32 bits */
    CSL_EMIFS_DATABUSSIZE_32	  =		     1
} CSL_EmifsDataBusSize;

/** @brief Enumeration for boot chip select */
typedef enum {
    /** Address 0x00000000 corresponds to CS0 */
    CSL_EMIFS_ARMBOOTMODE_CS0	 =		    0,
    /** Address 0x00000000 corresponds to CS3 */
    CSL_EMIFS_ARMBOOTMODE_CS3	 =		    1
} CSL_EmifsArmBootMode;

/** @brief Enumerations for EMIFS operations
 *
 * This enumeration is used to select the control command that has to be
 * passed to the CSL_emifsHwControl function.
 */
typedef enum {
    /** Disable EMIFS power down (argument type: NULL ) */
    CSL_EMIFS_CMD_POWER_DOWN_DISABLE =			0,
    /** Enable EMIFS power down (argument type: NULL ) */
    CSL_EMIFS_CMD_POWER_DOWN_ENABLE  =			1,
    /** Disable global power down (argument type: NULL ) */
    CSL_EMIFS_CMD_GBLPOWER_DOWN_DISABLE =		   2,
    /** Enable global power down (argument type: NULL ) */
    CSL_EMIFS_CMD_GBLPOWER_DOWN_ENABLE =		  3,
    /** Disable write protect for all flash devices (argument type: NULL ) */
    CSL_EMIFS_CMD_WRITE_PROTECT_DISABLE =		   4,
    /** Enable Write Protect for all Flash devices (argument type: NULL ) */
    CSL_EMIFS_CMD_WRITE_PROTECT_ENABLE =		  5
} CSL_EmifsHwControlCmd;

/** @brief Enumerations for h/w status query
 *
 * This enumeration is used to select the hardware status query that has to be
 * passed to the CSL_emifsGetHwStatus function.
 */
typedef enum {
    /** Get abort status */
    CSL_EMIFS_QUERY_ABORT_STATUS    =		       0,
    /** Get ready status */
    CSL_EMIFS_QUERY_READY_STATUS    =		       1
} CSL_EmifsHwStatusQuery;


/** Defines reset value of ARM boot mode */
#define CSL_EMIFS_DEFAULTS_ARMBOOTMODE	   CSL_EMIFS_CR_BM_RESETVAL

/** Defines reset values of CSL_EmifsChipConfig structure members. */
#define CSL_EMIFS_DEFAULTS_CHIPCONFIG	{   \
	    (Uint16)CSL_EMIFS_NCS_PGWSTEN_RESETVAL, \
	    (Uint16)CSL_EMIFS_NCS_BTWST_RESETVAL, \
	    (Uint16)CSL_EMIFS_NCS_PGWSWLEN_RESETVAL, \
	    (Uint16)CSL_EMIFS_NCS_WRWST_RESETVAL, \
	    (Uint16)CSL_EMIFS_NCS_RDWST_RESETVAL, \
	    (CSL_EmifsWrt32AddrMode)CSL_EMIFS_NCS_FL_RESETVAL, \
	    (Uint16)CSL_EMIFS_ANCS_OESETUP_RESETVAL, \
	    (Uint16)CSL_EMIFS_ANCS_OEHLD_RESETVAL, \
	    (CSL_EmifsAdvHold)CSL_EMIFS_ANCS_ADVHLD_RESETVAL, \
	    (CSL_EmifsBusTransMode)CSL_EMIFS_ANCS_BTMD_RESETVAL, \
	    (CSL_EmifsFlashClkDiv)CSL_EMIFS_NCS_FCLKDIV_RESETVAL, \
	    (CSL_EmifsDataRetime)CSL_EMIFS_NCS_RT_RESETVAL, \
	    (CSL_EmifsDynWaitState)CSL_EMIFS_DWSCR_DWSEN0_RESETVAL, \
	    (CSL_EmifsHandshakeMode)CSL_EMIFS_DWSCR_FHSEN0_RESETVAL \
	}

/** Defines reset values of CSL_EmifsBootConfig structure members. */
#define CSL_EMIFS_DEFAULTS_BOOTCONFIG  { \
	    (CSL_EmifsBootRdMode)CSL_EMIFS_NCS_RDMODE_RESETVAL, \
	    (CSL_EmifsDataBusSize)CSL_EMIFS_NCS_BW_RESETVAL, \
	    (CSL_EmifsADBusMux)CSL_EMIFS_NCS_MAD_RESETVAL \
	}

/** Defines reset values of CSL_EmifsConsecAccess structure members. */
#define CSL_EMIFS_DEFAULTS_CONSECACCESS  { \
	    (Uint8)CSL_EMIFS_PR_OCPI_RESETVAL, \
	    (Uint8)CSL_EMIFS_PR_DMA_RESETVAL, \
	    (Uint8)CSL_EMIFS_PR_DSP_RESETVAL, \
	    (Uint8)CSL_EMIFS_PR_MPU_RESETVAL \
	}

/** Defines reset values of CSL_EmifsDynPriTimeout structure members. */
#define CSL_EMIFS_DEFAULTS_DYNPRITIMEOUT  { \
	   (Uint8)CSL_EMIFS_DAPTR3_OCPI_RESETVAL, \
	    (Uint8)CSL_EMIFS_DAPTR1_DMA_RESETVAL, \
	    (Uint8)CSL_EMIFS_DAPTR2_DSP_RESETVAL \
	}

/** @brief Structure containing SDRAM configuration parameters.
 *
 * This structure is part of the CSL_EmifsHwSetup structure, and is passed
 * as a member of the CSL_EmifsHwSetup to the CSL_emifsHwSetup OR
 * CSL_emifsOpen function. Also the structure is used to collect the
 * current chip configuration information from the CSL_emifsGetHwStatus
 * function.
 */
typedef struct CSL_EmifsChipConfig {
    /** Number of wait states for Page mode ROM access within the page. */
    Uint16		    pageWtStates;
    /** Number of wait states for read to write bus transition */
    Uint16		    busTransWtStates;
    /** Duration of WE pulse */
    Uint16		    wePulseLength;
    /** Number of wait states for write operation */
    Uint16		    wrtWtStates;
    /** Number of wait states for asynchronous read operation. */
    Uint16		    rdWtStates;
    /** Address change mode for second 16bit writes with 32 bit writes to
    16 bit memories. */
    CSL_EmifsWrt32AddrMode  wrt32AddrMode;
    /** Number of cycles inserted from CS low to OE low */
    Uint16		    oeSetup;
    /** Number of cycles inserted from OE high to CS high */
    Uint16		    oeHold;
    /** Length of Address Valid pulse */
    CSL_EmifsAdvHold	    advHold;
    /** Bus turn around time mode */
    CSL_EmifsBusTransMode   busTransMode;
    /** Flash Clock Divider */
    CSL_EmifsFlashClkDiv    flashClkDiv;
    /** Data retime On/Off mode */
    CSL_EmifsDataRetime     dataRetime;
    /** Dynamic wait stateEnable/Disable */
    CSL_EmifsDynWaitState   dynWaitState;
    /** Handshake protocol mode */
    CSL_EmifsHandshakeMode  handshakeMode;
} CSL_EmifsChipConfig;

/** @brief Structure containing EMIFS boot configuration parameters. */
typedef struct CSL_EmifsBootConfig {
    /** Boot read mode. */
    CSL_EmifsBootRdMode     bootRdMode;
    /** Data bus width */
    CSL_EmifsDataBusSize    dataBusSize;
    /** Address/data bus muxing */
    CSL_EmifsADBusMux	    aDBusMux;
} CSL_EmifsBootConfig;

/** @brief Structure containing number of consecutive accesses allowed for
  * each requestor.
  *
  * This structure captures number of consecutive accesses allowed for each
  * requestor. This structure is part of the CSL_EmifsHwSetup structure, and
  * is passed as a member of the CSL_EmifsHwSetup parameter to the
  * CSL_EmifsHwSetup function. Also the structure is used to collect the
  * setup information (relating to consecutive access settings) from the
  * CSL_emifsGetHwStatus function.
  */
typedef struct CSL_EmifsConsecAccess {
    /** OCPI Consecutive Accesses ( < 16 ) */
    Uint8		    ocpiNumConsecAccess;
    /** DMA Consecutive Accesses ( < 16 ) */
    Uint8		    dmaNumConsecAccess;
    /** DSP Consecutive Accesses ( < 8 ) */
    Uint8		    dspNumConsecAccess;
    /** MPU Consecutive Accesses ( < 8 ) */
    Uint8		    mpuNumConsecAccess;
} CSL_EmifsConsecAccess;

/** @brief Structure containing dynamic priority timeout values for each
  * requestor.
  *
  * This structure captures dynamic priority timeout values for each
  * requestor. This structure is part of the CSL_EmifsHwSetup structure,
  * and is passed as a member of the CSL_EmifsHwSetup to the
  * CSL_emifsHwSetup function.
  */
typedef struct CSL_EmifsDynPriTimeout {
    /** OCPI Dynamic arbitration priority  timeout */
    Uint8		    ocpiPriorityTimeout;
    /** DMA Dynamic arbitration priority timeout */
    Uint8		    dmaPriorityTimeout;
    /** DSP Dynamic arbitration priority timeout */
    Uint8		    dspPriorityTimeout;
} CSL_EmifsDynPriTimeout;

/** @brief Structure containing EMIFS setup parameters.
 *
 * This structure is used to pass setup parameters to the CSL_EmifsHwSetup
 * function, which in turn writes to various registers of the EMIFS interface
 * hardware to configure the peripheral for a particular data transfer.
 * Note that CSL_EMIFS_MAX_CS is a macro that defines number of chip selects.
 *
 */
typedef struct CSL_EmifsHwSetup {
    /** Boot chip select */
    CSL_EmifsArmBootMode    armBootMode;
    /** Chip select configuration structure for each CS */
    CSL_EmifsChipConfig     *chipConfig[CSL_EMIFS_MAX_CS];
    /** Boot mode configuration for each CS */
    CSL_EmifsBootConfig     *bootConfig[CSL_EMIFS_MAX_CS];
    /** Priority Consecutive Accesses */
    CSL_EmifsConsecAccess   *consecAccess;
    /** Dynamic Arbitration Priority Timeout */
    CSL_EmifsDynPriTimeout  *dynPriTimeout;
} CSL_EmifsHwSetup;

/**
 * @brief   The config-structure
 *
 * Used to configure the EMIFS using CSL_emifsHwSetupRaw(..)
 */
typedef struct  {
    Uint32 PR;
    Uint32 CR;
    Uint32 NCS[4];
    Uint32 DAPTR1;
    Uint32 DAPTR2;
    Uint32 DAPTR3;
    Uint32 DWSCR;
    Uint32 ATOR;
    Uint32 ANCS[4];
} CSL_EmifsConfig;

/**
 * @brief   Default values for the config-structure
 */
#define CSL_EMIFS_CONFIG_DEFAULTS {         \
            CSL_EMIFS_PR_RESETVAL,\
            CSL_EMIFS_CR_RESETVAL,\
            { CSL_EMIFS_NCS_RESETVAL, CSL_EMIFS_NCS_RESETVAL, CSL_EMIFS_NCS_RESETVAL, CSL_EMIFS_NCS_RESETVAL}\
            CSL_EMIFS_DAPTR1_RESETVAL,\
            CSL_EMIFS_DAPTR2_RESETVAL,\
            CSL_EMIFS_DAPTR3_RESETVAL,\
            CSL_EMIFS_DWSCR_RESETVAL,\
            CSL_EMIFS_ATOR_RESETVAL,\
            { CSL_EMIFS_ANCS_RESETVAL, CSL_EMIFS_ANCS_RESETVAL, CSL_EMIFS_ANCS_RESETVAL, CSL_EMIFS_ANCS_RESETVAL}\
        }

/** @brief Structure in which the abort status of a transaction is returned.
  *
  * The CSL_EmifsAbortStatus structure is used to get abort status of a
  * transaction. This structure is passed as an argument to
  * CSL_emifsGetHwStatus function when the query used is
  * CSL_EMIFS_QUERY_ABORTSTATUS.
  */
typedef struct CSL_EmifsAbortStatus {
    /** 1 if abort has occurred */
    Bool		    abortFlag;
    /** Address of transaction aborted */
    Uint32		    abortAddress;
    /** Id of the Host whose transaction was aborted */
    Uint16		    abortHostId;
    /** 1 on Timeout Error. */
    Bool		    timeOutError;
    /** 1 on Restricted Access Mode Error */
    Bool		    ramdError;
} CSL_EmifsAbortStatus;

/** @brief This object contains the reference to the instance of EMIFS opened
 *  using the @a CSL_emifsOpen().
 *
 *  The pointer to this, is passed to all EMIFS CSL APIs.
 */
typedef struct CSL_EmifsObj {
	/** This is a pointer to the registers of the instance of EMIFS
     *  referred to by this object
     */
	CSL_EmifsRegsOvly regs;
	/** This is the instance of EMIFS being referred to by this object  */
	CSL_InstNum  	perNum;
} CSL_EmifsObj;

typedef struct CSL_EmifsObj *CSL_EmifsHandle;

/** @brief This will have the base-address information for the peripheral
 *  instance
 */
typedef struct {
	/** Base-address of the Configuration registers of the peripheral
	 */
	CSL_EmifsRegsOvly	regs;
} CSL_EmifsBaseAddress;


/** @brief Module specific parameters. Present implementation doesn't have
 *  any module specific parameters.
 */
typedef struct{
	/** Bit mask to be used for module specific parameters.
         *  The below declaration is just a place-holder for future