csl_uwire.h
来自「dsp在音频处理中的运用」· C头文件 代码 · 共 660 行 · 第 1/2 页
H
660 行
/** ============================================================================
* @file csl_uwire.h
*
* @path $(CSLPATH)\arm\uwire\src
*
* @desc API header file for UWIRE CSL
*
*/
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ===========================================================================
*/
/* @(#) PSP/CSL 3.00.01.00[5912] (2004-04-18) */
/* =============================================================================
* Revision History
* ===============
*
* 24-June-2004 rr File Created.
*
* =============================================================================
*/
#ifndef _CSL_UWIRE_H_
#define _CSL_UWIRE_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <cslr_uwire.h>
#include <csl.h>
/**
* UWIRE global typedef declarations
*/
/**
*@brief Enumeration for Index
*/
typedef enum {
CSL_UWIRE_INDEX_CS0 = CSL_UWIRE_CSR_INDEX_CS0,
/**<Select the first external device */
CSL_UWIRE_INDEX_CS1 = CSL_UWIRE_CSR_INDEX_CS1,
/**<Select the second external device */
CSL_UWIRE_INDEX_CS2 = CSL_UWIRE_CSR_INDEX_CS2,
/**<Select the third external device */
CSL_UWIRE_INDEX_CS3 = CSL_UWIRE_CSR_INDEX_CS3
/**<Select the fourth external device */
}CSL_UwireIndex;
/**
*@brief Enumeration for external clock division
*/
typedef enum {
CSL_UWIRE_CLK_DIV2 = CSL_UWIRE_SR3_CK_FREQ_EXTCLKDIV2,
/**<divide external clock by 2 */
CSL_UWIRE_CLK_DIV4 = CSL_UWIRE_SR3_CK_FREQ_EXTCLKDIV4,
/**<divide external clock by 4 */
CSL_UWIRE_CLK_DIV7 = CSL_UWIRE_SR3_CK_FREQ_EXTCLKDIV7,
/**<divide external clock by 7 */
CSL_UWIRE_CLK_DIV10 = CSL_UWIRE_SR3_CK_FREQ_EXTCLKDIV10
/**<divide external clock by 10 */
}CSL_UwireClkDiv;
/**
*@brief Enumeration for internal clock division
*/
typedef enum {
CSL_UWIRE_CSCLK_DIV2 = CSL_UWIRE_SR2_CS2_FRQ_INTCLKDIV2,
/**<divide internal clock by 2 */
CSL_UWIRE_CSCLK_DIV4 = CSL_UWIRE_SR2_CS2_FRQ_INTCLKDIV4,
/**<divide internal clock by 4 */
CSL_UWIRE_CSCLK_DIV8 = CSL_UWIRE_SR2_CS2_FRQ_INTCLKDIV8
/**<divide internal clock by 8 */
}CSL_UwireCsClkdiv;
/**
* @brief Enumeration of the control commands
*
* These are the control commands that could be used with
* CSL_uwireHwControl(..). Some of the commands expect an
* argument as documented along-side the description of
* the command.
*
*/
typedef enum {
CSL_UWIRE_CMD_LTDR,
/**<
* @brief load transmit data register
* @param Uint16
*/
CSL_UWIRE_CMD_SETACT,
/**<
* @brief Set the chip select of the selected device to
* its active level
* @param NULL
*/
CSL_UWIRE_CMD_SETINACT,
/**<
* @brief Set the chip select of the selected device to
* its inactive level
* @param NULL
*/
CSL_UWIRE_CMD_STARTEN,
/**<
* @brief Start a write and/or read process
* @param NULL
*/
CSL_UWIRE_CMD_STARTDB,
/**<
* @brief Do not start a write and/or read process
* @param NULL
*/
CSL_UWIRE_CMD_CSINDEX,
/**<
* @brief Sets the index for selecting the external device
* @param
*/
CSL_UWIRE_CMD_NBWR,
/**<
* @brief Number of bits to transmit
* @param Uint8
*/
CSL_UWIRE_CMD_NBRD
/**<
* @brief Number of bits to receive
* @param Uint8
*/
}CSL_UwireHwControlCmd;
/**
* @brief Enumeration of the queries
*
* These are the queries that could be used with CSL_uwireGetHwStatus(..).
* The queries return a value through the object pointed to by the pointer
* that it takes as an argument. The argument supported by the query is
* documented along-side the description of the query.
*/
typedef enum {
CSL_UWIRE_QUERY_RDR,
/**<
* @brief Query the receive data register
* @param (Uint16 *)
*/
CSL_UWIRE_QUERY_RDRB,
/**<
* @brief Query the receive data register state
* @param (Bool *)
*/
CSL_UWIRE_QUERY_CSRB
/**<
* @brief Query to check CSR is ready to receive data
* @param (Bool *)
*/
}CSL_UwireHwStatusQuery;
/** @brief The device setup structure
*
* Used to configure the external devices connected
*/
typedef struct CSL_UwiredevSetup {
Bool csRedChk;/**< check if CS is ready */
CSL_UwireCsClkdiv intClkDiv;/**< frequency of the serial clock SCLK */
Bool csActLvl;/**< active level of the CS chip-select */
Bool csEdWt;/**< active edge of SCLK for writing */
Bool csEdRd; /**< active edge of SCLK for reading */
}CSL_UwiredevSetup;
/** @brief Module specific parameters. Present implementation doesn't have
* any module specific parameters.
*/
typedef struct{
/** Bit mask to be used for module specific parameters.
* The below declaration is just a place-holder for future
* implementation.
*/
CSL_BitMask16 flags;
} CSL_UwireParam;
/** @brief Module specific context information. Present implementation doesn't have
* any Context information.
*/
typedef struct {
/** Context information of UWIRE.
* The below declaration is just a place-holder for future
* implementation.
*/
Uint16 contextInfo;
} CSL_UwireContext;
/**
* @brief The setup-structure
*
* Used to configure the uwire using CSL_uwireHwSetup(..)
*/
typedef struct CSL_UwireHwSetup {
CSL_UwireIndex chipSelectIndex;
/**< Set the index for selecting the external device*/
CSL_UwireClkDiv extClkDiv;
/**< Defines the frequency of the internal clock*/
Bool extClkEnable;
/**< Clock enable*/
Bool clkPolSet;
/**< Serial clock Polarity setup*/
Bool csTogEnable;
/**< Possible only in auto transmit mode for active level selection*/
Bool autoTransEnable;
/**< Auto transmit mode */
Bool intrEnable;
/**< interrupt enable*/
Bool dmaTransEnable;
/**< DMA transmit mode*/
CSL_UwiredevSetup devSetup[4];
/**< Set up the interface for a particular device*/
} CSL_UwireHwSetup;
/**
* Default values for CSL_UwireHwSetup structure
*/
#define CSL_UWIRE_HWSETUP_DEFAULTS { \
(CSL_UwireIndex)CSL_UWIRE_CSR_INDEX_RESETVAL, \
(CSL_UwireClkDiv)CSL_UWIRE_SR3_CK_FREQ_RESETVAL, \
(Bool)CSL_UWIRE_SR3_CLK_EN_RESETVAL, \
(Bool)CSL_UWIRE_SR4_CLK_IN_RESETVAL, \
(Bool)CSL_UWIRE_SR5_CS_TOGGLE_TX_EN_RESETVAL, \
(Bool)CSL_UWIRE_SR5_AUTO_TX_EN_RESETVAL, \
(Bool)CSL_UWIRE_SR5_IT_EN_RESETVAL, \
(Bool)CSL_UWIRE_SR5_DMA_TX_EN_RESETVAL, \
{{ \
CSL_UWIRE_SR1_CS0_CHK_RESETVAL, \
(CSL_UwireCsClkdiv)CSL_UWIRE_SR1_CS0_FRQ_RESETVAL, \
CSL_UWIRE_SR1_CS0CS_LVL_RESETVAL, \
CSL_UWIRE_SR1_CS0_EDGE_WR_RESETVAL, \
CSL_UWIRE_SR1_CS0_EDGE_RD_RESETVAL \
}, \
\
{CSL_UWIRE_SR1_CS1_CHK_RESETVAL, \
(CSL_UwireCsClkdiv)CSL_UWIRE_SR1_CS1_FRQ_RESETVAL, \
CSL_UWIRE_SR1_CS1CS_LVL_RESETVAL, \
CSL_UWIRE_SR1_CS1_EDGE_WR_RESETVAL, \
CSL_UWIRE_SR1_CS1_EDGE_RD_RESETVAL \
}, \
{CSL_UWIRE_SR2_CS2_CHK_RESETVAL, \
(CSL_UwireCsClkdiv)CSL_UWIRE_SR2_CS2_FRQ_RESETVAL, \
CSL_UWIRE_SR2_CS2CS_LVL_RESETVAL, \
CSL_UWIRE_SR2_CS2_EDGE_WR_RESETVAL, \
CSL_UWIRE_SR2_CS2_EDGE_RD_RESETVAL \
}, \
{CSL_UWIRE_SR2_CS3_CHK_RESETVAL, \
(CSL_UwireCsClkdiv)CSL_UWIRE_SR2_CS3_FRQ_RESETVAL, \
CSL_UWIRE_SR2_CS3CS_LVL_RESETVAL, \
CSL_UWIRE_SR2_CS3_EDGE_WR_RESETVAL, \
CSL_UWIRE_SR2_CS3_EDGE_RD_RESETVAL \
}} \
}
/**
* @brief The config-structure
*
* Used to configure the uwire using CSL_uwireHwSetupRaw(..)
*/
typedef struct {
volatile Uint16 TDR_RDR; /**< TDR_RDR register**/
volatile Uint16 CSR; /**< CSR register**/
volatile Uint16 SR1; /**< SR1 register**/
volatile Uint16 SR2; /**< SR2 register**/
volatile Uint16 SR3; /**< SR3 register**/
volatile Uint16 SR4; /**< SR4 register**/
volatile Uint16 SR5; /**< SR5 register**/
}CSL_UwireConfig;
/**
* Default values for the config-structure
*/
#define CSL_UWIRE_CONFIG_DEFAULTS { \
CSL_UWIRE_TDR_RDR_RESETVAL, \
CSL_UWIRE_CSR_RESETVAL, \
CSL_UWIRE_SR1_RESETVAL, \
CSL_UWIRE_SR2_RESETVAL, \
CSL_UWIRE_SR3_RESETVAL, \
CSL_UWIRE_SR4_RESETVAL, \
CSL_UWIRE_SR5_RESETVAL \
}
/** @brief This object contains the reference to the instance of UWIRE opened
* using the @a CSL_uwireOpen().
*
* The pointer to this, is passed to all UWIRE CSL APIs.
*/
⌨️ 快捷键说明
复制代码Ctrl + C
搜索代码Ctrl + F
全屏模式F11
增大字号Ctrl + =
减小字号Ctrl + -
显示快捷键?