_csl_mmu.h

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/** ============================================================================
 *   @file  _csl_mmu.h
 *
 *   @path  $(CSLPATH)\arm\mmu\src
 *
 *   @desc  Header file for internal use of CSL module for MMU
 *
 */

/*  ============================================================================
 *   Copyright (c) Texas Instruments Inc 2002, 2003, 2004
 *
 *   Use of this software is controlled by the terms and conditions found in the
 *   license agreement under which this software has been supplied.
 *   ===========================================================================
 */
 
/*  @(#) PSP/CSL 3.00.01.00[5912] (2004-04-18)  */

/* =============================================================================
 *  Revision History
 *  ===============
 *  26-Apr-2004 ar File Created.
 *
 * =============================================================================
 */

#ifndef __CSL_MMU_H_
#define __CSL_MMU_H_

#ifdef __cplusplus
extern "C" {
#endif

/** MMU global macro declarations */
 
/** Bit position of the Cacheable bit in page table entry */
#define CSL_MMU_TABLE_ENTRY_C_BIT_SHIFT   3

/** Bit position of the Cacheable bit in page table entry */
#define CSL_MMU_TABLE_ENTRY_B_BIT_SHIFT   2

/** Mask for the first 18 valid bit of the TTB register */
#define CSL_MMU_TTB_MASK                  0xFFFFC000

/** Right Shift required for generating entry index from virt address*/
#define CSL_MMU_VADDR_L1_SHIFT            18

/** Last two invalid bits of the address of table entry */ 
#define CSL_MMU_ENTRY_INDEX_VALID         0xFFFFFFFC

/** Bit position for the domain entry */
#define CSL_MMU_L1ENTRY_DOMAIN_SHIFT      5

/** This bit should be one */
#define CSL_MMU_SB_ONE                    0x1

/** Position for the 'Should be one bit' */
#define CSL_MMU_TABLE_ENTRY_BIT_NUM_4     4

/** Macro for making coarse page table base address in level1 page table */
#define CSL_MMU_CPT_BASE_ADDR_MASK        0xFFFFFC00

/** Macro for making section base address in level1 page table */
#define CSL_MMU_SECTION_BASE_ADDR_MASK    0xFFF00000

/** Bit position for the Access permission field for section entries */
#define CSL_MMU_L1ENTRY_AP_SHIFT          10

/** Macro for making fine page table base address in level1 page table */
#define CSL_MMU_FPT_BASE_ADDR_MASK        0xFFFFF000

/** Macros for calculating table entry address in CPT */
#define CSL_MMU_CPT_INDEX_MASK            0x000FF000
#define CSL_MMU_VADDR_L2CPT_SHIFT         10

/** Macro for Large page base address entry in level2 table */
#define CSL_MMU_LP_BASE_ADDR_MASK         0xFFFF0000

/** Macro for small page base address entry in level2 table */
#define CSL_MMU_SP_BASE_ADDR_MASK         0xFFFFF000

/** Macro for Tiny page base address entry in level2 table */
#define CSL_MMU_TP_BASE_ADDR_MASK         0xFFFFFC00

/** Bit position of the Access permission field for the first subpage */
#define CSL_MMU_ENTRY_AP0_SHIFT           4
/** Bit position of the Access permission field for the second subpage */
#define CSL_MMU_ENTRY_AP1_SHIFT           6
/** Bit position of the Access permission field for the third subpage */
#define CSL_MMU_ENTRY_AP2_SHIFT           8
/** Bit position of the Access permission field for the fourth subpage */
#define CSL_MMU_ENTRY_AP3_SHIFT           10

/** Macros for calculating table entry address in FPT */
#define CSL_MMU_FPT_INDEX_MASK            0x000FFC00
#define CSL_MMU_VADDR_L2FPT_SHIFT         8
                
#ifdef __cplusplus
}
#endif

#endif  /* _CSL_MMU_H_ */