cslr_ulpd.h

来自「dsp在音频处理中的运用」· C头文件代码 · 共 769 行 · 第 1/3 页
769 行
#define CSL_ULPD_POWER_CTRL_REG_LOW_PWR_REQ_SHIFT (0x00000001u)#define CSL_ULPD_POWER_CTRL_REG_LOW_PWR_REQ_RESETVAL (0x00000000u)#define CSL_ULPD_POWER_CTRL_REG_LOW_PWR_REQ_NOTACTIVE (0x00000000u)#define CSL_ULPD_POWER_CTRL_REG_LOW_PWR_REQ_ACTIVE (0x00000001u)#define CSL_ULPD_POWER_CTRL_REG_LOW_PWR_EN_MASK (0x00000001u)#define CSL_ULPD_POWER_CTRL_REG_LOW_PWR_EN_SHIFT (0x00000000u)#define CSL_ULPD_POWER_CTRL_REG_LOW_PWR_EN_RESETVAL (0x00000000u)#define CSL_ULPD_POWER_CTRL_REG_LOW_PWR_EN_DISABLED (0x00000000u)#define CSL_ULPD_POWER_CTRL_REG_LOW_PWR_EN_ENABLED (0x00000001u)#define CSL_ULPD_POWER_CTRL_REG_RESETVAL (0x00000A18u)/* STATUS_REQ_REG2 */#define CSL_ULPD_STATUS_REQ_REG2_MMC2_DPLL_REQ_MASK (0x00000001u)#define CSL_ULPD_STATUS_REQ_REG2_MMC2_DPLL_REQ_SHIFT (0x00000000u)#define CSL_ULPD_STATUS_REQ_REG2_MMC2_DPLL_REQ_RESETVAL (0x00000000u)#define CSL_ULPD_STATUS_REQ_REG2_MMC2_DPLL_REQ_ACTIVE (0x00000001u)#define CSL_ULPD_STATUS_REQ_REG2_MMC2_DPLL_REQ_INACTIVE (0x00000000u)#define CSL_ULPD_STATUS_REQ_REG2_RESETVAL (0x00000000u)/* SLEEP_STATUS */#define CSL_ULPD_SLEEP_STATUS_BIG_SLEEP_MASK (0x00000002u)#define CSL_ULPD_SLEEP_STATUS_BIG_SLEEP_SHIFT (0x00000001u)#define CSL_ULPD_SLEEP_STATUS_BIG_SLEEP_RESETVAL (0x00000000u)#define CSL_ULPD_SLEEP_STATUS_BIG_SLEEP_AWAKE (0x00000001u)#define CSL_ULPD_SLEEP_STATUS_BIG_SLEEP_NOTAWAKE (0x00000000u)#define CSL_ULPD_SLEEP_STATUS_DEEP_SLEEP_MASK (0x00000001u)#define CSL_ULPD_SLEEP_STATUS_DEEP_SLEEP_SHIFT (0x00000000u)#define CSL_ULPD_SLEEP_STATUS_DEEP_SLEEP_RESETVAL (0x00000000u)#define CSL_ULPD_SLEEP_STATUS_DEEP_SLEEP_AWAKE (0x00000001u)#define CSL_ULPD_SLEEP_STATUS_DEEP_SLEEP_NOTAWAKE (0x00000000u)#define CSL_ULPD_SLEEP_STATUS_RESETVAL   (0x00000000u)/* SETUP_ANALOG_CELL4_REG */#define CSL_ULPD_SETUP_ANALOG_CELL4_REG_SETUP_ANALOG_CELL4_MASK (0x0000FFFFu)#define CSL_ULPD_SETUP_ANALOG_CELL4_REG_SETUP_ANALOG_CELL4_SHIFT (0x00000000u)#define CSL_ULPD_SETUP_ANALOG_CELL4_REG_SETUP_ANALOG_CELL4_RESETVAL (0x00000000u)#define CSL_ULPD_SETUP_ANALOG_CELL4_REG_RESETVAL (0x00000000u)/* SETUP_ANALOG_CELL5_REG */#define CSL_ULPD_SETUP_ANALOG_CELL5_REG_SETUP_ANALOG_CELL5_MASK (0x0000FFFFu)#define CSL_ULPD_SETUP_ANALOG_CELL5_REG_SETUP_ANALOG_CELL5_SHIFT (0x00000000u)#define CSL_ULPD_SETUP_ANALOG_CELL5_REG_SETUP_ANALOG_CELL5_RESETVAL (0x00000000u)#define CSL_ULPD_SETUP_ANALOG_CELL5_REG_RESETVAL (0x00000000u)/* SETUP_ANALOG_CELL6_REG */#define CSL_ULPD_SETUP_ANALOG_CELL6_REG_SETUP_ANALOG_CELL6_MASK (0x0000FFFFu)#define CSL_ULPD_SETUP_ANALOG_CELL6_REG_SETUP_ANALOG_CELL6_SHIFT (0x00000000u)#define CSL_ULPD_SETUP_ANALOG_CELL6_REG_SETUP_ANALOG_CELL6_RESETVAL (0x00000000u)#define CSL_ULPD_SETUP_ANALOG_CELL6_REG_RESETVAL (0x00000000u)/* SOFT_DISABLE_REQ_REG */#define CSL_ULPD_SOFT_DISABLE_REQ_REG_DIS_CLOCK3_DPLL_REQ_MASK (0x00004000u)#define CSL_ULPD_SOFT_DISABLE_REQ_REG_DIS_CLOCK3_DPLL_REQ_SHIFT (0x0000000Eu)#define CSL_ULPD_SOFT_DISABLE_REQ_REG_DIS_CLOCK3_DPLL_REQ_RESETVAL (0x00000000u)#define CSL_ULPD_SOFT_DISABLE_REQ_REG_DIS_CLOCK3_DPLL_REQ_ENABLED (0x00000000u)#define CSL_ULPD_SOFT_DISABLE_REQ_REG_DIS_CLOCK3_DPLL_REQ_DISABLED (0x00000001u)#define CSL_ULPD_SOFT_DISABLE_REQ_REG_DIS_CLOCK2_DPLL_REQ_MASK (0x00002000u)#define CSL_ULPD_SOFT_DISABLE_REQ_REG_DIS_CLOCK2_DPLL_REQ_SHIFT (0x0000000Du)#define CSL_ULPD_SOFT_DISABLE_REQ_REG_DIS_CLOCK2_DPLL_REQ_RESETVAL (0x00000000u)#define CSL_ULPD_SOFT_DISABLE_REQ_REG_DIS_CLOCK2_DPLL_REQ_ENABLED (0x00000000u)#define CSL_ULPD_SOFT_DISABLE_REQ_REG_DIS_CLOCK2_DPLL_REQ_DISABLED (0x00000001u)#define CSL_ULPD_SOFT_DISABLE_REQ_REG_DIS_CLOCK1_DPLL_REQ_MASK (0x00001000u)#define CSL_ULPD_SOFT_DISABLE_REQ_REG_DIS_CLOCK1_DPLL_REQ_SHIFT (0x0000000Cu)#define CSL_ULPD_SOFT_DISABLE_REQ_REG_DIS_CLOCK1_DPLL_REQ_RESETVAL (0x00000000u)#define CSL_ULPD_SOFT_DISABLE_REQ_REG_DIS_CLOCK1_DPLL_REQ_ENABLED (0x00000000u)#define CSL_ULPD_SOFT_DISABLE_REQ_REG_DIS_CLOCK1_DPLL_REQ_DISABLED (0x00000001u)#define CSL_ULPD_SOFT_DISABLE_REQ_REG_DIS_MMC2_DPLL_REQ_MASK (0x00000800u)#define CSL_ULPD_SOFT_DISABLE_REQ_REG_DIS_MMC2_DPLL_REQ_SHIFT (0x0000000Bu)#define CSL_ULPD_SOFT_DISABLE_REQ_REG_DIS_MMC2_DPLL_REQ_RESETVAL (0x00000000u)#define CSL_ULPD_SOFT_DISABLE_REQ_REG_DIS_MMC2_DPLL_REQ_ENABLED (0x00000000u)#define CSL_ULPD_SOFT_DISABLE_REQ_REG_DIS_MMC2_DPLL_REQ_DISABLED (0x00000001u)#define CSL_ULPD_SOFT_DISABLE_REQ_REG_DIS_MMC_DPLL_REQ_MASK (0x00000400u)#define CSL_ULPD_SOFT_DISABLE_REQ_REG_DIS_MMC_DPLL_REQ_SHIFT (0x0000000Au)#define CSL_ULPD_SOFT_DISABLE_REQ_REG_DIS_MMC_DPLL_REQ_RESETVAL (0x00000000u)#define CSL_ULPD_SOFT_DISABLE_REQ_REG_DIS_MMC_DPLL_REQ_ENABLED (0x00000000u)#define CSL_ULPD_SOFT_DISABLE_REQ_REG_DIS_MMC_DPLL_REQ_DISABLED (0x00000001u)#define CSL_ULPD_SOFT_DISABLE_REQ_REG_DIS_UART3_DPLL_REQ_MASK (0x00000200u)#define CSL_ULPD_SOFT_DISABLE_REQ_REG_DIS_UART3_DPLL_REQ_SHIFT (0x00000009u)#define CSL_ULPD_SOFT_DISABLE_REQ_REG_DIS_UART3_DPLL_REQ_RESETVAL (0x00000000u)#define CSL_ULPD_SOFT_DISABLE_REQ_REG_DIS_UART3_DPLL_REQ_ENABLED (0x00000000u)#define CSL_ULPD_SOFT_DISABLE_REQ_REG_DIS_UART3_DPLL_REQ_DISABLED (0x00000001u)#define CSL_ULPD_SOFT_DISABLE_REQ_REG_DIS_UART2_DPLL_REQ_MASK (0x00000100u)#define CSL_ULPD_SOFT_DISABLE_REQ_REG_DIS_UART2_DPLL_REQ_SHIFT (0x00000008u)#define CSL_ULPD_SOFT_DISABLE_REQ_REG_DIS_UART2_DPLL_REQ_RESETVAL (0x00000000u)#define CSL_ULPD_SOFT_DISABLE_REQ_REG_DIS_UART2_DPLL_REQ_ENABLED (0x00000000u)#define CSL_ULPD_SOFT_DISABLE_REQ_REG_DIS_UART2_DPLL_REQ_DISABLED (0x00000001u)#define CSL_ULPD_SOFT_DISABLE_REQ_REG_DIS_UART1_DPLL_REQ_MASK (0x00000080u)#define CSL_ULPD_SOFT_DISABLE_REQ_REG_DIS_UART1_DPLL_REQ_SHIFT (0x00000007u)#define CSL_ULPD_SOFT_DISABLE_REQ_REG_DIS_UART1_DPLL_REQ_RESETVAL (0x00000000u)#define CSL_ULPD_SOFT_DISABLE_REQ_REG_DIS_UART1_DPLL_REQ_ENABLED (0x00000000u)#define CSL_ULPD_SOFT_DISABLE_REQ_REG_DIS_UART1_DPLL_REQ_DISABLED (0x00000001u)#define CSL_ULPD_SOFT_DISABLE_REQ_REG_DIS_USB_HOST_DPLL_REQ_MASK (0x00000040u)#define CSL_ULPD_SOFT_DISABLE_REQ_REG_DIS_USB_HOST_DPLL_REQ_SHIFT (0x00000006u)#define CSL_ULPD_SOFT_DISABLE_REQ_REG_DIS_USB_HOST_DPLL_REQ_RESETVAL (0x00000000u)#define CSL_ULPD_SOFT_DISABLE_REQ_REG_DIS_USB_HOST_DPLL_REQ_ENABLED (0x00000000u)#define CSL_ULPD_SOFT_DISABLE_REQ_REG_DIS_USB_HOST_DPLL_REQ_DISABLED (0x00000001u)#define CSL_ULPD_SOFT_DISABLE_REQ_REG_DIS_CAM_DPLL_MCLK_REQ_MASK (0x00000020u)#define CSL_ULPD_SOFT_DISABLE_REQ_REG_DIS_CAM_DPLL_MCLK_REQ_SHIFT (0x00000005u)#define CSL_ULPD_SOFT_DISABLE_REQ_REG_DIS_CAM_DPLL_MCLK_REQ_RESETVAL (0x00000000u)#define CSL_ULPD_SOFT_DISABLE_REQ_REG_DIS_CAM_DPLL_MCLK_REQ_ENABLED (0x00000000u)#define CSL_ULPD_SOFT_DISABLE_REQ_REG_DIS_CAM_DPLL_MCLK_REQ_DISABLED (0x00000001u)#define CSL_ULPD_SOFT_DISABLE_REQ_REG_DIS_PERIPH_NREQ_MASK (0x00000008u)#define CSL_ULPD_SOFT_DISABLE_REQ_REG_DIS_PERIPH_NREQ_SHIFT (0x00000003u)#define CSL_ULPD_SOFT_DISABLE_REQ_REG_DIS_PERIPH_NREQ_RESETVAL (0x00000000u)#define CSL_ULPD_SOFT_DISABLE_REQ_REG_DIS_PERIPH_NREQ_ENABLED (0x00000000u)#define CSL_ULPD_SOFT_DISABLE_REQ_REG_DIS_PERIPH_NREQ_DISABLED (0x00000001u)#define CSL_ULPD_SOFT_DISABLE_REQ_REG_DIS_SDW_MCLK_REQ_MASK (0x00000002u)#define CSL_ULPD_SOFT_DISABLE_REQ_REG_DIS_SDW_MCLK_REQ_SHIFT (0x00000001u)#define CSL_ULPD_SOFT_DISABLE_REQ_REG_DIS_SDW_MCLK_REQ_RESETVAL (0x00000000u)#define CSL_ULPD_SOFT_DISABLE_REQ_REG_DIS_SDW_MCLK_REQ_ENABLED (0x00000000u)#define CSL_ULPD_SOFT_DISABLE_REQ_REG_DIS_SDW_MCLK_REQ_DISABLED (0x00000001u)#define CSL_ULPD_SOFT_DISABLE_REQ_REG_DIS_COM_MCLK_REQ_MASK (0x00000001u)#define CSL_ULPD_SOFT_DISABLE_REQ_REG_DIS_COM_MCLK_REQ_SHIFT (0x00000000u)#define CSL_ULPD_SOFT_DISABLE_REQ_REG_DIS_COM_MCLK_REQ_RESETVAL (0x00000000u)#define CSL_ULPD_SOFT_DISABLE_REQ_REG_DIS_COM_MCLK_REQ_ENABLED (0x00000000u)#define CSL_ULPD_SOFT_DISABLE_REQ_REG_DIS_COM_MCLK_REQ_DISABLED (0x00000001u)#define CSL_ULPD_SOFT_DISABLE_REQ_REG_RESETVAL (0x00000000u)/* RESET_STATUS */#define CSL_ULPD_RESET_STATUS_32KWD_TIMEOUT_MASK (0x00000008u)#define CSL_ULPD_RESET_STATUS_32KWD_TIMEOUT_SHIFT (0x00000003u)#define CSL_ULPD_RESET_STATUS_32KWD_TIMEOUT_RESETVAL (0x00000000u)#define CSL_ULPD_RESET_STATUS_32KWD_TIMEOUT_OCCURRED (0x00000001u)#define CSL_ULPD_RESET_STATUS_32KWD_TIMEOUT_NOTOCCURRED (0x00000000u)#define CSL_ULPD_RESET_STATUS_SECU_VIOLA_MASK (0x00000004u)#define CSL_ULPD_RESET_STATUS_SECU_VIOLA_SHIFT (0x00000002u)#define CSL_ULPD_RESET_STATUS_SECU_VIOLA_RESETVAL (0x00000000u)#define CSL_ULPD_RESET_STATUS_SECU_VIOLA_OCCURRED (0x00000001u)#define CSL_ULPD_RESET_STATUS_SECU_VIOLA_NOTOCCURRED (0x00000000u)#define CSL_ULPD_RESET_STATUS_SECURE_WDTIMEOUT_MASK (0x00000002u)#define CSL_ULPD_RESET_STATUS_SECURE_WDTIMEOUT_SHIFT (0x00000001u)#define CSL_ULPD_RESET_STATUS_SECURE_WDTIMEOUT_RESETVAL (0x00000000u)#define CSL_ULPD_RESET_STATUS_SECURE_WDTIMEOUT_OCCURRED (0x00000001u)#define CSL_ULPD_RESET_STATUS_SECURE_WDTIMEOUT_NOTOCCURRED (0x00000000u)#define CSL_ULPD_RESET_STATUS_POWER_ON_RESET_MASK (0x00000001u)#define CSL_ULPD_RESET_STATUS_POWER_ON_RESET_SHIFT (0x00000000u)#define CSL_ULPD_RESET_STATUS_POWER_ON_RESET_RESETVAL (0x00000001u)#define CSL_ULPD_RESET_STATUS_POWER_ON_RESET_OCCURRED (0x00000001u)#define CSL_ULPD_RESET_STATUS_POWER_ON_RESET_NOTOCCURRED (0x00000000u)#define CSL_ULPD_RESET_STATUS_RESETVAL   (0x00000001u)/* REVISION_NUMBER */#define CSL_ULPD_REVISION_NUMBER_REVISION_NUMBER_MASK (0x000000FFu)#define CSL_ULPD_REVISION_NUMBER_REVISION_NUMBER_SHIFT (0x00000000u)#define CSL_ULPD_REVISION_NUMBER_REVISION_NUMBER_RESETVAL (0x00000000u)#define CSL_ULPD_REVISION_NUMBER_RESETVAL (0x00000000u)/* SDW_CLK_DIV_CTRL_SEL */#define CSL_ULPD_SDW_CLK_DIV_CTRL_SEL_SDW_RATIO_SEL_MASK (0x000000FCu)#define CSL_ULPD_SDW_CLK_DIV_CTRL_SEL_SDW_RATIO_SEL_SHIFT (0x00000002u)#define CSL_ULPD_SDW_CLK_DIV_CTRL_SEL_SDW_RATIO_SEL_RESETVAL (0x00000000u)#define CSL_ULPD_SDW_CLK_DIV_CTRL_SEL_SDW_ULPD_PLL_CLK_REQ_MASK (0x00000002u)#define CSL_ULPD_SDW_CLK_DIV_CTRL_SEL_SDW_ULPD_PLL_CLK_REQ_SHIFT (0x00000001u)#define CSL_ULPD_SDW_CLK_DIV_CTRL_SEL_SDW_ULPD_PLL_CLK_REQ_RESETVAL (0x00000000u)#define CSL_ULPD_SDW_CLK_DIV_CTRL_SEL_SDW_ULPD_PLL_CLK_REQ_INACTIVE (0x00000000u)#define CSL_ULPD_SDW_CLK_DIV_CTRL_SEL_SDW_ULPD_PLL_CLK_REQ_ACTIVE (0x00000001u)#define CSL_ULPD_SDW_CLK_DIV_CTRL_SEL_SDW_SYSCLK_PLLCLK_SEL_MASK (0x00000001u)#define CSL_ULPD_SDW_CLK_DIV_CTRL_SEL_SDW_SYSCLK_PLLCLK_SEL_SHIFT (0x00000000u)#define CSL_ULPD_SDW_CLK_DIV_CTRL_SEL_SDW_SYSCLK_PLLCLK_SEL_RESETVAL (0x00000001u)#define CSL_ULPD_SDW_CLK_DIV_CTRL_SEL_SDW_SYSCLK_PLLCLK_SEL_SYSTEMCLOCK (0x00000001u)#define CSL_ULPD_SDW_CLK_DIV_CTRL_SEL_SDW_SYSCLK_PLLCLK_SEL_DIVIDED (0x00000000u)#define CSL_ULPD_SDW_CLK_DIV_CTRL_SEL_RESETVAL (0x00000001u)/* COM_CLK_DIV_CTRL_SEL */#define CSL_ULPD_COM_CLK_DIV_CTRL_SEL_COM_RATIO_SEL_MASK (0x000000FCu)#define CSL_ULPD_COM_CLK_DIV_CTRL_SEL_COM_RATIO_SEL_SHIFT (0x00000002u)#define CSL_ULPD_COM_CLK_DIV_CTRL_SEL_COM_RATIO_SEL_RESETVAL (0x00000000u)#define CSL_ULPD_COM_CLK_DIV_CTRL_SEL_COM_ULPD_PLL_CLK_REQ_MASK (0x00000002u)#define CSL_ULPD_COM_CLK_DIV_CTRL_SEL_COM_ULPD_PLL_CLK_REQ_SHIFT (0x00000001u)#define CSL_ULPD_COM_CLK_DIV_CTRL_SEL_COM_ULPD_PLL_CLK_REQ_RESETVAL (0x00000000u)#define CSL_ULPD_COM_CLK_DIV_CTRL_SEL_COM_ULPD_PLL_CLK_REQ_INACTIVE (0x00000000u)#define CSL_ULPD_COM_CLK_DIV_CTRL_SEL_COM_ULPD_PLL_CLK_REQ_ACTIVE (0x00000001u)#define CSL_ULPD_COM_CLK_DIV_CTRL_SEL_COM_SYSCLK_PLLCLK_SEL_MASK (0x00000001u)#define CSL_ULPD_COM_CLK_DIV_CTRL_SEL_COM_SYSCLK_PLLCLK_SEL_SHIFT (0x00000000u)#define CSL_ULPD_COM_CLK_DIV_CTRL_SEL_COM_SYSCLK_PLLCLK_SEL_RESETVAL (0x00000001u)#define CSL_ULPD_COM_CLK_DIV_CTRL_SEL_COM_SYSCLK_PLLCLK_SEL_SYSTEMCLOCK (0x00000001u)#define CSL_ULPD_COM_CLK_DIV_CTRL_SEL_COM_SYSCLK_PLLCLK_SEL_DIVIDED (0x00000000u)#define CSL_ULPD_COM_CLK_DIV_CTRL_SEL_RESETVAL (0x00000001u)/* CAM_CLK_CTRL */#define CSL_ULPD_CAM_CLK_CTRL_SYSTEM_CLK_EN_MASK (0x00000004u)#define CSL_ULPD_CAM_CLK_CTRL_SYSTEM_CLK_EN_SHIFT (0x00000002u)#define CSL_ULPD_CAM_CLK_CTRL_SYSTEM_CLK_EN_RESETVAL (0x00000000u)#define CSL_ULPD_CAM_CLK_CTRL_SYSTEM_CLK_EN_DISABLE (0x00000000u)#define CSL_ULPD_CAM_CLK_CTRL_SYSTEM_CLK_EN_ENABLE (0x00000001u)#define CSL_ULPD_CAM_CLK_CTRL_CAM_CLK_DIV_MASK (0x00000002u)#define CSL_ULPD_CAM_CLK_CTRL_CAM_CLK_DIV_SHIFT (0x00000001u)#define CSL_ULPD_CAM_CLK_CTRL_CAM_CLK_DIV_RESETVAL (0x00000000u)#define CSL_ULPD_CAM_CLK_CTRL_CAM_CLK_DIV_CLKBY1 (0x00000000u)#define CSL_ULPD_CAM_CLK_CTRL_CAM_CLK_DIV_CLKBY2 (0x00000001u)#define CSL_ULPD_CAM_CLK_CTRL_CAM_CLOCK_EN_MASK (0x00000001u)#define CSL_ULPD_CAM_CLK_CTRL_CAM_CLOCK_EN_SHIFT (0x00000000u)#define CSL_ULPD_CAM_CLK_CTRL_CAM_CLOCK_EN_RESETVAL (0x00000000u)#define CSL_ULPD_CAM_CLK_CTRL_CAM_CLOCK_EN_ENABLE (0x00000001u)#define CSL_ULPD_CAM_CLK_CTRL_CAM_CLOCK_EN_DISABLE (0x00000000u)#define CSL_ULPD_CAM_CLK_CTRL_RESETVAL   (0x00000000u)/* SOFT_REQ_REG2 */#define CSL_ULPD_SOFT_REQ_REG2_SOFT_CLOCK3_DPLL_REQ_MASK (0x00000001u)#define CSL_ULPD_SOFT_REQ_REG2_SOFT_CLOCK3_DPLL_REQ_SHIFT (0x00000000u)#define CSL_ULPD_SOFT_REQ_REG2_SOFT_CLOCK3_DPLL_REQ_RESETVAL (0x00000000u)#define CSL_ULPD_SOFT_REQ_REG2_SOFT_CLOCK3_DPLL_REQ_INACTIVE (0x00000000u)#define CSL_ULPD_SOFT_REQ_REG2_SOFT_CLOCK3_DPLL_REQ_ACTIVE (0x00000001u)#define CSL_ULPD_SOFT_REQ_REG2_RESETVAL (0x00000000u)#endif
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