cslr_ulpd.h

来自「dsp在音频处理中的运用」· C头文件代码 · 共 769 行 · 第 1/3 页
769 行
#define CSL_ULPD_SOFT_REQ_REG_SOFT_UART1_DPLL_REQ_ACTIVE (0x00000001u)#define CSL_ULPD_SOFT_REQ_REG_SOFT_UART1_DPLL_REQ_INACTIVE (0x00000000u)#define CSL_ULPD_SOFT_REQ_REG_SOFT_USB_OTG_DPLL_REQ_MASK (0x00000100u)#define CSL_ULPD_SOFT_REQ_REG_SOFT_USB_OTG_DPLL_REQ_SHIFT (0x00000008u)#define CSL_ULPD_SOFT_REQ_REG_SOFT_USB_OTG_DPLL_REQ_RESETVAL (0x00000000u)#define CSL_ULPD_SOFT_REQ_REG_SOFT_USB_OTG_DPLL_REQ_ACTIVE (0x00000001u)#define CSL_ULPD_SOFT_REQ_REG_SOFT_USB_OTG_DPLL_REQ_INACTIVE (0x00000000u)#define CSL_ULPD_SOFT_REQ_REG_SOFT_CAM_DPLL_MCKO_REQ_MASK (0x00000080u)#define CSL_ULPD_SOFT_REQ_REG_SOFT_CAM_DPLL_MCKO_REQ_SHIFT (0x00000007u)#define CSL_ULPD_SOFT_REQ_REG_SOFT_CAM_DPLL_MCKO_REQ_RESETVAL (0x00000000u)#define CSL_ULPD_SOFT_REQ_REG_SOFT_CAM_DPLL_MCKO_REQ_ACTIVE (0x00000001u)#define CSL_ULPD_SOFT_REQ_REG_SOFT_CAM_DPLL_MCKO_REQ_INACTIVE (0x00000000u)#define CSL_ULPD_SOFT_REQ_REG_SOFT_COM_MCKO_REQ_MASK (0x00000040u)#define CSL_ULPD_SOFT_REQ_REG_SOFT_COM_MCKO_REQ_SHIFT (0x00000006u)#define CSL_ULPD_SOFT_REQ_REG_SOFT_COM_MCKO_REQ_RESETVAL (0x00000000u)#define CSL_ULPD_SOFT_REQ_REG_SOFT_COM_MCKO_REQ_ACTIVE (0x00000001u)#define CSL_ULPD_SOFT_REQ_REG_SOFT_COM_MCKO_REQ_INACTIVE (0x00000000u)#define CSL_ULPD_SOFT_REQ_REG_SOFT_PERIPH_NREQ_MASK (0x00000020u)#define CSL_ULPD_SOFT_REQ_REG_SOFT_PERIPH_NREQ_SHIFT (0x00000005u)#define CSL_ULPD_SOFT_REQ_REG_SOFT_PERIPH_NREQ_RESETVAL (0x00000000u)#define CSL_ULPD_SOFT_REQ_REG_SOFT_PERIPH_NREQ_ACTIVE (0x00000001u)#define CSL_ULPD_SOFT_REQ_REG_SOFT_PERIPH_NREQ_INACTIVE (0x00000000u)#define CSL_ULPD_SOFT_REQ_REG_USB_REQ_EN_MASK (0x00000010u)#define CSL_ULPD_SOFT_REQ_REG_USB_REQ_EN_SHIFT (0x00000004u)#define CSL_ULPD_SOFT_REQ_REG_USB_REQ_EN_RESETVAL (0x00000001u)#define CSL_ULPD_SOFT_REQ_REG_USB_REQ_EN_ENABLE (0x00000001u)#define CSL_ULPD_SOFT_REQ_REG_USB_REQ_EN_DISABLE (0x00000000u)#define CSL_ULPD_SOFT_REQ_REG_SOFT_USB_REQ_MASK (0x00000008u)#define CSL_ULPD_SOFT_REQ_REG_SOFT_USB_REQ_SHIFT (0x00000003u)#define CSL_ULPD_SOFT_REQ_REG_SOFT_USB_REQ_RESETVAL (0x00000000u)#define CSL_ULPD_SOFT_REQ_REG_SOFT_USB_REQ_ACTIVE (0x00000001u)#define CSL_ULPD_SOFT_REQ_REG_SOFT_USB_REQ_INACTIVE (0x00000000u)#define CSL_ULPD_SOFT_REQ_REG_SOFT_SDW_REQ_MASK (0x00000004u)#define CSL_ULPD_SOFT_REQ_REG_SOFT_SDW_REQ_SHIFT (0x00000002u)#define CSL_ULPD_SOFT_REQ_REG_SOFT_SDW_REQ_RESETVAL (0x00000000u)#define CSL_ULPD_SOFT_REQ_REG_SOFT_SDW_REQ_ACTIVE (0x00000001u)#define CSL_ULPD_SOFT_REQ_REG_SOFT_SDW_REQ_INACTIVE (0x00000000u)#define CSL_ULPD_SOFT_REQ_REG_SOFT_COM_REQ_MASK (0x00000002u)#define CSL_ULPD_SOFT_REQ_REG_SOFT_COM_REQ_SHIFT (0x00000001u)#define CSL_ULPD_SOFT_REQ_REG_SOFT_COM_REQ_RESETVAL (0x00000000u)#define CSL_ULPD_SOFT_REQ_REG_SOFT_COM_REQ_ACTIVE (0x00000001u)#define CSL_ULPD_SOFT_REQ_REG_SOFT_COM_REQ_INACTIVE (0x00000000u)#define CSL_ULPD_SOFT_REQ_REG_SOFT_DPLL_REQ_MASK (0x00000001u)#define CSL_ULPD_SOFT_REQ_REG_SOFT_DPLL_REQ_SHIFT (0x00000000u)#define CSL_ULPD_SOFT_REQ_REG_SOFT_DPLL_REQ_RESETVAL (0x00000000u)#define CSL_ULPD_SOFT_REQ_REG_SOFT_DPLL_REQ_ACTIVE (0x00000001u)#define CSL_ULPD_SOFT_REQ_REG_SOFT_DPLL_REQ_INACTIVE (0x00000000u)#define CSL_ULPD_SOFT_REQ_REG_RESETVAL   (0x00000010u)/* COUNTER_32_FIQ_REG */#define CSL_ULPD_COUNTER_32_FIQ_REG_COUNTER_32_FIQ_MASK (0x000000FFu)#define CSL_ULPD_COUNTER_32_FIQ_REG_COUNTER_32_FIQ_SHIFT (0x00000000u)#define CSL_ULPD_COUNTER_32_FIQ_REG_COUNTER_32_FIQ_RESETVAL (0x00000000u)#define CSL_ULPD_COUNTER_32_FIQ_REG_RESETVAL (0x00000000u)/* STATUS_REQ_REG */#define CSL_ULPD_STATUS_REQ_REG_CLOCK3_DPLL_REQ_MASK (0x00008000u)#define CSL_ULPD_STATUS_REQ_REG_CLOCK3_DPLL_REQ_SHIFT (0x0000000Fu)#define CSL_ULPD_STATUS_REQ_REG_CLOCK3_DPLL_REQ_RESETVAL (0x00000000u)#define CSL_ULPD_STATUS_REQ_REG_CLOCK3_DPLL_REQ_ACTIVE (0x00000001u)#define CSL_ULPD_STATUS_REQ_REG_CLOCK3_DPLL_REQ_INACTIVE (0x00000000u)#define CSL_ULPD_STATUS_REQ_REG_CLOCK2_DPLL_REQ_MASK (0x00004000u)#define CSL_ULPD_STATUS_REQ_REG_CLOCK2_DPLL_REQ_SHIFT (0x0000000Eu)#define CSL_ULPD_STATUS_REQ_REG_CLOCK2_DPLL_REQ_RESETVAL (0x00000000u)#define CSL_ULPD_STATUS_REQ_REG_CLOCK2_DPLL_REQ_ACTIVE (0x00000001u)#define CSL_ULPD_STATUS_REQ_REG_CLOCK2_DPLL_REQ_INACTIVE (0x00000000u)#define CSL_ULPD_STATUS_REQ_REG_CLOCK1_DPLL_REQ_MASK (0x00002000u)#define CSL_ULPD_STATUS_REQ_REG_CLOCK1_DPLL_REQ_SHIFT (0x0000000Du)#define CSL_ULPD_STATUS_REQ_REG_CLOCK1_DPLL_REQ_RESETVAL (0x00000000u)#define CSL_ULPD_STATUS_REQ_REG_CLOCK1_DPLL_REQ_ACTIVE (0x00000001u)#define CSL_ULPD_STATUS_REQ_REG_CLOCK1_DPLL_REQ_INACTIVE (0x00000000u)#define CSL_ULPD_STATUS_REQ_REG_MMC_DPLL_REQ_MASK (0x00001000u)#define CSL_ULPD_STATUS_REQ_REG_MMC_DPLL_REQ_SHIFT (0x0000000Cu)#define CSL_ULPD_STATUS_REQ_REG_MMC_DPLL_REQ_RESETVAL (0x00000000u)#define CSL_ULPD_STATUS_REQ_REG_MMC_DPLL_REQ_ACTIVE (0x00000001u)#define CSL_ULPD_STATUS_REQ_REG_MMC_DPLL_REQ_INACTIVE (0x00000000u)#define CSL_ULPD_STATUS_REQ_REG_UART3_DPLL_REQ_MASK (0x00000800u)#define CSL_ULPD_STATUS_REQ_REG_UART3_DPLL_REQ_SHIFT (0x0000000Bu)#define CSL_ULPD_STATUS_REQ_REG_UART3_DPLL_REQ_RESETVAL (0x00000000u)#define CSL_ULPD_STATUS_REQ_REG_UART3_DPLL_REQ_ACTIVE (0x00000001u)#define CSL_ULPD_STATUS_REQ_REG_UART3_DPLL_REQ_INACTIVE (0x00000000u)#define CSL_ULPD_STATUS_REQ_REG_UART2_DPLL_REQ_MASK (0x00000400u)#define CSL_ULPD_STATUS_REQ_REG_UART2_DPLL_REQ_SHIFT (0x0000000Au)#define CSL_ULPD_STATUS_REQ_REG_UART2_DPLL_REQ_RESETVAL (0x00000000u)#define CSL_ULPD_STATUS_REQ_REG_UART2_DPLL_REQ_ACTIVE (0x00000001u)#define CSL_ULPD_STATUS_REQ_REG_UART2_DPLL_REQ_INACTIVE (0x00000000u)#define CSL_ULPD_STATUS_REQ_REG_UART1_DPLL_REQ_MASK (0x00000200u)#define CSL_ULPD_STATUS_REQ_REG_UART1_DPLL_REQ_SHIFT (0x00000009u)#define CSL_ULPD_STATUS_REQ_REG_UART1_DPLL_REQ_RESETVAL (0x00000000u)#define CSL_ULPD_STATUS_REQ_REG_UART1_DPLL_REQ_ACTIVE (0x00000001u)#define CSL_ULPD_STATUS_REQ_REG_UART1_DPLL_REQ_INACTIVE (0x00000000u)#define CSL_ULPD_STATUS_REQ_REG_USB_HOST_DPLL_REQ_MASK (0x00000100u)#define CSL_ULPD_STATUS_REQ_REG_USB_HOST_DPLL_REQ_SHIFT (0x00000008u)#define CSL_ULPD_STATUS_REQ_REG_USB_HOST_DPLL_REQ_RESETVAL (0x00000000u)#define CSL_ULPD_STATUS_REQ_REG_USB_HOST_DPLL_REQ_ACTIVE (0x00000001u)#define CSL_ULPD_STATUS_REQ_REG_USB_HOST_DPLL_REQ_INACTIVE (0x00000000u)#define CSL_ULPD_STATUS_REQ_REG_CAM_DPLL_MCLK_REQ_MASK (0x00000080u)#define CSL_ULPD_STATUS_REQ_REG_CAM_DPLL_MCLK_REQ_SHIFT (0x00000007u)#define CSL_ULPD_STATUS_REQ_REG_CAM_DPLL_MCLK_REQ_RESETVAL (0x00000000u)#define CSL_ULPD_STATUS_REQ_REG_CAM_DPLL_MCLK_REQ_ACTIVE (0x00000001u)#define CSL_ULPD_STATUS_REQ_REG_CAM_DPLL_MCLK_REQ_INACTIVE (0x00000000u)#define CSL_ULPD_STATUS_REQ_REG_USB_DPLL_MCLK_REQ_MASK (0x00000040u)#define CSL_ULPD_STATUS_REQ_REG_USB_DPLL_MCLK_REQ_SHIFT (0x00000006u)#define CSL_ULPD_STATUS_REQ_REG_USB_DPLL_MCLK_REQ_RESETVAL (0x00000000u)#define CSL_ULPD_STATUS_REQ_REG_USB_DPLL_MCLK_REQ_ACTIVE (0x00000001u)#define CSL_ULPD_STATUS_REQ_REG_USB_DPLL_MCLK_REQ_INACTIVE (0x00000000u)#define CSL_ULPD_STATUS_REQ_REG_USB_MCLK_REQ_MASK (0x00000020u)#define CSL_ULPD_STATUS_REQ_REG_USB_MCLK_REQ_SHIFT (0x00000005u)#define CSL_ULPD_STATUS_REQ_REG_USB_MCLK_REQ_RESETVAL (0x00000000u)#define CSL_ULPD_STATUS_REQ_REG_USB_MCLK_REQ_ACTIVE (0x00000001u)#define CSL_ULPD_STATUS_REQ_REG_USB_MCLK_REQ_INACTIVE (0x00000000u)#define CSL_ULPD_STATUS_REQ_REG_SDW_MCLK_REQ_MASK (0x00000010u)#define CSL_ULPD_STATUS_REQ_REG_SDW_MCLK_REQ_SHIFT (0x00000004u)#define CSL_ULPD_STATUS_REQ_REG_SDW_MCLK_REQ_RESETVAL (0x00000000u)#define CSL_ULPD_STATUS_REQ_REG_SDW_MCLK_REQ_ACTIVE (0x00000001u)#define CSL_ULPD_STATUS_REQ_REG_SDW_MCLK_REQ_INACTIVE (0x00000000u)#define CSL_ULPD_STATUS_REQ_REG_COM_MCLK_REQ_MASK (0x00000008u)#define CSL_ULPD_STATUS_REQ_REG_COM_MCLK_REQ_SHIFT (0x00000003u)#define CSL_ULPD_STATUS_REQ_REG_COM_MCLK_REQ_RESETVAL (0x00000000u)#define CSL_ULPD_STATUS_REQ_REG_COM_MCLK_REQ_ACTIVE (0x00000001u)#define CSL_ULPD_STATUS_REQ_REG_COM_MCLK_REQ_INACTIVE (0x00000000u)#define CSL_ULPD_STATUS_REQ_REG_PERIPH_NREQ_MASK (0x00000004u)#define CSL_ULPD_STATUS_REQ_REG_PERIPH_NREQ_SHIFT (0x00000002u)#define CSL_ULPD_STATUS_REQ_REG_PERIPH_NREQ_RESETVAL (0x00000000u)#define CSL_ULPD_STATUS_REQ_REG_PERIPH_NREQ_ACTIVE (0x00000001u)#define CSL_ULPD_STATUS_REQ_REG_PERIPH_NREQ_INACTIVE (0x00000000u)#define CSL_ULPD_STATUS_REQ_REG_WAKEUP_NREQ_MASK (0x00000002u)#define CSL_ULPD_STATUS_REQ_REG_WAKEUP_NREQ_SHIFT (0x00000001u)#define CSL_ULPD_STATUS_REQ_REG_WAKEUP_NREQ_RESETVAL (0x00000000u)#define CSL_ULPD_STATUS_REQ_REG_WAKEUP_NREQ_ACTIVE (0x00000001u)#define CSL_ULPD_STATUS_REQ_REG_WAKEUP_NREQ_INACTIVE (0x00000000u)#define CSL_ULPD_STATUS_REQ_REG_CHIP_IDLE_MASK (0x00000001u)#define CSL_ULPD_STATUS_REQ_REG_CHIP_IDLE_SHIFT (0x00000000u)#define CSL_ULPD_STATUS_REQ_REG_CHIP_IDLE_RESETVAL (0x00000000u)#define CSL_ULPD_STATUS_REQ_REG_CHIP_IDLE_ACTIVE (0x00000001u)#define CSL_ULPD_STATUS_REQ_REG_CHIP_IDLE_INACTIVE (0x00000000u)#define CSL_ULPD_STATUS_REQ_REG_RESETVAL (0x00000000u)/* PLL_DIV_REG */#define CSL_ULPD_PLL_DIV_REG_PLL_DIV_FACTOR_MASK (0x0000FFFFu)#define CSL_ULPD_PLL_DIV_REG_PLL_DIV_FACTOR_SHIFT (0x00000000u)#define CSL_ULPD_PLL_DIV_REG_PLL_DIV_FACTOR_RESETVAL (0x00000000u)#define CSL_ULPD_PLL_DIV_REG_RESETVAL    (0x00000000u)/* ULPD_PLL_CTRL_STATUS */#define CSL_ULPD_ULPD_PLL_CTRL_STATUS_LOCK_STATUS_MASK (0x00008000u)#define CSL_ULPD_ULPD_PLL_CTRL_STATUS_LOCK_STATUS_SHIFT (0x0000000Fu)#define CSL_ULPD_ULPD_PLL_CTRL_STATUS_LOCK_STATUS_RESETVAL (0x00000000u)#define CSL_ULPD_ULPD_PLL_CTRL_STATUS_LOCK_STATUS_LOCKED (0x00000001u)#define CSL_ULPD_ULPD_PLL_CTRL_STATUS_LOCK_STATUS_UNLOCKED (0x00000000u)#define CSL_ULPD_ULPD_PLL_CTRL_STATUS_PLL_CTRL_RES_MASK (0x00007FF8u)#define CSL_ULPD_ULPD_PLL_CTRL_STATUS_PLL_CTRL_RES_SHIFT (0x00000003u)#define CSL_ULPD_ULPD_PLL_CTRL_STATUS_PLL_CTRL_RES_RESETVAL (0x00000000u)#define CSL_ULPD_ULPD_PLL_CTRL_STATUS_PLL_CONTROL_MASK (0x00000007u)#define CSL_ULPD_ULPD_PLL_CTRL_STATUS_PLL_CONTROL_SHIFT (0x00000000u)#define CSL_ULPD_ULPD_PLL_CTRL_STATUS_PLL_CONTROL_RESETVAL (0x00000003u)#define CSL_ULPD_ULPD_PLL_CTRL_STATUS_PLL_CONTROL_NINETEEN (0x00000000u)#define CSL_ULPD_ULPD_PLL_CTRL_STATUS_PLL_CONTROL_THIRTEEN (0x00000002u)#define CSL_ULPD_ULPD_PLL_CTRL_STATUS_PLL_CONTROL_TWELVE (0x00000003u)#define CSL_ULPD_ULPD_PLL_CTRL_STATUS_RESETVAL (0x00000003u)/* POWER_CTRL_REG */#define CSL_ULPD_POWER_CTRL_REG_ISOLATION_CONTROL_MASK (0x00001000u)#define CSL_ULPD_POWER_CTRL_REG_ISOLATION_CONTROL_SHIFT (0x0000000Cu)#define CSL_ULPD_POWER_CTRL_REG_ISOLATION_CONTROL_RESETVAL (0x00000000u)#define CSL_ULPD_POWER_CTRL_REG_ISOLATION_CONTROL_ACTIVE (0x00000001u)#define CSL_ULPD_POWER_CTRL_REG_ISOLATION_CONTROL_INACTIVE (0x00000000u)#define CSL_ULPD_POWER_CTRL_REG_MIN_MAX_REG_MASK (0x00000800u)#define CSL_ULPD_POWER_CTRL_REG_MIN_MAX_REG_SHIFT (0x0000000Bu)#define CSL_ULPD_POWER_CTRL_REG_MIN_MAX_REG_RESETVAL (0x00000001u)#define CSL_ULPD_POWER_CTRL_REG_MIN_MAX_REG_MINIMAL (0x00000001u)#define CSL_ULPD_POWER_CTRL_REG_MIN_MAX_REG_NOMINAL (0x00000000u)#define CSL_ULPD_POWER_CTRL_REG_DVS_ENABLE_MASK (0x00000400u)#define CSL_ULPD_POWER_CTRL_REG_DVS_ENABLE_SHIFT (0x0000000Au)#define CSL_ULPD_POWER_CTRL_REG_DVS_ENABLE_RESETVAL (0x00000000u)#define CSL_ULPD_POWER_CTRL_REG_DVS_ENABLE_DISABLED (0x00000000u)#define CSL_ULPD_POWER_CTRL_REG_DVS_ENABLE_ENABLED (0x00000001u)#define CSL_ULPD_POWER_CTRL_REG_OSC_STOP_EN_MASK (0x00000200u)#define CSL_ULPD_POWER_CTRL_REG_OSC_STOP_EN_SHIFT (0x00000009u)#define CSL_ULPD_POWER_CTRL_REG_OSC_STOP_EN_RESETVAL (0x00000001u)#define CSL_ULPD_POWER_CTRL_REG_OSC_STOP_EN_STOPPED (0x00000001u)#define CSL_ULPD_POWER_CTRL_REG_OSC_STOP_EN_NOTSTOPPED (0x00000000u)#define CSL_ULPD_POWER_CTRL_REG_SOFT_LDO_SLEEP_MASK (0x00000100u)#define CSL_ULPD_POWER_CTRL_REG_SOFT_LDO_SLEEP_SHIFT (0x00000008u)#define CSL_ULPD_POWER_CTRL_REG_SOFT_LDO_SLEEP_RESETVAL (0x00000000u)#define CSL_ULPD_POWER_CTRL_REG_SOFT_LDO_SLEEP_SLEEPTOACTIVE (0x00000001u)#define CSL_ULPD_POWER_CTRL_REG_SOFT_LDO_SLEEP_NOSLEEP (0x00000000u)#define CSL_ULPD_POWER_CTRL_REG_LDO_CTRL_EN_MASK (0x00000080u)#define CSL_ULPD_POWER_CTRL_REG_LDO_CTRL_EN_SHIFT (0x00000007u)#define CSL_ULPD_POWER_CTRL_REG_LDO_CTRL_EN_RESETVAL (0x00000000u)#define CSL_ULPD_POWER_CTRL_REG_LDO_CTRL_EN_SOFTLDOSLEEP (0x00000000u)#define CSL_ULPD_POWER_CTRL_REG_LDO_CTRL_EN_DEEPSLEEP (0x00000001u)#define CSL_ULPD_POWER_CTRL_REG_LDO_STEADY_MASK (0x00000040u)#define CSL_ULPD_POWER_CTRL_REG_LDO_STEADY_SHIFT (0x00000006u)#define CSL_ULPD_POWER_CTRL_REG_LDO_STEADY_RESETVAL (0x00000000u)#define CSL_ULPD_POWER_CTRL_REG_LDO_STEADY_UNSTABLE (0x00000000u)#define CSL_ULPD_POWER_CTRL_REG_LDO_STEADY_STABLE (0x00000001u)#define CSL_ULPD_POWER_CTRL_REG_DEEP_SLEEP_TRANSITION_EN_MASK (0x00000010u)#define CSL_ULPD_POWER_CTRL_REG_DEEP_SLEEP_TRANSITION_EN_SHIFT (0x00000004u)#define CSL_ULPD_POWER_CTRL_REG_DEEP_SLEEP_TRANSITION_EN_RESETVAL (0x00000001u)#define CSL_ULPD_POWER_CTRL_REG_DEEP_SLEEP_TRANSITION_EN_ALLOWED (0x00000001u)#define CSL_ULPD_POWER_CTRL_REG_DEEP_SLEEP_TRANSITION_EN_FORBIDDEN (0x00000000u)#define CSL_ULPD_POWER_CTRL_REG_SW_NSHUTDOWN_MASK (0x00000008u)#define CSL_ULPD_POWER_CTRL_REG_SW_NSHUTDOWN_SHIFT (0x00000003u)#define CSL_ULPD_POWER_CTRL_REG_SW_NSHUTDOWN_RESETVAL (0x00000001u)#define CSL_ULPD_POWER_CTRL_REG_SW_NSHUTDOWN_LOW (0x00000000u)#define CSL_ULPD_POWER_CTRL_REG_SW_NSHUTDOWN_NOTLOW (0x00000001u)#define CSL_ULPD_POWER_CTRL_REG_SW_NSHUTDOWN_RST_MASK (0x00000004u)#define CSL_ULPD_POWER_CTRL_REG_SW_NSHUTDOWN_RST_SHIFT (0x00000002u)#define CSL_ULPD_POWER_CTRL_REG_SW_NSHUTDOWN_RST_RESETVAL (0x00000000u)#define CSL_ULPD_POWER_CTRL_REG_LOW_PWR_REQ_MASK (0x00000002u)
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