cslr_ulpd.h

来自「dsp在音频处理中的运用」· C头文件 代码 · 共 769 行 · 第 1/3 页

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#ifndef _CSLR_ULPD_001_H_#define _CSLR_ULPD_001_H_#include <cslr.h>#include <tistdtypes.h>/**************************************************************************\* Register Overlay Structure\**************************************************************************/typedef struct  {    volatile Uint16 COUNTER_32_LSB_REG;    const char RSVD0[2];    volatile Uint16 COUNTER_32_MSB_REG;    const char RSVD1[2];    volatile Uint16 COUNTER_HIGH_FREQ_LSB_REG;    const char RSVD2[2];    volatile Uint16 COUNTER_HIGH_FREQ_MSB_REG;    const char RSVD3[2];    volatile Uint16 GAUGING_CTRL_REG;    const char RSVD4[2];    volatile Uint16 IT_STATUS_REG;    const char RSVD5[14];    volatile Uint16 SETUP_ANALOG_CELL3_REG;    const char RSVD6[2];    volatile Uint16 SETUP_ANALOG_CELL2_REG;    const char RSVD7[2];    volatile Uint16 SETUP_ANALOG_CELL1_REG;    const char RSVD8[2];    volatile Uint16 CLOCK_CTRL_REG;    const char RSVD9[2];    volatile Uint16 SOFT_REQ_REG;    const char RSVD10[2];    volatile Uint16 COUNTER_32_FIQ_REG;    const char RSVD11[6];    volatile Uint16 STATUS_REQ_REG;    const char RSVD12[2];    volatile Uint16 PLL_DIV_REG;    const char RSVD13[6];    volatile Uint16 ULPD_PLL_CTRL_STATUS;    const char RSVD14[2];    volatile Uint16 POWER_CTRL_REG;    const char RSVD15[2];    volatile Uint16 STATUS_REQ_REG2;    const char RSVD16[2];    volatile Uint16 SLEEP_STATUS;    const char RSVD17[2];    volatile Uint16 SETUP_ANALOG_CELL4_REG;    const char RSVD18[2];    volatile Uint16 SETUP_ANALOG_CELL5_REG;    const char RSVD19[2];    volatile Uint16 SETUP_ANALOG_CELL6_REG;    const char RSVD20[2];    volatile Uint16 SOFT_DISABLE_REQ_REG;    const char RSVD21[2];    volatile Uint16 RESET_STATUS;    const char RSVD22[2];    volatile Uint16 REVISION_NUMBER;    const char RSVD23[2];    volatile Uint16 SDW_CLK_DIV_CTRL_SEL;    const char RSVD24[2];    volatile Uint16 COM_CLK_DIV_CTRL_SEL;    const char RSVD25[2];    volatile Uint16 CAM_CLK_CTRL;    const char RSVD26[2];    volatile Uint16 SOFT_REQ_REG2;} CSL_UlpdRegs;/**************************************************************************\* Overlay structure typedef definition\**************************************************************************/typedef volatile CSL_UlpdRegs  *CSL_UlpdRegsOvly;/**************************************************************************\* Field Definition Macros\**************************************************************************//* COUNTER_32_LSB_REG */#define CSL_ULPD_COUNTER_32_LSB_REG_COUNTER_SLEEP_CLK_LSB_MASK (0x0000FFFFu)#define CSL_ULPD_COUNTER_32_LSB_REG_COUNTER_SLEEP_CLK_LSB_SHIFT (0x00000000u)#define CSL_ULPD_COUNTER_32_LSB_REG_COUNTER_SLEEP_CLK_LSB_RESETVAL (0x00000001u)#define CSL_ULPD_COUNTER_32_LSB_REG_RESETVAL (0x00000001u)/* COUNTER_32_MSB_REG */#define CSL_ULPD_COUNTER_32_MSB_REG_COUNTER_32_MSB_MASK (0x0000000Fu)#define CSL_ULPD_COUNTER_32_MSB_REG_COUNTER_32_MSB_SHIFT (0x00000000u)#define CSL_ULPD_COUNTER_32_MSB_REG_COUNTER_32_MSB_RESETVAL (0x00000000u)#define CSL_ULPD_COUNTER_32_MSB_REG_RESETVAL (0x00000000u)/* COUNTER_HIGH_FREQ_LSB_REG */#define CSL_ULPD_COUNTER_HIGH_FREQ_LSB_REG_COUNTER_HIGH_FREQ_LSB_MASK (0x0000FFFFu)#define CSL_ULPD_COUNTER_HIGH_FREQ_LSB_REG_COUNTER_HIGH_FREQ_LSB_SHIFT (0x00000000u)#define CSL_ULPD_COUNTER_HIGH_FREQ_LSB_REG_COUNTER_HIGH_FREQ_LSB_RESETVAL (0x00000001u)#define CSL_ULPD_COUNTER_HIGH_FREQ_LSB_REG_RESETVAL (0x00000001u)/* COUNTER_HIGH_FREQ_MSB_REG */#define CSL_ULPD_COUNTER_HIGH_FREQ_MSB_REG_COUNTER_HIGH_FREQ_MSB_MASK (0x0000003Fu)#define CSL_ULPD_COUNTER_HIGH_FREQ_MSB_REG_COUNTER_HIGH_FREQ_MSB_SHIFT (0x00000000u)#define CSL_ULPD_COUNTER_HIGH_FREQ_MSB_REG_COUNTER_HIGH_FREQ_MSB_RESETVAL (0x00000000u)#define CSL_ULPD_COUNTER_HIGH_FREQ_MSB_REG_RESETVAL (0x00000000u)/* GAUGING_CTRL_REG */#define CSL_ULPD_GAUGING_CTRL_REG_SELECT_HI_FREQ_CLOCK_MASK (0x00000002u)#define CSL_ULPD_GAUGING_CTRL_REG_SELECT_HI_FREQ_CLOCK_SHIFT (0x00000001u)#define CSL_ULPD_GAUGING_CTRL_REG_SELECT_HI_FREQ_CLOCK_RESETVAL (0x00000000u)#define CSL_ULPD_GAUGING_CTRL_REG_SELECT_HI_FREQ_CLOCK_AUXILIARY (0x00000001u)#define CSL_ULPD_GAUGING_CTRL_REG_SELECT_HI_FREQ_CLOCK_TWELVE (0x00000000u)#define CSL_ULPD_GAUGING_CTRL_REG_GAUGING_EN_MASK (0x00000001u)#define CSL_ULPD_GAUGING_CTRL_REG_GAUGING_EN_SHIFT (0x00000000u)#define CSL_ULPD_GAUGING_CTRL_REG_GAUGING_EN_RESETVAL (0x00000000u)#define CSL_ULPD_GAUGING_CTRL_REG_GAUGING_EN_RUNNING (0x00000001u)#define CSL_ULPD_GAUGING_CTRL_REG_GAUGING_EN_STOPPED (0x00000000u)#define CSL_ULPD_GAUGING_CTRL_REG_RESETVAL (0x00000000u)/* IT_STATUS_REG */#define CSL_ULPD_IT_STATUS_REG_IT_WAKEUP_USB_MASK (0x00000008u)#define CSL_ULPD_IT_STATUS_REG_IT_WAKEUP_USB_SHIFT (0x00000003u)#define CSL_ULPD_IT_STATUS_REG_IT_WAKEUP_USB_RESETVAL (0x00000000u)#define CSL_ULPD_IT_STATUS_REG_OVERFLOW_32_MASK (0x00000004u)#define CSL_ULPD_IT_STATUS_REG_OVERFLOW_32_SHIFT (0x00000002u)#define CSL_ULPD_IT_STATUS_REG_OVERFLOW_32_RESETVAL (0x00000000u)#define CSL_ULPD_IT_STATUS_REG_OVERFLOW_HI_FREQ_MASK (0x00000002u)#define CSL_ULPD_IT_STATUS_REG_OVERFLOW_HI_FREQ_SHIFT (0x00000001u)#define CSL_ULPD_IT_STATUS_REG_OVERFLOW_HI_FREQ_RESETVAL (0x00000000u)#define CSL_ULPD_IT_STATUS_REG_IT_GAUGING_MASK (0x00000001u)#define CSL_ULPD_IT_STATUS_REG_IT_GAUGING_SHIFT (0x00000000u)#define CSL_ULPD_IT_STATUS_REG_IT_GAUGING_RESETVAL (0x00000000u)#define CSL_ULPD_IT_STATUS_REG_RESETVAL  (0x00000000u)/* SETUP_ANALOG_CELL3_REG */#define CSL_ULPD_SETUP_ANALOG_CELL3_REG_SETUP_ANALOG_CELL3_MASK (0x0000FFFFu)#define CSL_ULPD_SETUP_ANALOG_CELL3_REG_SETUP_ANALOG_CELL3_SHIFT (0x00000000u)#define CSL_ULPD_SETUP_ANALOG_CELL3_REG_SETUP_ANALOG_CELL3_RESETVAL (0x000003FFu)#define CSL_ULPD_SETUP_ANALOG_CELL3_REG_RESETVAL (0x000003FFu)/* SETUP_ANALOG_CELL2_REG */#define CSL_ULPD_SETUP_ANALOG_CELL2_REG_SETUP_ANALOG_CELL2_MASK (0x0000FFFFu)#define CSL_ULPD_SETUP_ANALOG_CELL2_REG_SETUP_ANALOG_CELL2_SHIFT (0x00000000u)#define CSL_ULPD_SETUP_ANALOG_CELL2_REG_SETUP_ANALOG_CELL2_RESETVAL (0x00000000u)#define CSL_ULPD_SETUP_ANALOG_CELL2_REG_RESETVAL (0x00000000u)/* SETUP_ANALOG_CELL1_REG */#define CSL_ULPD_SETUP_ANALOG_CELL1_REG_SETUP_ANALOG_CELL1_MASK (0x0000FFFFu)#define CSL_ULPD_SETUP_ANALOG_CELL1_REG_SETUP_ANALOG_CELL1_SHIFT (0x00000000u)#define CSL_ULPD_SETUP_ANALOG_CELL1_REG_SETUP_ANALOG_CELL1_RESETVAL (0x00000000u)#define CSL_ULPD_SETUP_ANALOG_CELL1_REG_RESETVAL (0x00000000u)/* CLOCK_CTRL_REG */#define CSL_ULPD_CLOCK_CTRL_REG_SLICER_BYPASS_MASK (0x00000040u)#define CSL_ULPD_CLOCK_CTRL_REG_SLICER_BYPASS_SHIFT (0x00000006u)#define CSL_ULPD_CLOCK_CTRL_REG_SLICER_BYPASS_RESETVAL (0x00000000u)#define CSL_ULPD_CLOCK_CTRL_REG_SLICER_BYPASS_ENABLE (0x00000000u)#define CSL_ULPD_CLOCK_CTRL_REG_SLICER_BYPASS_DISABLE (0x00000001u)#define CSL_ULPD_CLOCK_CTRL_REG_DIS_USB_PVCI_CLK_MASK (0x00000020u)#define CSL_ULPD_CLOCK_CTRL_REG_DIS_USB_PVCI_CLK_SHIFT (0x00000005u)#define CSL_ULPD_CLOCK_CTRL_REG_DIS_USB_PVCI_CLK_RESETVAL (0x00000000u)#define CSL_ULPD_CLOCK_CTRL_REG_DIS_USB_PVCI_CLK_ENABLE (0x00000000u)#define CSL_ULPD_CLOCK_CTRL_REG_DIS_USB_PVCI_CLK_DISABLE (0x00000001u)#define CSL_ULPD_CLOCK_CTRL_REG_USB_MCLK_EN_MASK (0x00000010u)#define CSL_ULPD_CLOCK_CTRL_REG_USB_MCLK_EN_SHIFT (0x00000004u)#define CSL_ULPD_CLOCK_CTRL_REG_USB_MCLK_EN_RESETVAL (0x00000000u)#define CSL_ULPD_CLOCK_CTRL_REG_USB_MCLK_EN_ENABLE (0x00000001u)#define CSL_ULPD_CLOCK_CTRL_REG_USB_MCLK_EN_DISABLE (0x00000000u)#define CSL_ULPD_CLOCK_CTRL_REG_TI_RESERVED_EN_MASK (0x00000008u)#define CSL_ULPD_CLOCK_CTRL_REG_TI_RESERVED_EN_SHIFT (0x00000003u)#define CSL_ULPD_CLOCK_CTRL_REG_TI_RESERVED_EN_RESETVAL (0x00000000u)#define CSL_ULPD_CLOCK_CTRL_REG_TI_RESERVED_EN_ENABLE (0x00000001u)#define CSL_ULPD_CLOCK_CTRL_REG_TI_RESERVED_EN_DISABLE (0x00000000u)#define CSL_ULPD_CLOCK_CTRL_REG_SDW_MCLK_INV_MASK (0x00000004u)#define CSL_ULPD_CLOCK_CTRL_REG_SDW_MCLK_INV_SHIFT (0x00000002u)#define CSL_ULPD_CLOCK_CTRL_REG_SDW_MCLK_INV_RESETVAL (0x00000000u)#define CSL_ULPD_CLOCK_CTRL_REG_SDW_MCLK_INV_CLKHIGH (0x00000001u)#define CSL_ULPD_CLOCK_CTRL_REG_SDW_MCLK_INV_CLKLOW (0x00000000u)#define CSL_ULPD_CLOCK_CTRL_REG_COM_MCLK_INV_MASK (0x00000002u)#define CSL_ULPD_CLOCK_CTRL_REG_COM_MCLK_INV_SHIFT (0x00000001u)#define CSL_ULPD_CLOCK_CTRL_REG_COM_MCLK_INV_RESETVAL (0x00000000u)#define CSL_ULPD_CLOCK_CTRL_REG_COM_MCLK_INV_CLKHIGH (0x00000001u)#define CSL_ULPD_CLOCK_CTRL_REG_COM_MCLK_INV_CLKLOW (0x00000000u)#define CSL_ULPD_CLOCK_CTRL_REG_MODEM_32K_EN_MASK (0x00000001u)#define CSL_ULPD_CLOCK_CTRL_REG_MODEM_32K_EN_SHIFT (0x00000000u)#define CSL_ULPD_CLOCK_CTRL_REG_MODEM_32K_EN_RESETVAL (0x00000000u)#define CSL_ULPD_CLOCK_CTRL_REG_MODEM_32K_EN_ENABLE (0x00000001u)#define CSL_ULPD_CLOCK_CTRL_REG_MODEM_32K_EN_DISABLE (0x00000000u)#define CSL_ULPD_CLOCK_CTRL_REG_RESETVAL (0x00000000u)/* SOFT_REQ_REG */#define CSL_ULPD_SOFT_REQ_REG_SOFT_CLOCK2_DPLL_REQ_MASK (0x00008000u)#define CSL_ULPD_SOFT_REQ_REG_SOFT_CLOCK2_DPLL_REQ_SHIFT (0x0000000Fu)#define CSL_ULPD_SOFT_REQ_REG_SOFT_CLOCK2_DPLL_REQ_RESETVAL (0x00000000u)#define CSL_ULPD_SOFT_REQ_REG_SOFT_CLOCK2_DPLL_REQ_ACTIVE (0x00000001u)#define CSL_ULPD_SOFT_REQ_REG_SOFT_CLOCK2_DPLL_REQ_INACTIVE (0x00000000u)#define CSL_ULPD_SOFT_REQ_REG_SOFT_CLOCK1_DPLL_REG_MASK (0x00004000u)#define CSL_ULPD_SOFT_REQ_REG_SOFT_CLOCK1_DPLL_REG_SHIFT (0x0000000Eu)#define CSL_ULPD_SOFT_REQ_REG_SOFT_CLOCK1_DPLL_REG_RESETVAL (0x00000000u)#define CSL_ULPD_SOFT_REQ_REG_SOFT_CLOCK1_DPLL_REG_ACTIVE (0x00000001u)#define CSL_ULPD_SOFT_REQ_REG_SOFT_CLOCK1_DPLL_REG_INACTIVE (0x00000000u)#define CSL_ULPD_SOFT_REQ_REG_SOFT_MMC2_DPLL_REQ_MASK (0x00002000u)#define CSL_ULPD_SOFT_REQ_REG_SOFT_MMC2_DPLL_REQ_SHIFT (0x0000000Du)#define CSL_ULPD_SOFT_REQ_REG_SOFT_MMC2_DPLL_REQ_RESETVAL (0x00000000u)#define CSL_ULPD_SOFT_REQ_REG_SOFT_MMC2_DPLL_REQ_ACTIVE (0x00000001u)#define CSL_ULPD_SOFT_REQ_REG_SOFT_MMC2_DPLL_REQ_INACTIVE (0x00000000u)#define CSL_ULPD_SOFT_REQ_REG_SOFT_MMC_DPLL_REQ_MASK (0x00001000u)#define CSL_ULPD_SOFT_REQ_REG_SOFT_MMC_DPLL_REQ_SHIFT (0x0000000Cu)#define CSL_ULPD_SOFT_REQ_REG_SOFT_MMC_DPLL_REQ_RESETVAL (0x00000000u)#define CSL_ULPD_SOFT_REQ_REG_SOFT_MMC_DPLL_REQ_ACTIVE (0x00000001u)#define CSL_ULPD_SOFT_REQ_REG_SOFT_MMC_DPLL_REQ_INACTIVE (0x00000000u)#define CSL_ULPD_SOFT_REQ_REG_SOFT_UART3_DPLL_REQ_MASK (0x00000800u)#define CSL_ULPD_SOFT_REQ_REG_SOFT_UART3_DPLL_REQ_SHIFT (0x0000000Bu)#define CSL_ULPD_SOFT_REQ_REG_SOFT_UART3_DPLL_REQ_RESETVAL (0x00000000u)#define CSL_ULPD_SOFT_REQ_REG_SOFT_UART3_DPLL_REQ_ACTIVE (0x00000001u)#define CSL_ULPD_SOFT_REQ_REG_SOFT_UART3_DPLL_REQ_INACTIVE (0x00000000u)#define CSL_ULPD_SOFT_REQ_REG_SOFT_UART2_DPLL_REQ_MASK (0x00000400u)#define CSL_ULPD_SOFT_REQ_REG_SOFT_UART2_DPLL_REQ_SHIFT (0x0000000Au)#define CSL_ULPD_SOFT_REQ_REG_SOFT_UART2_DPLL_REQ_RESETVAL (0x00000000u)#define CSL_ULPD_SOFT_REQ_REG_SOFT_UART2_DPLL_REQ_ACTIVE (0x00000001u)#define CSL_ULPD_SOFT_REQ_REG_SOFT_UART2_DPLL_REQ_INACTIVE (0x00000000u)#define CSL_ULPD_SOFT_REQ_REG_SOFT_UART1_DPLL_REQ_MASK (0x00000200u)#define CSL_ULPD_SOFT_REQ_REG_SOFT_UART1_DPLL_REQ_SHIFT (0x00000009u)#define CSL_ULPD_SOFT_REQ_REG_SOFT_UART1_DPLL_REQ_RESETVAL (0x00000000u)
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