cslr_emifs.h

来自「dsp在音频处理中的运用」· C头文件 代码 · 共 279 行

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/*****************************************************\ *  Copyright 2003, Texas Instruments Incorporated.  * *  All rights reserved.                             * *  Restricted rights to use, duplicate or disclose  * *  this   code   are  granted   through  contract.  * *                                                   * * "@(#) PSP/CSL  3.0.0.0  (2003-09-30)              *\*****************************************************/#ifndef _CSLR_EMIFS_001_H_#define _CSLR_EMIFS_001_H_#include <cslr.h>#include <tistdtypes.h>/**************************************************************************\* Register Overlay Structure\**************************************************************************/typedef struct  {    const Uint8 PAD0[4];    Uint32 PR;    const Uint8 PAD1[4];    Uint32 CR;    Uint32 NCS[4];    const Uint8 PAD2[8];    Uint32 DAPTR1;    Uint32 DAPTR2;    Uint32 DAPTR3;    const Uint8 PAD3[12];    Uint32 DWSCR;    Uint32 AAR;    Uint32 ATR;    Uint32 ATOR;    Uint32 ANCS[4];} CSL_EmifsRegs;/**************************************************************************\* Overlay structure typedef definition\**************************************************************************/typedef volatile CSL_EmifsRegs  * CSL_EmifsRegsOvly;/**************************************************************************\* Field Definition Macros\**************************************************************************/  /* CSL_EMIFS_PR */#define CSL_EMIFS_PR_OCPI_MASK        (0x0000F000u)#define CSL_EMIFS_PR_OCPI_SHIFT       (0x0000000Cu)#define CSL_EMIFS_PR_OCPI_RESETVAL    (0x00000000u)#define CSL_EMIFS_PR_DMA_MASK         (0x00000F00u)#define CSL_EMIFS_PR_DMA_SHIFT        (0x00000008u)#define CSL_EMIFS_PR_DMA_RESETVAL     (0x00000000u)#define CSL_EMIFS_PR_DSP_MASK         (0x00000070u)#define CSL_EMIFS_PR_DSP_SHIFT        (0x00000004u)#define CSL_EMIFS_PR_DSP_RESETVAL     (0x00000000u)#define CSL_EMIFS_PR_MPU_MASK         (0x00000007u)#define CSL_EMIFS_PR_MPU_SHIFT        (0x00000000u)#define CSL_EMIFS_PR_MPU_RESETVAL     (0x00000000u)#define CSL_EMIFS_PR_RESETVAL         (0x00000000u)  /* CSL_EMIFS_CR */#define CSL_EMIFS_CR_FR_MASK          (0x00000010u)#define CSL_EMIFS_CR_FR_SHIFT         (0x00000004u)#define CSL_EMIFS_CR_FR_RESETVAL      (0x00000000u)#define CSL_EMIFS_CR_PDE_MASK         (0x00000008u)#define CSL_EMIFS_CR_PDE_SHIFT        (0x00000003u)#define CSL_EMIFS_CR_PDE_RESETVAL     (0x00000000u)#define CSL_EMIFS_CR_PWDEN_MASK       (0x00000004u)#define CSL_EMIFS_CR_PWDEN_SHIFT      (0x00000002u)#define CSL_EMIFS_CR_PWDEN_RESETVAL   (0x00000000u)#define CSL_EMIFS_CR_BM_MASK          (0x00000002u)#define CSL_EMIFS_CR_BM_SHIFT         (0x00000001u)#define CSL_EMIFS_CR_BM_RESETVAL      (0x00000000u)#define CSL_EMIFS_CR_WP_MASK          (0x00000001u)#define CSL_EMIFS_CR_WP_SHIFT         (0x00000000u)#define CSL_EMIFS_CR_WP_RESETVAL      (0x00000000u)#define CSL_EMIFS_CR_RESETVAL         (0x00000000u)  /* CSL_EMIFS_NCS */#define CSL_EMIFS_NCS_PGWSTEN_MASK    (0x80000000u)#define CSL_EMIFS_NCS_PGWSTEN_SHIFT   (0x0000001Fu)#define CSL_EMIFS_NCS_PGWSTEN_RESETVAL                                    \          (0x00000000u)#define CSL_EMIFS_NCS_PGWST_MASK      (0x78000000u)#define CSL_EMIFS_NCS_PGWST_SHIFT     (0x0000001Bu)#define CSL_EMIFS_NCS_PGWST_RESETVAL  (0x00000000u)#define CSL_EMIFS_NCS_BTWST_MASK      (0x07800000u)#define CSL_EMIFS_NCS_BTWST_SHIFT     (0x00000017u)#define CSL_EMIFS_NCS_BTWST_RESETVAL  (0x00000000u)#define CSL_EMIFS_NCS_MAD_MASK        (0x00400000u)#define CSL_EMIFS_NCS_MAD_SHIFT       (0x00000016u)#define CSL_EMIFS_NCS_MAD_RESETVAL    (0x00000000u)#define CSL_EMIFS_NCS_FL_MASK         (0x00200000u)#define CSL_EMIFS_NCS_FL_SHIFT        (0x00000015u)#define CSL_EMIFS_NCS_FL_RESETVAL     (0x00000000u)#define CSL_EMIFS_NCS_BW_MASK         (0x00100000u)#define CSL_EMIFS_NCS_BW_SHIFT        (0x00000014u)#define CSL_EMIFS_NCS_BW_RESETVAL     (0x00000000u)#define CSL_EMIFS_NCS_RDMODE_MASK     (0x00070000u)#define CSL_EMIFS_NCS_RDMODE_SHIFT    (0x00000010u)#define CSL_EMIFS_NCS_RDMODE_RESETVAL (0x00000000u)#define CSL_EMIFS_NCS_PGWSWLEN_MASK   (0x0000F000u)#define CSL_EMIFS_NCS_PGWSWLEN_SHIFT  (0x0000000Cu)#define CSL_EMIFS_NCS_PGWSWLEN_RESETVAL                                   \          (0x0000000Fu)#define CSL_EMIFS_NCS_WRWST_MASK      (0x00000F00u)#define CSL_EMIFS_NCS_WRWST_SHIFT     (0x00000008u)#define CSL_EMIFS_NCS_WRWST_RESETVAL  (0x0000000Fu)#define CSL_EMIFS_NCS_RDWST_MASK      (0x000000F0u)#define CSL_EMIFS_NCS_RDWST_SHIFT     (0x00000004u)#define CSL_EMIFS_NCS_RDWST_RESETVAL  (0x0000000Fu)#define CSL_EMIFS_NCS_RT_MASK         (0x00000004u)#define CSL_EMIFS_NCS_RT_SHIFT        (0x00000002u)#define CSL_EMIFS_NCS_RT_RESETVAL     (0x00000000u)#define CSL_EMIFS_NCS_FCLKDIV_MASK    (0x00000003u)#define CSL_EMIFS_NCS_FCLKDIV_SHIFT   (0x00000000u)#define CSL_EMIFS_NCS_FCLKDIV_RESETVAL                                    \          (0x00000003u)#define CSL_EMIFS_NCS_RESETVAL        (0x0000FFF3u)  /* CSL_EMIFS_DAPTR1 */#define CSL_EMIFS_DAPTR1_DMA_MASK     (0x000000FFu)#define CSL_EMIFS_DAPTR1_DMA_SHIFT    (0x00000000u)#define CSL_EMIFS_DAPTR1_DMA_RESETVAL (0x00000000u)#define CSL_EMIFS_DAPTR1_RESETVAL     (0x00000000u)  /* CSL_EMIFS_DAPTR2 */#define CSL_EMIFS_DAPTR2_DSP_MASK     (0x000000FFu)#define CSL_EMIFS_DAPTR2_DSP_SHIFT    (0x00000000u)#define CSL_EMIFS_DAPTR2_DSP_RESETVAL (0x00000000u)#define CSL_EMIFS_DAPTR2_RESETVAL     (0x00000000u)  /* CSL_EMIFS_DAPTR3 */#define CSL_EMIFS_DAPTR3_OCPI_MASK    (0x000000FFu)#define CSL_EMIFS_DAPTR3_OCPI_SHIFT   (0x00000000u)#define CSL_EMIFS_DAPTR3_OCPI_RESETVAL                                    \          (0x00000000u)#define CSL_EMIFS_DAPTR3_RESETVAL     (0x00000000u)  /* CSL_EMIFS_DWSCR */#define CSL_EMIFS_DWSCR_FHSEN3_MASK   (0x00000080u)#define CSL_EMIFS_DWSCR_FHSEN3_SHIFT  (0x00000007u)#define CSL_EMIFS_DWSCR_FHSEN3_RESETVAL                                   \          (0x00000000u)#define CSL_EMIFS_DWSCR_FHSEN2_MASK   (0x00000040u)#define CSL_EMIFS_DWSCR_FHSEN2_SHIFT  (0x00000006u)#define CSL_EMIFS_DWSCR_FHSEN2_RESETVAL                                   \          (0x00000000u)#define CSL_EMIFS_DWSCR_FHSEN1_MASK   (0x00000020u)#define CSL_EMIFS_DWSCR_FHSEN1_SHIFT  (0x00000005u)#define CSL_EMIFS_DWSCR_FHSEN1_RESETVAL                                   \          (0x00000000u)#define CSL_EMIFS_DWSCR_FHSEN0_MASK   (0x00000010u)#define CSL_EMIFS_DWSCR_FHSEN0_SHIFT  (0x00000004u)#define CSL_EMIFS_DWSCR_FHSEN0_RESETVAL                                   \          (0x00000000u)#define CSL_EMIFS_DWSCR_DWSEN3_MASK   (0x00000008u)#define CSL_EMIFS_DWSCR_DWSEN3_SHIFT  (0x00000003u)#define CSL_EMIFS_DWSCR_DWSEN3_RESETVAL                                   \          (0x00000000u)#define CSL_EMIFS_DWSCR_DWSEN2_MASK   (0x00000004u)#define CSL_EMIFS_DWSCR_DWSEN2_SHIFT  (0x00000002u)#define CSL_EMIFS_DWSCR_DWSEN2_RESETVAL                                   \          (0x00000000u)#define CSL_EMIFS_DWSCR_DWSEN1_MASK   (0x00000002u)#define CSL_EMIFS_DWSCR_DWSEN1_SHIFT  (0x00000001u)#define CSL_EMIFS_DWSCR_DWSEN1_RESETVAL                                   \          (0x00000000u)#define CSL_EMIFS_DWSCR_DWSEN0_MASK   (0x00000001u)#define CSL_EMIFS_DWSCR_DWSEN0_SHIFT  (0x00000000u)#define CSL_EMIFS_DWSCR_DWSEN0_RESETVAL                                   \          (0x00000000u)#define CSL_EMIFS_DWSCR_RESETVAL      (0x00000000u)  /* CSL_EMIFS_AAR */#define CSL_EMIFS_AAR_ABADDR_MASK     (0xFFFFFFFFu)#define CSL_EMIFS_AAR_ABADDR_SHIFT    (0x00000000u)#define CSL_EMIFS_AAR_ABADDR_RESETVAL (0x00000000u)#define CSL_EMIFS_AAR_RESETVAL        (0x00000000u)  /* CSL_EMIFS_ATR */#define CSL_EMIFS_ATR_TOERR_MASK      (0x00000010u)#define CSL_EMIFS_ATR_TOERR_SHIFT     (0x00000004u)#define CSL_EMIFS_ATR_TOERR_RESETVAL  (0x00000000u)#define CSL_EMIFS_ATR_RAMERR_MASK     (0x00000008u)#define CSL_EMIFS_ATR_RAMERR_SHIFT    (0x00000003u)#define CSL_EMIFS_ATR_RAMERR_RESETVAL (0x00000000u)#define CSL_EMIFS_ATR_HOSTID_MASK     (0x00000006u)#define CSL_EMIFS_ATR_HOSTID_SHIFT    (0x00000001u)#define CSL_EMIFS_ATR_HOSTID_RESETVAL (0x00000000u)#define CSL_EMIFS_ATR_ABFLAG_MASK     (0x00000001u)#define CSL_EMIFS_ATR_ABFLAG_SHIFT    (0x00000000u)#define CSL_EMIFS_ATR_ABFLAG_RESETVAL (0x00000000u)#define CSL_EMIFS_ATR_RESETVAL        (0x00000000u)  /* CSL_EMIFS_ATOR */#define CSL_EMIFS_ATOR_TOEN_MASK      (0x00000100u)#define CSL_EMIFS_ATOR_TOEN_SHIFT     (0x00000008u)#define CSL_EMIFS_ATOR_TOEN_RESETVAL  (0x00000000u)#define CSL_EMIFS_ATOR_TOVAL_MASK     (0x000000FFu)#define CSL_EMIFS_ATOR_TOVAL_SHIFT    (0x00000000u)#define CSL_EMIFS_ATOR_TOVAL_RESETVAL (0x000000FFu)#define CSL_EMIFS_ATOR_RESETVAL       (0x000000FFu)  /* CSL_EMIFS_ANCS */#define CSL_EMIFS_ANCS_BTMD_MASK      (0x00000200u)#define CSL_EMIFS_ANCS_BTMD_SHIFT     (0x00000009u)#define CSL_EMIFS_ANCS_BTMD_RESETVAL  (0x00000000u)#define CSL_EMIFS_ANCS_ADVHLD_MASK    (0x00000100u)#define CSL_EMIFS_ANCS_ADVHLD_SHIFT   (0x00000008u)#define CSL_EMIFS_ANCS_ADVHLD_RESETVAL                                    \          (0x00000000u)#define CSL_EMIFS_ANCS_OEHLD_MASK     (0x000000F0u)#define CSL_EMIFS_ANCS_OEHLD_SHIFT    (0x00000004u)#define CSL_EMIFS_ANCS_OEHLD_RESETVAL (0x00000000u)#define CSL_EMIFS_ANCS_OESETUP_MASK   (0x0000000Fu)#define CSL_EMIFS_ANCS_OESETUP_SHIFT  (0x00000000u)#define CSL_EMIFS_ANCS_OESETUP_RESETVAL                                   \          (0x00000000u)#define CSL_EMIFS_ANCS_RESETVAL       (0x00000000u)#endif

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