cslr_wdt.h

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/** ============================================================================
 *   @file  cslr_wdt.h
 *
 *   @path  $(CSLPATH)\arm\wdt\src
 *
 *   @desc  Register layer header file for the OMAP3.2 watchdog timer CSL on ARM
 *          side
 * =============================================================================
 */

/*  ============================================================================
 *   Copyright (c) Texas Instruments Inc 2002, 2003, 2004
 *
 *   Use of this software is controlled by the terms and conditions found in the
 *   license agreement under which this software has been supplied.
 *   ===========================================================================
 */

/* =============================================================================
 *  Revision History
 *  ================
 *  24-May-2004 ka File Created.
 *  28-Jun-2004 ka Changes for the new CSL architecture
 *
 * =============================================================================
 */
#ifndef _CSLR_WDT_H_
#define _CSLR_WDT_H_

#include <cslr.h>
#include <tistdtypes.h>

/**
 * Register overlay structure
 */
typedef struct  {
    /** Watchdog timer control register */
    volatile Uint32 CNTL;

    /**
      * Watchdog timer load/read register. Both watchdog timer load register and
      * read register are present at the same offset (0x04). Load register is
      * selected when write access is made to this location. Read register is
      * selected when read access is made to this location.
      */
    volatile Uint32 LOADREAD;

    /** Watchdog timer mode register */
    volatile Uint32 MODE;
} CSL_WdtRegs;

/**
 * Overlay structure typedef definition
 */
typedef volatile CSL_WdtRegs * CSL_WdtRegsOvly;


/*******************************************************************************
 * Field Definition Macros
 ******************************************************************************/

/*******************************************************************************
 * Control register (CNTL)
 ******************************************************************************/

/** CNTL PTV - field mask */
#define CSL_WDT_CNTL_PTV_MASK            (0x00000E00u)
/** CNTL PTV - field shift value */
#define CSL_WDT_CNTL_PTV_SHIFT           (0x00000009u)
/** CNTL PTV - field reset value */
#define CSL_WDT_CNTL_PTV_RESETVAL        (0x00000007u)
/** Divide the input reference clock by 2 */
#define CSL_WDT_CNTL_PTV_CLKBY2          (0x00000000u)
/** Divide the input reference clock by 4 */
#define CSL_WDT_CNTL_PTV_CLKBY4          (0x00000001u)
/** Divide the input reference clock by 8 */
#define CSL_WDT_CNTL_PTV_CLKBY8          (0x00000002u)
/** Divide the input reference clock by 16 */
#define CSL_WDT_CNTL_PTV_CLKBY16         (0x00000003u)
/** Divide the input reference clock by 32 */
#define CSL_WDT_CNTL_PTV_CLKBY32         (0x00000004u)
/** Divide the input reference clock by 64 */
#define CSL_WDT_CNTL_PTV_CLKBY64         (0x00000005u)
/** Divide the input reference clock by 128 */
#define CSL_WDT_CNTL_PTV_CLKBY128        (0x00000006u)
/** Divide the input reference clock by 256 */
#define CSL_WDT_CNTL_PTV_CLKBY256        (0x00000007u)

/** CNTL AR - filed mask */
#define CSL_WDT_CNTL_AR_MASK             (0x00000100u)
/** CNTL AR - filed shift */
#define CSL_WDT_CNTL_AR_SHIFT            (0x00000008u)
/** CNTL AR - filed reset value */
#define CSL_WDT_CNTL_AR_RESETVAL         (0x00000001u)
/** CNTL AR - set in one-shot mode */
#define CSL_WDT_CNTL_AR_DISABLE          (0x00000000u)
/** CNTL AR - set in auto reload mode */
#define CSL_WDT_CNTL_AR_ENABLE           (0x00000001u)

/** CNTL ST - field mask */
#define CSL_WDT_CNTL_ST_MASK             (0x00000080u)
/** CNTL ST - field shift */
#define CSL_WDT_CNTL_ST_SHIFT            (0x00000007u)
/** CNTL ST - field reset value */
#define CSL_WDT_CNTL_ST_RESETVAL         (0x00000000u)
/** CNTL ST - stop the watchdog timer */
#define CSL_WDT_CNTL_ST_RESET            (0x00000000u)
/** CNTL ST - start the watchdog timer */
#define CSL_WDT_CNTL_ST_SET              (0x00000001u)

/** CNTL FREE - field mask */
#define CSL_WDT_CNTL_FREE_MASK           (0x00000002u)
/** CNTL FREE - field shift */
#define CSL_WDT_CNTL_FREE_SHIFT          (0x00000001u)
/** CNTL FREE - field reset value */
#define CSL_WDT_CNTL_FREE_RESETVAL       (0x00000001u)
/** CNTL FREE - stop counting on suspend indication */
#define CSL_WDT_CNTL_FREE_RESET          (0x00000000u)
/** CNTL FREE - a suspend indication has no effect on the count */
#define CSL_WDT_CNTL_FREE_SET            (0x00000001u)

/** CNTL reset value */
#define CSL_WDT_CNTL_RESETVAL            (0x00000F02u)


/*******************************************************************************
 * MPU Load/Read timer register
 ******************************************************************************/

/** LOAD_TIMER/VALUE_TIMER - field mask */
#define CSL_WDT_LOADREAD_LOADREAD_TIMER_MASK (0x0000FFFFu)
/** LOAD_TIMER/VALUE_TIMER - field shift */
#define CSL_WDT_LOADREAD_LOADREAD_TIMER_SHIFT (0x00000000u)
/** LOAD_TIMER/VALUE_TIMER - field reset value */
#define CSL_WDT_LOADREAD_LOADREAD_TIMER_RESETVAL (0x00000000u)

/** Load/Read timer register reset value */
#define CSL_WDT_LOADREAD_RESETVAL        (0x0000FFFFu)


/*******************************************************************************
 * Watchdog timer mode register
 ******************************************************************************/

/** WATCHDOG - field mask */
#define CSL_WDT_MODE_WATCHDOG_MASK       (0x00008000u)
/** WATCHDOG - field shift */
#define CSL_WDT_MODE_WATCHDOG_SHIFT      (0x0000000Fu)
/** WATCHDOG - field reset value */
#define CSL_WDT_MODE_WATCHDOG_RESETVAL   (0x00000001u)
/** General purpose timer mode */
#define CSL_WDT_MODE_WATCHDOG_GPT_MODE   (0x00000000u)
/** Watchdog timer mode */
#define CSL_WDT_MODE_WATCHDOG_WDT_MODE   (0x00000001u)

/** WATCHDOG_DIS - field mask */
#define CSL_WDT_MODE_WATCHDOG_DIS_MASK   (0x000000FFu)
/** WATCHDOG_DIS - field shift */
#define CSL_WDT_MODE_WATCHDOG_DIS_SHIFT  (0x00000000u)
/** WATCHDOG_DIS - reset value */
#define CSL_WDT_MODE_WATCHDOG_DIS_RESETVAL (0x00000000u)
/** Watchdog timer stop command 1 */
#define CSL_WDT_MODE_WATCHDOG_DIS_CMD1   (0x000000F5u)
/** Watchdog timer stop command 2 */
#define CSL_WDT_MODE_WATCHDOG_DIS_CMD2   (0x000000A0u)

/** Watchdog timer mode register reset value */
#define CSL_WDT_MODE_RESETVAL            (0x00008000u)

#endif /* _CSLR_WDT_001_H_ */