soc.h

dsp在音频处理中的运用

#define CSL_GPTIMER_4      (3)  /** Instance4 of GPTIMER  */

#define CSL_GPTIMER_5      (4)  /** Instance5 of GPTIMER  */

#define CSL_GPTIMER_6      (5)  /** Instance6 of GPTIMER  */

#define CSL_GPTIMER_7      (6)  /** Instance7 of GPTIMER  */

#define CSL_GPTIMER_8      (7)  /** Instance8 of GPTIMER  */

/** @brief Peripheral Instance of WDTimer  */
#define CSL_WDT            (0)  /** Instance1 of WDTimer  */

/** @brief Peripheral Instance of HECC  */
#define CSL_HECC_1          (0)  /** Instance of HECC  */

#define CSL_HECC_2          (1)  /** Instance of HECC  */

/** @brief Peripheral Instance of RTC  */
#define CSL_RTC            (0)  /** Instance of RTC  */

/** @brief Peripheral Instance of ADCC */
#define CSL_ADCC           (0)  /** Instance of ADCC */

/** @brief Peripheral Instance enumeration for GPIO  */
#define CSL_GPIO_1          (0)  /** Instance1 of GPIO  */

#define CSL_GPIO_2          (1)  /** Instance2 of GPIO  */

#define CSL_GPIO_3          (2)  /** Instance3 of GPIO  */

#define CSL_GPIO_4          (3)  /** Instance4 of GPIO  */

/** @brief Peripheral Instance of LCD Controller */
#define CSL_LCDCTRL         (0)  /** Instance of LCD controller */

/** @brief Peripheral Instance of LEDPG */
#define CSL_LEDPG_1         (0)  /** Instance 1 of LEDPG controller */

#define CSL_LEDPG_2         (1)  /** Instance 2 of LEDPG controller */

/** @brief Peripheral Instance of PWL */
#define CSL_PWL         (0)  /** Instance 1 of PWL controller */

/** @brief Peripheral Instance of LCDCONV */
#define CSL_LCD_CONV         (0)  /** Instance 1 of LCDCONV  */

/** @brief Peripheral Instance of OSTIMER */
#define CSL_OSTIMER         (0)  /** Instance 1 of OSTIMER  */

/** @brief Peripheral Instance of SOSSI */
#define CSL_SOSSI         (0)  /** Instance 1 of SOSSI  */

/** @brief Peripheral Instance of CCP */
#define CSL_CCP        (0)  /** Instance 1 of CCP*/

/** @brief Peripheral Instance of UWIRE */
#define CSL_UWIRE        (0)  /** Instance 1 of UWIRE*/

/** @brief Peripheral Instance of SSR */
#define CSL_SSR        (0)  /** Instance 1 of SSR*/

/** @brief Peripheral Instance of SST */
#define CSL_SST        (0)  /** Instance 1 of SST*/

/** @brief Peripheral Instance of CAMERA IF */
#define CSL_CAM        (0)  /** Instance 1 of CAMERA IF*/

/** @brief Peripheral Instance of PWT */
#define CSL_PWT        (0)  /** Instance 1 of PWT*/

/** @brief Peripheral Instance of HDQ1WIRE */
#define CSL_HDQ1W        (0)  /** Instance 1 of HDQ1WIRE*/

/** @brief Peripheral Instance of OCPT1 */
#define CSL_OCPT1        (0)  /** Instance 1 of OCPT1 */

/** @brief Peripheral Instance of SPL */
#define CSL_SPL             (0)  /** Instance 1 of SPL */

/** @brief Peripheral Instance of SPI */
#define CSL_SPI             (0)  /** Instance 1 of SPI */

/* Interrupt/Exception Counts */
#define __CSL_INTC_EVENTID__INTC0CNT__     (8)      /* ARM exception count */
#define __CSL_INTC_EVENTID__INTC1CNT__     (32)     /* Level-1 Interrupt count */
#define __CSL_INTC_EVENTID__INTC2CNT__     (128)    /* Level-2 Interrupt count */

/**
 * @brief   Interrupt Event IDs
 */
#define _CSL_INTC_EVENTID__INTC1START           (0)

#define CSL_INTC_EVENTID_L2IRQ                  (_CSL_INTC_EVENTID__INTC1START + 0)  /**< Level 2 interrupt handler IRQ */
#define CSL_INTC_EVENTID_CAMERAIF               (_CSL_INTC_EVENTID__INTC1START + 1)  /**< Camera Interface */
#define CSL_INTC_EVENTID_L2FIQ                  (_CSL_INTC_EVENTID__INTC1START + 2)  /**< Level 2 interrupt handler FIQ */
#define CSL_INTC_EVENTID_EXTLFIQ                (_CSL_INTC_EVENTID__INTC1START + 3)  /**< External FIQ (User-defined) */
#define CSL_INTC_EVENTID_MCBSP2TX               (_CSL_INTC_EVENTID__INTC1START + 4)  /**< McBSP2 TX */
#define CSL_INTC_EVENTID_MCBSP2RX               (_CSL_INTC_EVENTID__INTC1START + 5)  /**< McBSP2 RX */
#define CSL_INTC_EVENTID_RTDX                   (_CSL_INTC_EVENTID__INTC1START + 6)  /**< Emulation event */
#define CSL_INTC_EVENTID_DSPMMUABORT            (_CSL_INTC_EVENTID__INTC1START + 7)  /**< DSP MMU ABORT */
#define CSL_INTC_EVENTID_HOSTINT                (_CSL_INTC_EVENTID__INTC1START + 8)  /**< HOST Interrupt */
#define CSL_INTC_EVENTID_ABORT                  (_CSL_INTC_EVENTID__INTC1START + 9)  /**< Abort Interrupt */
#define CSL_INTC_EVENTID_DSPMBX1                (_CSL_INTC_EVENTID__INTC1START + 10) /**< DSP_MAILBOX1 */
#define CSL_INTC_EVENTID_DSPMBX2                (_CSL_INTC_EVENTID__INTC1START + 11) /**< DSP_MAILBOX2 */
#define CSL_INTC_EVENTID_LCDLINE                (_CSL_INTC_EVENTID__INTC1START + 12) /**< LCD_LINE */
#define CSL_INTC_EVENTID_GPIO1                  (_CSL_INTC_EVENTID__INTC1START + 14) /**< GPIO1 */
#define CSL_INTC_EVENTID_UART3                  (_CSL_INTC_EVENTID__INTC1START + 15) /**< UART3 */
#define CSL_INTC_EVENTID_TIMER3                 (_CSL_INTC_EVENTID__INTC1START + 16) /**< TIMER3 */
#define CSL_INTC_EVENTID_GPTIMER1               (_CSL_INTC_EVENTID__INTC1START + 17) /**< GPTIMER1 */
#define CSL_INTC_EVENTID_GPTIMER2               (_CSL_INTC_EVENTID__INTC1START + 18) /**< GPTIMER2 */
#define CSL_INTC_EVENTID_DMACH0                 (_CSL_INTC_EVENTID__INTC1START + 19) /**< DMA Channel 0 */
#define CSL_INTC_EVENTID_DMACH0CH6              (_CSL_INTC_EVENTID__INTC1START + 19) /**< DMA Channel 0/6 (OMAP3.1) */
#define CSL_INTC_EVENTID_DMACH1                 (_CSL_INTC_EVENTID__INTC1START + 20) /**< DMA Channel 1 */
#define CSL_INTC_EVENTID_DMACH1CH7              (_CSL_INTC_EVENTID__INTC1START + 20) /**< DMA Channel 1/7 (OMAP3.1)*/
#define CSL_INTC_EVENTID_DMACH2                 (_CSL_INTC_EVENTID__INTC1START + 21) /**< DMA Channel 2 */
#define CSL_INTC_EVENTID_DMACH2CH8              (_CSL_INTC_EVENTID__INTC1START + 21) /**< DMA Channel 2/8 (OMAP3.1) */
#define CSL_INTC_EVENTID_DMACH3                 (_CSL_INTC_EVENTID__INTC1START + 22) /**< DMA Channel 3 */
#define CSL_INTC_EVENTID_DMACH4                 (_CSL_INTC_EVENTID__INTC1START + 23) /**< DMA Channel 4 */
#define CSL_INTC_EVENTID_DMACH5                 (_CSL_INTC_EVENTID__INTC1START + 24) /**< DMA Channel 5 */
#define CSL_INTC_EVENTID_DMACHLCD               (_CSL_INTC_EVENTID__INTC1START + 25) /**< DMA LCD Channel */
#define CSL_INTC_EVENTID_TIMER1                 (_CSL_INTC_EVENTID__INTC1START + 26) /**< Timer1 */
#define CSL_INTC_EVENTID_WDTIMER                (_CSL_INTC_EVENTID__INTC1START + 27) /**< Watchdog Timer */
#define CSL_INTC_EVENTID_RHEAPUBLIC             (_CSL_INTC_EVENTID__INTC1START + 28) /**< Public TIPB abort */
#define CSL_INTC_EVENTID_SPI1                   (_CSL_INTC_EVENTID__INTC1START + 29) /**< SSR FIFO full channel 0 */
#define CSL_INTC_EVENTID_TIMER2                 (_CSL_INTC_EVENTID__INTC1START + 30) /**< Timer2 */
#define CSL_INTC_EVENTID_LCDCTRL                (_CSL_INTC_EVENTID__INTC1START + 31) /**< LCD Controller */

#define _CSL_INTC_EVENTID__INTC1END             (_CSL_INTC_EVENTID__INTC1START + __CSL_INTC_EVENTID__INTC1CNT__ - 1)


#define _CSL_INTC_EVENTID__INTC2START           (_CSL_INTC_EVENTID__INTC1END + 1)

#define CSL_INTC_EVENTID_FAC                    (_CSL_INTC_EVENTID__INTC2START + 0)   /**< FAC */
#define CSL_INTC_EVENTID_KEYBOARD               (_CSL_INTC_EVENTID__INTC2START + 1)   /**< Keyboard */
#define CSL_INTC_EVENTID_UWIRETX                (_CSL_INTC_EVENTID__INTC2START + 2)   /**< 碬IRE TX */
#define CSL_INTC_EVENTID_UWIRERX                (_CSL_INTC_EVENTID__INTC2START + 3)   /**< 碬IRE RX */
#define CSL_INTC_EVENTID_I2C                    (_CSL_INTC_EVENTID__INTC2START + 4)   /**< I2C */
#define CSL_INTC_EVENTID_MPUIO                  (_CSL_INTC_EVENTID__INTC2START + 5)   /**< MPUIO */
#define CSL_INTC_EVENTID_USBHHC1                (_CSL_INTC_EVENTID__INTC2START + 6)   /**< USB HHC 1 */
#define CSL_INTC_EVENTID_USBHHC2                (_CSL_INTC_EVENTID__INTC2START + 7)   /**< USB HHC 2 */
#define CSL_INTC_EVENTID_USBOTG                 (_CSL_INTC_EVENTID__INTC2START + 8)   /**< USB OTG */
#define CSL_INTC_EVENTID_SOSSIATTN              (_CSL_INTC_EVENTID__INTC2START + 9)   /**< SoSSI attn */
#define CSL_INTC_EVENTID_MCBSP3TX               (_CSL_INTC_EVENTID__INTC2START + 10)  /**< McBSP3 TX */
#define CSL_INTC_EVENTID_MCBSP3RX               (_CSL_INTC_EVENTID__INTC2START + 11)  /**< McBSP3 RX */
#define CSL_INTC_EVENTID_MCBSP1TX               (_CSL_INTC_EVENTID__INTC2START + 12)  /**< McBSP1 TX */
#define CSL_INTC_EVENTID_MCBSP1RX               (_CSL_INTC_EVENTID__INTC2START + 13)  /**< McBSP1 RX */
#define CSL_INTC_EVENTID_UART1                  (_CSL_INTC_EVENTID__INTC2START + 14)  /**< UART1 */
#define CSL_INTC_EVENTID_UART2                  (_CSL_INTC_EVENTID__INTC2START + 15)  /**< UART2 */
#define CSL_INTC_EVENTID_MCSI1TX                (_CSL_INTC_EVENTID__INTC2START + 16)  /**< MCSI1 Transfer */
#define CSL_INTC_EVENTID_MCSI1RX                (_CSL_INTC_EVENTID__INTC2START + 16)  /**< MCSI1 Receive */
#define CSL_INTC_EVENTID_MCSI1FE                (_CSL_INTC_EVENTID__INTC2START + 16)  /**< MCSI1 Frame Error  */
#define CSL_INTC_EVENTID_MCSI1RST               (_CSL_INTC_EVENTID__INTC2START + 16)  /**< MCSI1 RST */
#define CSL_INTC_EVENTID_MCSI2TX                (_CSL_INTC_EVENTID__INTC2START + 17)  /**< MCSI2 Transfer */
#define CSL_INTC_EVENTID_MCSI2RX                (_CSL_INTC_EVENTID__INTC2START + 17)  /**< MCSI2 Receive */
#define CSL_INTC_EVENTID_MCSI2FE                (_CSL_INTC_EVENTID__INTC2START + 17)  /**< MCSI2 Frame Error  */
#define CSL_INTC_EVENTID_MCSI2RST               (_CSL_INTC_EVENTID__INTC2START + 17)  /**< MCSI2 RST */
#define CSL_INTC_EVENTID_SOSSIMATCH             (_CSL_INTC_EVENTID__INTC2START + 19)  /**< SoSSI match */
#define CSL_INTC_EVENTID_USBW2FGENIIT           (_CSL_INTC_EVENTID__INTC2START + 20)  /**< USB W2FC Geni it */
#define CSL_INTC_EVENTID_1WIRE                  (_CSL_INTC_EVENTID__INTC2START + 21)  /**< 1-Wire */
#define CSL_INTC_EVENTID_OSTIMER                (_CSL_INTC_EVENTID__INTC2START + 22)  /**< OS timer */
#define CSL_INTC_EVENTID_MMCSDIO1               (_CSL_INTC_EVENTID__INTC2START + 23)  /**< MMC/SDIO1 */
#define CSL_INTC_EVENTID_USBCLI                 (_CSL_INTC_EVENTID__INTC2START + 24)  /**< USB client wakeup IRQ */
#define CSL_INTC_EVENTID_32KGAUGE               (_CSL_INTC_EVENTID__INTC2START + 24)  /**< 32-kHz gauging IRQ */
#define CSL_INTC_EVENTID_RTCPERIODICAL          (_CSL_INTC_EVENTID__INTC2START + 25)  /**< RTC periodical timer */
#define CSL_INTC_EVENTID_RTCALARM               (_CSL_INTC_EVENTID__INTC2START + 26)  /**< RTC alarm */
#define CSL_INTC_EVENTID_MEMORYSTICK            (_CSL_INTC_EVENTID__INTC2START + 27)  /**< Memory Stick */
#define CSL_INTC_EVENTID_DSPMMU                 (_CSL_INTC_EVENTID__INTC2START + 28)  /**< DSP_MMU_IRQ */
#define CSL_INTC_EVENTID_USBW2FC_ISO_ON         (_CSL_INTC_EVENTID__INTC2START + 29)  /**< USB W2FC IRQ_ISO_ON */
#define CSL_INTC_EVENTID_USBW2FC_NON_ISO_ON     (_CSL_INTC_EVENTID__INTC2START + 30)  /**< USB W2FC IRQ_NON_ISO_ON */
#define CSL_INTC_EVENTID_MCBSP2RXOVERFLOW       (_CSL_INTC_EVENTID__INTC2START + 31)  /**< McBSP2 RX OVERFLOW */
#define CSL_INTC_EVENTID_STIGLOBAL              (_CSL_INTC_EVENTID__INTC2START + 32)  /**< STI global interrupt (reserved) */
#define CSL_INTC_EVENTID_STIWAKEUP              (_CSL_INTC_EVENTID__INTC2START + 33)  /**< STI wake-up (reserved) */
#define CSL_INTC_EVENTID_GPTIMER3               (_CSL_INTC_EVENTID__INTC2START + 34)  /**< GPTIMER3 */
#define CSL_INTC_EVENTID_GPTIMER4               (_CSL_INTC_EVENTID__INTC2START + 35)  /**< GPTIMER4 */
#define CSL_INTC_EVENTID_GPTIMER5               (_CSL_INTC_EVENTID__INTC2START + 36)  /**< GPTIMER5 */
#define CSL_INTC_EVENTID_GPTIMER6               (_CSL_INTC_EVENTID__INTC2START + 37)  /**< GPTIMER6 */
#define CSL_INTC_EVENTID_GPTIMER7               (_CSL_INTC_EVENTID__INTC2START + 38)  /**< GPTIMER7 */
#define CSL_INTC_EVENTID_GPTIMER8               (_CSL_INTC_EVENTID__INTC2START + 39)  /**< GPTIMER8 */
#define CSL_INTC_EVENTID_GPIO2                  (_CSL_INTC_EVENTID__INTC2START + 40)  /**< IRQ1_GPIO2 */
#define CSL_INTC_EVENTID_GPIO3                  (_CSL_INTC_EVENTID__INTC2START + 41)  /**< IRQ1_GPIO3 */
#define CSL_INTC_EVENTID_MMCSDIO2               (_CSL_INTC_EVENTID__INTC2START + 42)  /**< MMC/SDIO2 */
#define CSL_INTC_EVENTID_COMPACTFLASH           (_CSL_INTC_EVENTID__INTC2START + 43)  /**< CompactFlash */
#define CSL_INTC_EVENTID_COMMRX                 (_CSL_INTC_EVENTID__INTC2START + 44)  /**< COMMRX (emulation event) */
#define CSL_INTC_EVENTID_COMMTX                 (_CSL_INTC_EVENTID__INTC2START + 45)  /**< COMMTX (emulation event) */
#define CSL_INTC_EVENTID_PERIPHWAKEUP           (_CSL_INTC_EVENTID__INTC2START + 46)  /**< Peripheral wake up */
#define CSL_INTC_EVENTID_GPIO4                  (_CSL_INTC_EVENTID__INTC2START + 48)  /**< IRQ1_GPIO4 */
#define CSL_INTC_EVENTID_SPI                    (_CSL_INTC_EVENTID__INTC2START + 49)  /**< SPI */
#define CSL_INTC_EVENTID_CCPSTATUS              (_CSL_INTC_EVENTID__INTC2START + 50)  /**< CCPSTATUS */
#define CSL_INTC_EVENTID_CCPFIFONOTEMPTY        (_CSL_INTC_EVENTID__INTC2START + 51)  /**< CCP FIFONOTEMPTY */
#define CSL_INTC_EVENTID_CCTATTN                (_CSL_INTC_EVENTID__INTC2START + 52)  /**< CCP ATTN */
#define CSL_INTC_EVENTID_DMACH6                 (_CSL_INTC_EVENTID__INTC2START + 53)  /**< DMA Channel 6 */
#define CSL_INTC_EVENTID_DMACH7                 (_CSL_INTC_EVENTID__INTC2START + 54)  /**< DMA Channel 7 */
#define CSL_INTC_EVENTID_DMACH8                 (_CSL_INTC_EVENTID__INTC2START + 55)  /**< DMA Channel 8 */
#define CSL_INTC_EVENTID_DMACH9                 (_CSL_INTC_EVENTID__INTC2START + 56)  /**< DMA Channel 9 */
#define CSL_INTC_EVENTID_DMACH10                (_CSL_INTC_EVENTID__INTC2START + 57)  /**< DMA Channel 10 */
#define CSL_INTC_EVENTID_DMACH11                (_CSL_INTC_EVENTID__INTC2START + 58)  /**< DMA Channel 11 */
#define CSL_INTC_EVENTID_DMACH12                (_CSL_INTC_EVENTID__INTC2START + 59)  /**< DMA Channel 12 */
#define CSL_INTC_EVENTID_DMACH13                (_CSL_INTC_EVENTID__INTC2START + 60)  /**< DMA Channel 13 */
#define CSL_INTC_EVENTID_DMACH14                (_CSL_INTC_EVENTID__INTC2START + 61)  /**< DMA Channel 14 */
#define CSL_INTC_EVENTID_DMACH15                (_CSL_INTC_EVENTID__INTC2START + 62)  /**< DMA Channel 15 */
#define CSL_INTC_EVENTID_NANDFLASH              (_CSL_INTC_EVENTID__INTC2START + 63)  /**< NAND flash interrupt */
#define CSL_INTC_EVENTID_SSTCH0FIFOEMPTY        (_CSL_INTC_EVENTID__INTC2START + 65)  /**< SST FIFO empty (channel 0) */
#define CSL_INTC_EVENTID_SSRCH0OVERRUN          (_CSL_INTC_EVENTID__INTC2START + 67)  /**< SSR overrun (channel 0) */
#define CSL_INTC_EVENTID_SSTCH1FIFOEMPTY        (_CSL_INTC_EVENTID__INTC2START + 68)  /**< SST FIFO empty (channel 1) */
#define CSL_INTC_EVENTID_SSRCH1FIFOFULL         (_CSL_INTC_EVENTID__INTC2START + 69)  /**< SSR FIFO full (channel 1) */
#define CSL_INTC_EVENTID_SSRCH1OVERRUN          (_CSL_INTC_EVENTID__INTC2START + 70)  /**< SSR overrun (channel 1) */
#define CSL_INTC_EVENTID_SSTCH2FIFOEMPTY        (_CSL_INTC_EVENTID__INTC2START + 71)  /**< SST FIFO empty (channel 2) */
#define CSL_INTC_EVENTID_SSRCH2FIFOFULL         (_CSL_INTC_EVENTID__INTC2START + 72)  /**< SSR FIFO full (channel 2) */
#define CSL_INTC_EVENTID_SSRCH2OVERRUN          (_CSL_INTC_EVENTID__INTC2START + 73)  /**< SSR overrun (channel 2) */
#define CSL_INTC_EVENTID_SSTCH3FIFOEMPTY        (_CSL_INTC_EVENTID__INTC2START + 74)  /**< SST FIFO empty (channel 3) */
#define CSL_INTC_EVENTID_SSRCH3FIFOFULL         (_CSL_INTC_EVENTID__INTC2START + 75)  /**< SSR FIFO full (channel 3) */
#define CSL_INTC_EVENTID_SSRCH3OVERRUN          (_CSL_INTC_EVENTID__INTC2START + 76)  /**< SSR overrun (channel 3) */
#define CSL_INTC_EVENTID_SSTCH4FIFOEMPTY        (_CSL_INTC_EVENTID__INTC2START + 77)  /**< SST FIFO empty (channel 4) */
#define CSL_INTC_EVENTID_SSRCH4FIFOFULL         (_CSL_INTC_EVENTID__INTC2START + 78)  /**< SSR FIFO full (channel 4) */
#define CSL_INTC_EVENTID_SSRCH4OVERRUN          (_CSL_INTC_EVENTID__INTC2START + 79)  /**< SSR overrun (channel 4) */
#define CSL_INTC_EVENTID_SSTCH5FIFOEMPTY        (_CSL_INTC_EVENTID__INTC2START + 80)  /**< SST FIFO empty (channel 5) */
#define CSL_INTC_EVENTID_SSRCH5FIFOFULL         (_CSL_INTC_EVENTID__INTC2START + 81)  /**< SSR FIFO full (channel 5) */
#define CSL_INTC_EVENTID_SSRCH5OVERRUN          (_CSL_INTC_EVENTID__INTC2START + 82)  /**< SSR overrun (channel 5) */
#define CSL_INTC_EVENTID_SSTCH6FIFOEMPTY        (_CSL_INTC_EVENTID__INTC2START + 83)  /**< SST FIFO empty (channel 6) */
#define CSL_INTC_EVENTID_SSRCH6FIFOFULL         (_CSL_INTC_EVENTID__INTC2START + 84)  /**< SSR FIFO full (channel 6) */
#define CSL_INTC_EVENTID_SSRCH6OVERRUN          (_CSL_INTC_EVENTID__INTC2START + 85)  /**< SSR overrun (channel 6) */
#define CSL_INTC_EVENTID_SSTCH7FIFOEMPTY        (_CSL_INTC_EVENTID__INTC2START + 86)  /**< SST FIFO empty (channel 7) */
#define CSL_INTC_EVENTID_SSRCH7FIFOFULL         (_CSL_INTC_EVENTID__INTC2START + 87)  /**< SSR FIFO full (channel 7) */
#define CSL_INTC_EVENTID_SSRCH7OVERRUN          (_CSL_INTC_EVENTID__INTC2START + 88)  /**< SSR overrun (channel 7) */
#define CSL_INTC_EVENTID_SSRSIGNALERR           (_CSL_INTC_EVENTID__INTC2START + 89)  /**< SSR signaling error */
#define CSL_INTC_EVENTID_SSRCONTROLLER          (_CSL_INTC_EVENTID__INTC2START + 90)  /**< SSR controller interrupt */
#define CSL_INTC_EVENTID_SHA1MD5                (_CSL_INTC_EVENTID__INTC2START + 91)  /**< SHA-1/MD5 */
#define CSL_INTC_EVENTID_RNG                    (_CSL_INTC_EVENTID__INTC2START + 92)  /**< RNG */
#define CSL_INTC_EVENTID_RNGIDLE                (_CSL_INTC_EVENTID__INTC2START + 93)  /**< RNGIDLE */
#define CSL_INTC_EVENTID_VLYNQ                  (_CSL_INTC_EVENTID__INTC2START + 94)  /**< VLYNQ */
#define CSL_INTC_EVENTID_GDDLCH0                (_CSL_INTC_EVENTID__INTC2START + 95)  /**< GDD - Logical Channel 0 */
#define CSL_INTC_EVENTID_GDDLCH1                (_CSL_INTC_EVENTID__INTC2START + 96)  /**< GDD - Logical Channel 1 */
#define CSL_INTC_EVENTID_GDDLCH2                (_CSL_INTC_EVENTID__INTC2START + 97)  /**< GDD - Logical Channel 2 */
#define CSL_INTC_EVENTID_GDDLCH3                (_CSL_INTC_EVENTID__INTC2START + 98)  /**< GDD - Logical Channel 3 */
#define CSL_INTC_EVENTID_GDDLCH4                (_CSL_INTC_EVENTID__INTC2START + 99)  /**< GDD - Logical Channel 4 */
#define CSL_INTC_EVENTID_GDDLCH5                (_CSL_INTC_EVENTID__INTC2START + 100) /**< GDD - Logical Channel 5 */
#define CSL_INTC_EVENTID_GDDLCH6                (_CSL_INTC_EVENTID__INTC2START + 101) /**< GDD - Logical Channel 6 */
#define CSL_INTC_EVENTID_GDDLCH7                (_CSL_INTC_EVENTID__INTC2START + 102) /**< GDD - Logical Channel 7 */

#define _CSL_INTC_EVENTID__INTC2END             (_CSL_INTC_EVENTID__INTC2START + __CSL_INTC_EVENTID__INTC2CNT__ - 1)


#define _CSL_INTC_EVENTID__INTC0START           (_CSL_INTC_EVENTID__INTC2END + 1)

#define CSL_INTC_EVENTID_RESET                  (_CSL_INTC_EVENTID__INTC0START + 0)  /**< the RESET exception vector */
#define CSL_INTC_EVENTID_UNDEF                  (_CSL_INTC_EVENTID__INTC0START + 1)  /**< the UNDEF exception vector */
#define CSL_INTC_EVENTID_SWI                    (_CSL_INTC_EVENTID__INTC0START + 2)  /**< the SWI exception vector */
#define CSL_INTC_EVENTID_PREABT                 (_CSL_INTC_EVENTID__INTC0START + 3)  /**< the PREABT exception vector */
#define CSL_INTC_EVENTID_DATABT                 (_CSL_INTC_EVENTID__INTC0START + 4)  /**< the DATABT exception vector */
#define CSL_INTC_EVENTID_IRQ                    (_CSL_INTC_EVENTID__INTC0START + 6)  /**< the IRQ exception vector */
#define CSL_INTC_EVENTID_FIQ                    (_CSL_INTC_EVENTID__INTC0START + 7)  /**< the FIQ exception vector */

#define _CSL_INTC_EVENTID__INTC0END             (_CSL_INTC_EVENTID__INTC0START + __CSL_INTC_EVENTID__INTC0CNT__ - 1)


#endif  /* _SOC_H_ */