soc.h

dsp在音频处理中的运用

#define CSL_DSPMMU_1_REGS             (0xFFFED200u)

/** @brief Base address of USB Device Controller peripheral registers */
#define CSL_USBF_1_REGS             (0xFFFB4000u)

/** @brief Base address of USB Device Host peripheral registers */
#define CSL_USBHC_1_REGS            (0xFFFBA000u)

/** @brief Base address of USB OTG peripheral registers */
#define CSL_USBOTG_1_REGS           (0xFFFB0400)

/** @brief Base address of ARM2DSP1 mailbox peripheral data registers */
#define CSL_MBX_ARM2DSP1_DATA_REGS (0xFFFCF000u)

/** @brief Base address of ARM2DSP2 mailbox peripheral data registers */
#define CSL_MBX_ARM2DSP2_DATA_REGS (0xFFFCF024u)

/** @brief Base address of DSP2ARM1 mailbox peripheral data registers */
#define CSL_MBX_DSP2ARM1_DATA_REGS (0xFFFCF008u)

/** @brief Base address of DSP2ARM2 mailbox peripheral data registers */
#define CSL_MBX_DSP2ARM2_DATA_REGS (0xFFFCF010u)

/** @brief Base address of ARM2DSP1 mailbox peripheral flag registers */
#define CSL_MBX_ARM2DSP1_INTR_REGS (0xFFFCF018u)

/** @brief Base address of ARM2DSP2 mailbox peripheral flag registers */
#define CSL_MBX_ARM2DSP2_INTR_REGS (0xFFFCF02Cu)

/** @brief Base address of DSP2ARM1 mailbox peripheral flag registers */
#define CSL_MBX_DSP2ARM1_INTR_REGS (0xFFFCF01Cu)

/** @brief Base address of DSP2ARM2 mailbox peripheral flag registers */
#define CSL_MBX_DSP2ARM2_INTR_REGS (0xFFFCF020u)

/** @brief Base address of NAND Flash Controller(NFC) peripheral flag registers */
#define CSL_NFC_1_REGS              (0xFFFBCC00u)

/** @brief Base address of Compact Flash Controller(CFC) peripheral flag registers */
#define CSL_CFC_1_REGS              (0xFFFE2800u)

/** @brief Base address of MMC peripheral flag registers */
#define CSL_MMCSD_1_REGS              (0xFFFB7800u)

#define CSL_MMCSD_2_REGS              (0xFFFB7C00u)

/** @brief Base address of GPTIMER peripheral flag registers */
#define CSL_GPTIMER_1_REGS          (0xFFFB1400u)

#define CSL_GPTIMER_2_REGS          (0xFFFB1C00u)

#define CSL_GPTIMER_3_REGS          (0xFFFB2400u)

#define CSL_GPTIMER_4_REGS          (0xFFFB2C00u)

#define CSL_GPTIMER_5_REGS          (0xFFFB3400u)

#define CSL_GPTIMER_6_REGS          (0xFFFB3C00u)

#define CSL_GPTIMER_7_REGS          (0xFFFB7400u)

#define CSL_GPTIMER_8_REGS          (0xFFFBD400u)

/** @brief Base address of WDTimer peripheral flag registers */
#define CSL_WDT_1_REGS              (0xFFFEC800u)

/** @brief Base address of HECC peripheral flag registers */
#define CSL_HECC_1_REGS              (0xFFFBA800u)

/** @brief Base address of HECC peripheral flag registers */
#define CSL_HECC_2_REGS             (0xFFFBC000u)

/** @brief Base address of RTC peripheral flag registers */
#define CSL_RTC_1_REGS              (0xFFFB4800u)

/** @brief Base address of ADCC peripheral control registers */
#define CSL_ADCC_1_REGS             (0xFFFB6000u)

/** @brief Base address of GPIO peripheral registers */
#define CSL_GPIO_1_REGS             (0xFFFBE400)

#define CSL_GPIO_2_REGS             (0xFFFBEC00)

#define CSL_GPIO_3_REGS             (0xFFFBB400)

#define CSL_GPIO_4_REGS             (0xFFFBBC00)

/** @brief Base address of LCD Controller peripheral control registers */
#define CSL_LCDCTRL_1_REGS          (0xFFFEC000u)

/** @brief Base address of LPG peripheral control registers */
#define CSL_LEDPG_1_REGS          (0xFFFBD000u)

#define CSL_LEDPG_2_REGS          (0xFFFBD800u)

/** @brief Base address of PWL peripheral control registers */
#define CSL_PWL_1_REGS          (0xFFFB5800u)

/** @brief Base address of LCDCONV peripheral control registers */
#define CSL_LCDCONV_1_REGS          (0xFFFE3000)

/** @brief Base address of OSTIMER peripheral control registers */
#define CSL_OSTIMER_REGS          (0xFFFB9000)

/** @brief Base address of SOSSI peripheral control registers */
#define CSL_SOSSI_REGS          (0xFFFBAC00)

/** @brief Base address of CCP peripheral control registers */
#define CSL_CCP_1_REGS          (0xFFFBC800)

/** @brief Base address of UWIRE peripheral control registers */
#define CSL_UWIRE_REGS          (0xFFFB3000)

/** @brief Base address of SSR peripheral control registers */
#define CSL_SSR_1_REGS          (0x30000800)

/** @brief Base address of SST peripheral control registers */
#define CSL_SST_1_REGS          (0x30000000)

/** @brief Base address of CAMERA IF peripheral control registers */
#define CSL_CAM_1_REGS          (0xFFFB6800)

/** @brief Base address of PWT peripheral control registers */
#define CSL_PWT_1_REGS          (0xFFFB6000)

/** @brief Base address of HDQ1WIRE peripheral control registers */
#define CSL_HDQ1W_1_REGS          (0xFFFBC000)

/** @brief Base address of OCPT1 TC port registers */
#define CSL_OCPT1_1_REGS          (0xFFFECC00)

/** @brief Base address of SPL registers */
#define CSL_SPL_1_REGS            ( 0xFFFE1040u)

/** @brief Base address of SPI registers */
#define CSL_SPI_1_REGS            ( 0xFFFB0C00u)


/**************************************************************************\
* Peripheral Instance enumeration
\**************************************************************************/
/** @brief Peripheral Instance of DPLL */
#define    CSL_DPLL_1 	 (0)   /** Instance 1 of DPLL */

/** @brief Peripheral Instance for ULPD */
#define    CSL_ULPD   (0)      /** Instance 1 of ULPD */


/** @brief Peripheral Instances of UART */
#define CSL_UART_1    (0)      /** Instance 1 of UART */

#define CSL_UART_2    (1)      /** Instance 2 of UART */

#define CSL_UART_3    (2)      /** Instance 3 of UART */

/** @brief Peripheral Instance enumeration for MIBSPI  */
#define CSL_MIBSPI_1          (0) /** Instance 1 of MIBSPI  */

#define CSL_MIBSPI_2          (1) /** Instance 2 of MIBSPI  */

#define CSL_MIBSPI_3          (2) /** Instance 3 of MIBSPI  */

#define CSL_MIBSPI_4          (3) /** Instance 4 of MIBSPI  */

#define CSL_MIBSPI_5          (4) /** Instance 5 of MIBSPI  */
													   

/** @brief Peripheral Instances of  IRDA   */
/** This is part of Instance 1 of UART */
#define CSL_IRDA_1 	  (0)     /** Instance 1 of IRDA  */

/** Instance 3 of IRDA. (This is part of Instance 3 of UART).
	There is no Instance 2 of IRDA, as Instance 2 of UART
	doesn't support IRDA
 */
#define CSL_IRDA_3 	  (1)     /** Instance 3 of IRDA.  */


/** @brief Peripheral Instance of EMIFF */
#define CSL_EMIFF    (0)     /** Instance 1 of EMIFF   */

/** @brief Peripheral Instance of EMIFS */
#define CSL_EMIFS     (0)  	/** Instance of EMIFS      */

/** @brief Peripheral Instance of SSW */
#define CSL_SSW 	  (0)  /** Instance of SSW        */

/** @brief Peripheral Instance of DMA */
#define CSL_DMA	      (0) /** Instance of DMA      */

/** @brief Peripheral Instance of I2C */
#define CSL_I2C_1    (0)      /** Instance 1 of I2C */

/** @brief Peripheral Instances of TIMER */
#define CSL_TIMER_1         (0)  /** Instance 1 of TIMER  */

#define CSL_TIMER_2         (1)  /** Instance 2 of TIMER  */

#define CSL_TIMER_3         (2) /** Instance 3 of TIMER  */

/** @brief Peripheral Instance of MCBSP */
#define CSL_MCBSP_2         (0)  /** Instance 2 of MCBSP  */

/** @brief Peripheral Instance of CLKRST */
#define CSL_CLKRST          (0) /** Instance of CLKRST  */

/** @brief Peripheral Instance of DSPMMU */
#define CSL_DSPMMU      (0)   /** Instance of DSPMMU  */

/** @brief Peripheral Instance of ARM MMU */
#define CSL_MMU         (0)     /** Instance of MMU  */

#define    CSL_VLYNQ   (0)      /** Instance 1 of VLYNQ */

/** @brief Peripheral Instance of ARM NFC */
#define CSL_NFC         (0)     /** Instance of NFC  */

/** @brief Peripheral Instance of ARM CFC */
#define CSL_CFC         (0)     /** Instance of CFC  */

/** @brief Peripheral Instance of USB Device Controller  */
#define CSL_USBF        (0) /** Instance of USBF  */

/** @brief Peripheral Instance of USB Host Controller  */
#define CSL_USBHC        (0) /** Instance of USBHC  */

/** @brief Peripheral Instance of USB OTG */
#define CSL_USBOTG       (0) /** Instance of USBOTG  */

/** @brief Peripheral Instances of Mailbox  */
#define    CSL_MBX_ARM2DSP1       (0)  /** Instance 1 of ARM to DSP Mailbox */

#define    CSL_MBX_ARM2DSP2       (1)  /** Instance 2 of ARM to DSP Mailbox */

#define    CSL_MBX_DSP2ARM1       (2)  /** Instance 1 of DSP to ARM Mailbox */

#define    CSL_MBX_DSP2ARM2       (3)  /** Instance 2 of DSP to ARM Mailbox */

/** @brief Peripheral Instance of Cache  */
#define CSL_CACHE          (0)  /** Instance of CACHE  */

/** @brief Peripheral Instances of MMC  */
#define CSL_MMCSD_1          (0)  /** Instance1 of MMC  */

#define CSL_MMCSD_2          (1)  /** Instance2 of MMC  */

/** @brief Peripheral Instance of ATA Primary */											
#define CSL_ATA_PRIMARY	1

/** @brief Peripheral Instance of ATA Secondary */
#define CSL_ATA_SECONDARY	2


/** @brief Peripheral Instances of GPTIMER  */
#define CSL_GPTIMER_1      (0)  /** Instance1 of GPTIMER  */

#define CSL_GPTIMER_2      (1)  /** Instance2 of GPTIMER  */

#define CSL_GPTIMER_3      (2)  /** Instance3 of GPTIMER  */