soc.h

dsp在音频处理中的运用

#ifndef _SOC_H_
#define _SOC_H_

/**************************************************************************\
* 5912 ARM soc file
\**************************************************************************/

#include <cslr.h>

/**************************************************************************\
* Peripheral Instance count
\**************************************************************************/
/** @brief Number of INTC0 instances */
#define CSL_INTC0_CNT                 1

/** @brief Number of INTC1 instances */
#define CSL_INTC1_CNT                 1

/** @brief Number of INTC2 instances */
#define CSL_INTC2_CNT                 1

/** @brief Number of DPLL instances */
#define CSL_DPLL_CNT                  1

/** @brief Number of ULPD instances */
#define CSL_ULPD_CNT                  1

/** @brief Number of UART instances */
#define CSL_UART_CNT                  3

/** @brief Number of IRDA instances */
#define CSL_IRDA_CNT                  2

/** @brief Number of EMIFF instances */
#define CSL_EMIFF_CNT                 1

/** @brief Number of EMIFS instances */
#define CSL_EMIFS_CNT                 1

/** @brief Number of Static Switch(SSW) instances */
#define CSL_SSW_CNT                   1

/** @brief Number of DMA instances */
#define CSL_DMA_CNT                   1

/** @brief Number of I2C instances */
#define CSL_I2C_CNT                   1

/** @brief Number of TIMER instances */
#define CSL_TIMER_CNT                 3

/** @brief Number of MIBSPI instances */
#define CSL_MIBSPI_CNT                5


/** @brief Number of MCBSP instances */
#define CSL_MCBSP_CNT                 1

/** @brief Number of CLKRST instances */
#define CSL_CLKRST_CNT                 1

/** @brief Number of DSPMMU instances */
#define CSL_DSPMMU_CNT                 1

/** @brief Number of MMU instances */
#define CSL_MMU_CNT                    1

/** @brief Number of USB Device Controller instances */
#define CSL_USBF_CNT                 1

/** @brief Number of USB Host Controller instances */
#define CSL_USBHC_CNT               1

/** @brief Number of MBX instances */
#define CSL_MBX_CNT      	    4

/** @brief Number of USB OTG instances */
#define CSL_USBOTG_CNT               1

/** @brief Number of NAND Flash Controller instances */
#define CSL_NFC_CNT               1

/** @brief Number of VLYNQ instances */
#define CSL_VLYNQ_CNT                   1 


/** @brief Number of MMC instances */
#define CSL_MMCSD_CNT               2

/** @brief Number of GPTIMER instances */
#define CSL_GPTIMER_CNT               8

/** @brief Number of WDT instances */
#define CSL_WDT_CNT               1

/** @brief Number of SPL instances */
#define CSL_ATA_CNT                   1


/** @brief Number of HECC instances */
#define CSL_HECC_CNT               2

/** @brief Number of RTC instances */
#define CSL_RTC_CNT               1

/** @brief Number of GPIO instances */
#define CSL_GPIO_CNT               4

/** @brief Number of ADCC instances */
#define CSL_ADCC_CNT                 1

/** @brief Number of CFC instances */
#define CSL_CFC_CNT                 1

/** @brief Number of LCD Controller instances */
#define CSL_LCDCTRL_CNT                 1

/** @brief Number of LPG instances */
#define CSL_LEDPG_CNT                 2

/** @brief Number of PWL instances */
#define CSL_PWL_CNT                 1

/** @brief Number of LCDCONV instances */
#define CSL_LCDCONV_CNT                 1

/** @brief Number of OSTIMER instances */
#define CSL_OSTIMER_CNT                 1

/** @brief Number of SOSSI instances */
#define CSL_SOSSI_CNT                 1

/** @brief Number of CCP instances */
#define CSL_CCP_CNT                 1

/** @brief Number of UWIRE instances */
#define CSL_UWIRE_CNT                 1

/** @brief Number of SSR instances */
#define CSL_SSR_CNT                 1

/** @brief Number of SST instances */
#define CSL_SST_CNT                 1

/** @brief Number of CAMERA IF instances */
#define CSL_CAM_CNT                 1

/** @brief Number of PWT instances */
#define CSL_PWT_CNT                 1

/** @brief Number of HDQ1WIRE instances */
#define CSL_HDQ1W_CNT                 1

/** @brief Number of OCPT1 instances */
#define CSL_OCPT1_CNT                 1

/** @brief Number of SPL instances */
#define CSL_SPL_CNT                 1

/** @brief Number of SPI instances */
#define CSL_SPI_CNT                 1


/**************************************************************************\
* Channel Instance count
\**************************************************************************/
/** @brief Number of Generic Channel instances */
#define CSL_DMA_CHA_CNT              16

/** @brief Number of LCD Channel instances */
#define CSL_DMA_LCD_CHA_CNT          1


/**************************************************************************\
* Peripheral Base Address
\**************************************************************************/

/** @brief Base address of INTC2 peripheral registers */
#define CSL_INTC1_0_REGS            (0xFFFECB00u)

/** @brief Base address of INTC2 peripheral registers (Alternate symbol) */
#define CSL_INTC1_REGS              (0xFFFECB00u)

/** @brief Base address of INTC2 peripheral registers */
#define CSL_INTC2_0_REGS            (0xFFFE0000u)

/** @brief Base address of INTC2 peripheral registers (Alternate symbol) */
#define CSL_INTC2_REGS              (0xFFFE0000u)

/** @brief Base address of MIBSPI1 peripheral registers */
#define CSL_MIBSPI_1_REGS           (0xFFFB5000u)

#define CSL_MIBSPI_2_REGS           (0xFFFB6800u)

#define CSL_MIBSPI_3_REGS           (0xFFFB8800u)

#define CSL_MIBSPI_4_REGS           (0xFFFB9000u)

#define CSL_MIBSPI_5_REGS           (0xFFFBA000u)

/** @brief Base address of ATA registers */
#define CSL_ATA_0_REGS            ( 0x30042000u)
													 

/** @brief Base address of DPLL peripheral registers */
#define CSL_DPLL_1_REGS             (0xFFFECF00u)

/** @brief Base address of ULPD peripheral registers */
#define CSL_ULPD_1_REGS             (0xFFFE0800u)

/** @brief Base address of UART1 peripheral registers */
#define CSL_UART_1_REGS             (0xFFFB0000u)

/** @brief Base address of UART2 peripheral registers */
#define CSL_UART_2_REGS             (0xFFFB0800u)

/** @brief Base address of UART3 peripheral registers */
#define CSL_UART_3_REGS             (0xFFFB9800u)

/** @brief Base address of VLYNQ registers */
#define CSL_VLYNQ_1_REGS	    ( 0x30002000u) 

/** @brief Base address of IRDA1 peripheral registers */
#define CSL_IRDA_1_REGS             (CSL_UART_1_REGS)

/** @brief Base address of IRDA3 peripheral registers */
#define CSL_IRDA_3_REGS             (CSL_UART_3_REGS)

/** @brief Base address of EMIFF peripheral registers */
#define CSL_EMIFF_1_REGS            (0xFFFECC00u)

/** @brief Base address of EMIFS peripheral registers */
#define CSL_EMIFS_1_REGS            (0xFFFECC00u)

/** @brief Base address of Static Switch(SSW) peripheral registers */
#define CSL_SSW_1_REGS              (0xFFFBC800u)

/** @brief Base address of DMA peripheral registers */
#define CSL_DMA_1_REGS              (0xFFFED800u)

/** @brief Base address of I2C peripheral registers */
#define CSL_I2C_1_REGS              (0xFFFB3800u)

/** @brief Base address of TIMER0 peripheral registers */
#define CSL_TIMER_1_REGS            (0xFFFEC500u)

/** @brief Base address of TIMER1 peripheral registers */
#define CSL_TIMER_2_REGS            (0xFFFEC600u)

/** @brief Base address of TIMER2 peripheral registers */
#define CSL_TIMER_3_REGS            (0xFFFEC700u)

/** @brief Base address of MCBSP2 peripheral registers */
#define CSL_MCBSP_2_REGS             (0xFFFB1000u)

/** @brief Base address of CLKRST peripheral registers */
#define CSL_CLKRST_1_REGS             (0xFFFECE00u)

/** @brief Base address of DSPMMU peripheral registers */