cslr_uart.h

来自「dsp在音频处理中的运用」· C头文件代码 · 共 716 行 · 第 1/2 页
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#define CSL_UART_LSR_TX_SR_E_SHIFT       (0x00000006u)#define CSL_UART_LSR_TX_SR_E_RESETVAL    (0x00000001u)#define CSL_UART_LSR_TX_FIFO_E_MASK      (0x00000020u)#define CSL_UART_LSR_TX_FIFO_E_SHIFT     (0x00000005u)#define CSL_UART_LSR_TX_FIFO_E_RESETVAL  (0x00000001u)#define CSL_UART_LSR_RX_BI_MASK          (0x00000010u)#define CSL_UART_LSR_RX_BI_SHIFT         (0x00000004u)#define CSL_UART_LSR_RX_BI_RESETVAL      (0x00000000u)#define CSL_UART_LSR_RX_FE_MASK          (0x00000008u)#define CSL_UART_LSR_RX_FE_SHIFT         (0x00000003u)#define CSL_UART_LSR_RX_FE_RESETVAL      (0x00000000u)#define CSL_UART_LSR_RX_PE_MASK          (0x00000004u)#define CSL_UART_LSR_RX_PE_SHIFT         (0x00000002u)#define CSL_UART_LSR_RX_PE_RESETVAL      (0x00000000u)#define CSL_UART_LSR_RX_OE_MASK          (0x00000002u)#define CSL_UART_LSR_RX_OE_SHIFT         (0x00000001u)#define CSL_UART_LSR_RX_OE_RESETVAL      (0x00000000u)#define CSL_UART_LSR_RX_FIFO_E_MASK      (0x00000001u)#define CSL_UART_LSR_RX_FIFO_E_SHIFT     (0x00000000u)#define CSL_UART_LSR_RX_FIFO_E_RESETVAL  (0x00000000u)#define CSL_UART_LSR_RESETVAL            (0x00000060u)/* XON2 */#define CSL_UART_XON2_XON_WORD2_MASK     (0x000000FFu)#define CSL_UART_XON2_XON_WORD2_SHIFT    (0x00000000u)#define CSL_UART_XON2_XON_WORD2_RESETVAL (0x00000000u)#define CSL_UART_XON2_RESETVAL           (0x00000000u)/* MSR_TCR_XOFF1 */#define CSL_UART_MSR_TCR_XOFF1_MSR_TCR_XOFF1_MASK (0x000000FFu)#define CSL_UART_MSR_TCR_XOFF1_MSR_TCR_XOFF1_SHIFT (0x00000000u)#define CSL_UART_MSR_TCR_XOFF1_MSR_TCR_XOFF1_RESETVAL (0x00000000u)#define CSL_UART_MSR_TCR_XOFF1_RESETVAL  (0x00000000u)/* MSR */#define CSL_UART_MSR_NCD_STS_MASK        (0x00000080u)#define CSL_UART_MSR_NCD_STS_SHIFT       (0x00000007u)#define CSL_UART_MSR_NCD_STS_RESETVAL    (0x00000000u)#define CSL_UART_MSR_NRI_STS_MASK        (0x00000040u)#define CSL_UART_MSR_NRI_STS_SHIFT       (0x00000006u)#define CSL_UART_MSR_NRI_STS_RESETVAL    (0x00000000u)#define CSL_UART_MSR_NDSR_STS_MASK       (0x00000020u)#define CSL_UART_MSR_NDSR_STS_SHIFT      (0x00000005u)#define CSL_UART_MSR_NDSR_STS_RESETVAL   (0x00000000u)#define CSL_UART_MSR_NCTS_STS_MASK       (0x00000010u)#define CSL_UART_MSR_NCTS_STS_SHIFT      (0x00000004u)#define CSL_UART_MSR_NCTS_STS_RESETVAL   (0x00000000u)#define CSL_UART_MSR_DCD_STS_MASK        (0x00000008u)#define CSL_UART_MSR_DCD_STS_SHIFT       (0x00000003u)#define CSL_UART_MSR_DCD_STS_RESETVAL    (0x00000000u)#define CSL_UART_MSR_RI_STS_MASK         (0x00000004u)#define CSL_UART_MSR_RI_STS_SHIFT        (0x00000002u)#define CSL_UART_MSR_RI_STS_RESETVAL     (0x00000000u)#define CSL_UART_MSR_DSR_STS_MASK        (0x00000002u)#define CSL_UART_MSR_DSR_STS_SHIFT       (0x00000001u)#define CSL_UART_MSR_DSR_STS_RESETVAL    (0x00000000u)#define CSL_UART_MSR_CTS_STS_MASK        (0x00000001u)#define CSL_UART_MSR_CTS_STS_SHIFT       (0x00000000u)#define CSL_UART_MSR_CTS_STS_RESETVAL    (0x00000000u)#define CSL_UART_MSR_RESETVAL            (0x00000000u)/* XOFF1 */#define CSL_UART_XOFF1_XOFF_WORD1_MASK   (0x000000FFu)#define CSL_UART_XOFF1_XOFF_WORD1_SHIFT  (0x00000000u)#define CSL_UART_XOFF1_XOFF_WORD1_RESETVAL (0x00000000u)#define CSL_UART_XOFF1_RESETVAL          (0x00000000u)/* TCR */#define CSL_UART_TCR_RX_FIFO_TRIG_START_MASK (0x000000F0u)#define CSL_UART_TCR_RX_FIFO_TRIG_START_SHIFT (0x00000004u)#define CSL_UART_TCR_RX_FIFO_TRIG_START_RESETVAL (0x00000000u)#define CSL_UART_TCR_RX_FIFO_TRIG_HALT_MASK (0x0000000Fu)#define CSL_UART_TCR_RX_FIFO_TRIG_HALT_SHIFT (0x00000000u)#define CSL_UART_TCR_RX_FIFO_TRIG_HALT_RESETVAL (0x0000000Fu)#define CSL_UART_TCR_RESETVAL            (0x0000000Fu)/* SPR_TLR_XOFF2 */#define CSL_UART_SPR_TLR_XOFF2_SPR_TLR_XOFF2_MASK (0x000000FFu)#define CSL_UART_SPR_TLR_XOFF2_SPR_TLR_XOFF2_SHIFT (0x00000000u)#define CSL_UART_SPR_TLR_XOFF2_SPR_TLR_XOFF2_RESETVAL (0x00000000u)#define CSL_UART_SPR_TLR_XOFF2_RESETVAL  (0x00000000u)/* XOFF2 */#define CSL_UART_XOFF2_XOFF_WORD2_MASK   (0x000000FFu)#define CSL_UART_XOFF2_XOFF_WORD2_SHIFT  (0x00000000u)#define CSL_UART_XOFF2_XOFF_WORD2_RESETVAL (0x00000000u)#define CSL_UART_XOFF2_RESETVAL          (0x00000000u)/* SPR */#define CSL_UART_SPR_SPR_WORD_MASK       (0x000000FFu)#define CSL_UART_SPR_SPR_WORD_SHIFT      (0x00000000u)#define CSL_UART_SPR_SPR_WORD_RESETVAL   (0x00000000u)#define CSL_UART_SPR_RESETVAL            (0x00000000u)/* TLR */#define CSL_UART_TLR_RX_FIFO_TRIG_DMA_MASK (0x000000F0u)#define CSL_UART_TLR_RX_FIFO_TRIG_DMA_SHIFT (0x00000004u)#define CSL_UART_TLR_RX_FIFO_TRIG_DMA_RESETVAL (0x00000000u)#define CSL_UART_TLR_TX_FIFO_TRIG_DMA_MASK (0x0000000Fu)#define CSL_UART_TLR_TX_FIFO_TRIG_DMA_SHIFT (0x00000000u)#define CSL_UART_TLR_TX_FIFO_TRIG_DMA_RESETVAL (0x00000000u)#define CSL_UART_TLR_RESETVAL            (0x00000000u)/* MDR1 */#define CSL_UART_MDR1_FRAME_END_MODE_MASK (0x00000080u)#define CSL_UART_MDR1_FRAME_END_MODE_SHIFT (0x00000007u)#define CSL_UART_MDR1_FRAME_END_MODE_RESETVAL (0x00000000u)#define CSL_UART_MDR1_FRAME_END_MODE_FRM_LEN (0x00000000u)#define CSL_UART_MDR1_FRAME_END_MODE_EOT (0x00000001u)#define CSL_UART_MDR1_SIP_MODE_MASK      (0x00000040u)#define CSL_UART_MDR1_SIP_MODE_SHIFT     (0x00000006u)#define CSL_UART_MDR1_SIP_MODE_RESETVAL  (0x00000000u)#define CSL_UART_MDR1_SIP_MODE_MANUAL    (0x00000000u)#define CSL_UART_MDR1_SIP_MODE_AUTOMATIC (0x00000001u)#define CSL_UART_MDR1_SCT_MASK           (0x00000020u)#define CSL_UART_MDR1_SCT_SHIFT          (0x00000005u)#define CSL_UART_MDR1_SCT_RESETVAL       (0x00000000u)#define CSL_UART_MDR1_SCT_DISABLE        (0x00000000u)#define CSL_UART_MDR1_SCT_ENABLE         (0x00000001u)#define CSL_UART_MDR1_SET_TXIR_MASK      (0x00000010u)#define CSL_UART_MDR1_SET_TXIR_SHIFT     (0x00000004u)#define CSL_UART_MDR1_SET_TXIR_RESETVAL  (0x00000000u)#define CSL_UART_MDR1_SET_TXIR_NONE      (0x00000000u)#define CSL_UART_MDR1_SET_TXIR_HIGH      (0x00000001u)#define CSL_UART_MDR1_IR_SLEEP_MASK      (0x00000008u)#define CSL_UART_MDR1_IR_SLEEP_SHIFT     (0x00000003u)#define CSL_UART_MDR1_IR_SLEEP_RESETVAL  (0x00000000u)#define CSL_UART_MDR1_IR_SLEEP_DISABLE   (0x00000000u)#define CSL_UART_MDR1_IR_SLEEP_ENABLE    (0x00000001u)#define CSL_UART_MDR1_MODE_SELECT_MASK   (0x00000007u)#define CSL_UART_MDR1_MODE_SELECT_SHIFT  (0x00000000u)#define CSL_UART_MDR1_MODE_SELECT_RESETVAL (0x00000007u)#define CSL_UART_MDR1_MODE_SELECT_16X    (0x00000000u)#define CSL_UART_MDR1_MODE_SELECT_SIR    (0x00000001u)#define CSL_UART_MDR1_MODE_SELECT_16XAUTOBAUD (0x00000002u)#define CSL_UART_MDR1_MODE_SELECT_13X    (0x00000003u)#define CSL_UART_MDR1_MODE_SELECT_MIR    (0x00000004u)#define CSL_UART_MDR1_MODE_SELECT_FIR    (0x00000005u)#define CSL_UART_MDR1_MODE_SELECT_DISABLE (0x00000007u)#define CSL_UART_MDR1_RESETVAL           (0x00000007u)/* UASR */#define CSL_UART_UASR_PARITY_TYPE_MASK   (0x000000C0u)#define CSL_UART_UASR_PARITY_TYPE_SHIFT  (0x00000006u)#define CSL_UART_UASR_PARITY_TYPE_RESETVAL (0x00000000u)#define CSL_UART_UASR_PARITY_TYPE_NONE   (0x00000000u)#define CSL_UART_UASR_PARITY_TYPE_SPACE  (0x00000001u)#define CSL_UART_UASR_PARITY_TYPE_EVEN   (0x00000002u)#define CSL_UART_UASR_PARITY_TYPE_ODD    (0x00000003u)#define CSL_UART_UASR_BIT_BY_CHAR_MASK   (0x00000020u)#define CSL_UART_UASR_BIT_BY_CHAR_SHIFT  (0x00000005u)#define CSL_UART_UASR_BIT_BY_CHAR_RESETVAL (0x00000000u)#define CSL_UART_UASR_BIT_BY_CHAR_7      (0x00000000u)#define CSL_UART_UASR_BIT_BY_CHAR_8      (0x00000001u)#define CSL_UART_UASR_SPEED_MASK         (0x0000001Fu)#define CSL_UART_UASR_SPEED_SHIFT        (0x00000000u)#define CSL_UART_UASR_SPEED_RESETVAL     (0x00000000u)#define CSL_UART_UASR_SPEED_NONE         (0x00000000u)#define CSL_UART_UASR_SPEED_1152         (0x00000001u)#define CSL_UART_UASR_SPEED_576          (0x00000002u)#define CSL_UART_UASR_SPEED_384          (0x00000003u)#define CSL_UART_UASR_SPEED_288          (0x00000004u)#define CSL_UART_UASR_SPEED_192          (0x00000005u)#define CSL_UART_UASR_SPEED_144          (0x00000006u)#define CSL_UART_UASR_SPEED_096          (0x00000007u)#define CSL_UART_UASR_SPEED_048          (0x00000008u)#define CSL_UART_UASR_SPEED_024          (0x00000009u)#define CSL_UART_UASR_SPEED_012          (0x0000000Au)#define CSL_UART_UASR_RESETVAL           (0x00000000u)/* SCR */#define CSL_UART_SCR_RX_TRIG_GRANU1_MASK (0x00000080u)#define CSL_UART_SCR_RX_TRIG_GRANU1_SHIFT (0x00000007u)#define CSL_UART_SCR_RX_TRIG_GRANU1_RESETVAL (0x00000000u)#define CSL_UART_SCR_RX_TRIG_GRANU1_DISABLE (0x00000000u)#define CSL_UART_SCR_RX_TRIG_GRANU1_ENABLE (0x00000001u)#define CSL_UART_SCR_TX_TRIG_GRANU1_MASK (0x00000040u)#define CSL_UART_SCR_TX_TRIG_GRANU1_SHIFT (0x00000006u)#define CSL_UART_SCR_TX_TRIG_GRANU1_RESETVAL (0x00000000u)#define CSL_UART_SCR_TX_TRIG_GRANU1_DISABLE (0x00000000u)#define CSL_UART_SCR_TX_TRIG_GRANU1_ENABLE (0x00000001u)#define CSL_UART_SCR_DSR_IT_MASK         (0x00000020u)#define CSL_UART_SCR_DSR_IT_SHIFT        (0x00000005u)#define CSL_UART_SCR_DSR_IT_RESETVAL     (0x00000000u)#define CSL_UART_SCR_DSR_IT_DISABLE      (0x00000000u)#define CSL_UART_SCR_DSR_IT_ENABLE       (0x00000001u)#define CSL_UART_SCR_RX_CTS_DSR_WAKE_UP_ENABLE_MASK (0x00000010u)#define CSL_UART_SCR_RX_CTS_DSR_WAKE_UP_ENABLE_SHIFT (0x00000004u)#define CSL_UART_SCR_RX_CTS_DSR_WAKE_UP_ENABLE_RESETVAL (0x00000000u)#define CSL_UART_SCR_RX_CTS_DSR_WAKE_UP_ENABLE_DISABLE (0x00000000u)#define CSL_UART_SCR_RX_CTS_DSR_WAKE_UP_ENABLE_ENABLE (0x00000001u)#define CSL_UART_SCR_TX_EMPTY_CTL_IT_MASK (0x00000008u)#define CSL_UART_SCR_TX_EMPTY_CTL_IT_SHIFT (0x00000003u)#define CSL_UART_SCR_TX_EMPTY_CTL_IT_RESETVAL (0x00000000u)#define CSL_UART_SCR_TX_EMPTY_CTL_IT_DISABLE (0x00000000u)#define CSL_UART_SCR_TX_EMPTY_CTL_IT_ENABLE (0x00000001u)#define CSL_UART_SCR_DMA_MODE_2_MASK     (0x00000006u)#define CSL_UART_SCR_DMA_MODE_2_SHIFT    (0x00000001u)#define CSL_UART_SCR_DMA_MODE_2_RESETVAL (0x00000000u)#define CSL_UART_SCR_DMA_MODE_2_00       (0x00000000u)#define CSL_UART_SCR_DMA_MODE_2_01       (0x00000001u)#define CSL_UART_SCR_DMA_MODE_2_02       (0x00000002u)#define CSL_UART_SCR_DMA_MODE_2_03       (0x00000003u)#define CSL_UART_SCR_DMA_MODE_CTL_MASK   (0x00000001u)#define CSL_UART_SCR_DMA_MODE_CTL_SHIFT  (0x00000000u)#define CSL_UART_SCR_DMA_MODE_CTL_RESETVAL (0x00000000u)#define CSL_UART_SCR_DMA_MODE_CTL_DISABLE (0x00000000u)#define CSL_UART_SCR_DMA_MODE_CTL_ENABLE (0x00000001u)#define CSL_UART_SCR_RESETVAL            (0x00000000u)/* SSR */#define CSL_UART_SSR_RX_CTS_DSR_WAKE_UP_STS_MASK (0x00000002u)#define CSL_UART_SSR_RX_CTS_DSR_WAKE_UP_STS_SHIFT (0x00000001u)#define CSL_UART_SSR_RX_CTS_DSR_WAKE_UP_STS_RESETVAL (0x00000000u)#define CSL_UART_SSR_TX_FIFO_FULL_MASK   (0x00000001u)#define CSL_UART_SSR_TX_FIFO_FULL_SHIFT  (0x00000000u)#define CSL_UART_SSR_TX_FIFO_FULL_RESETVAL (0x00000000u)#define CSL_UART_SSR_RESETVAL            (0x00000000u)/* MVR */#define CSL_UART_MVR_MAJOR_REV_MASK      (0x000000F0u)#define CSL_UART_MVR_MAJOR_REV_SHIFT     (0x00000004u)#define CSL_UART_MVR_MAJOR_REV_RESETVAL  (0x00000001u)#define CSL_UART_MVR_MINOR_REV_MASK      (0x0000000Fu)#define CSL_UART_MVR_MINOR_REV_SHIFT     (0x00000000u)#define CSL_UART_MVR_MINOR_REV_RESETVAL  (0x00000001u)#define CSL_UART_MVR_RESETVAL            (0x00000011u)/* SYSC */#define CSL_UART_SYSC_IDLEMODE_MASK      (0x00000018u)#define CSL_UART_SYSC_IDLEMODE_SHIFT     (0x00000003u)#define CSL_UART_SYSC_IDLEMODE_RESETVAL  (0x00000000u)#define CSL_UART_SYSC_IDLEMODE_FORCE     (0x00000000u)#define CSL_UART_SYSC_IDLEMODE_NONE      (0x00000001u)#define CSL_UART_SYSC_IDLEMODE_SMART     (0x00000002u)#define CSL_UART_SYSC_ENAWAKEUP_MASK     (0x00000004u)#define CSL_UART_SYSC_ENAWAKEUP_SHIFT    (0x00000002u)#define CSL_UART_SYSC_ENAWAKEUP_RESETVAL (0x00000000u)#define CSL_UART_SYSC_ENAWAKEUP_DISABLE  (0x00000000u)#define CSL_UART_SYSC_ENAWAKEUP_ENABLE   (0x00000001u)#define CSL_UART_SYSC_SOFTRESET_MASK     (0x00000002u)#define CSL_UART_SYSC_SOFTRESET_SHIFT    (0x00000001u)#define CSL_UART_SYSC_SOFTRESET_RESETVAL (0x00000000u)#define CSL_UART_SYSC_SOFTRESET_DISABLE  (0x00000000u)#define CSL_UART_SYSC_SOFTRESET_ENABLE   (0x00000001u)#define CSL_UART_SYSC_AUTOIDLE_MASK      (0x00000001u)#define CSL_UART_SYSC_AUTOIDLE_SHIFT     (0x00000000u)#define CSL_UART_SYSC_AUTOIDLE_RESETVAL  (0x00000000u)#define CSL_UART_SYSC_AUTOIDLE_CLKRUN    (0x00000000u)#define CSL_UART_SYSC_AUTOIDLE_AUTO_OCP  (0x00000001u)#define CSL_UART_SYSC_RESETVAL           (0x00000000u)/* SYSS */#define CSL_UART_SYSS_RESETDONE_MASK     (0x00000001u)#define CSL_UART_SYSS_RESETDONE_SHIFT    (0x00000000u)#define CSL_UART_SYSS_RESETDONE_RESETVAL (0x00000000u)#define CSL_UART_SYSS_RESETVAL           (0x00000000u)/* WER */#define CSL_UART_WER_RLS_MASK            (0x00000040u)#define CSL_UART_WER_RLS_SHIFT           (0x00000006u)#define CSL_UART_WER_RLS_RESETVAL        (0x00000001u)#define CSL_UART_WER_RHR_MASK            (0x00000020u)#define CSL_UART_WER_RHR_SHIFT           (0x00000005u)#define CSL_UART_WER_RHR_RESETVAL        (0x00000001u)#define CSL_UART_WER_RXIR_MASK           (0x00000010u)#define CSL_UART_WER_RXIR_SHIFT          (0x00000004u)#define CSL_UART_WER_RXIR_RESETVAL       (0x00000001u)#define CSL_UART_WER_DCD_MASK            (0x00000008u)#define CSL_UART_WER_DCD_SHIFT           (0x00000003u)#define CSL_UART_WER_DCD_RESETVAL        (0x00000001u)#define CSL_UART_WER_RI_MASK             (0x00000004u)#define CSL_UART_WER_RI_SHIFT            (0x00000002u)#define CSL_UART_WER_RI_RESETVAL         (0x00000001u)#define CSL_UART_WER_DSR_MASK            (0x00000002u)#define CSL_UART_WER_DSR_SHIFT           (0x00000001u)#define CSL_UART_WER_DSR_RESETVAL        (0x00000001u)#define CSL_UART_WER_CTS_MASK            (0x00000001u)#define CSL_UART_WER_CTS_SHIFT           (0x00000000u)#define CSL_UART_WER_CTS_RESETVAL        (0x00000001u)#define CSL_UART_WER_RESETVAL           (0x0000007Fu)#endif
cslr_uart.h - 源码说明

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