cslr_uart.h

来自「dsp在音频处理中的运用」· C头文件代码 · 共 716 行 · 第 1/2 页
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#ifndef _CSLR_UART_001_H_#define _CSLR_UART_001_H_#include <cslr.h>#include <tistdtypes.h>/**************************************************************************\* Register Overlay Structure\**************************************************************************/typedef struct  {    volatile Uint8 RHR_THR_DLL;    const char RSVD0[3];    volatile Uint8 IER_DLH;    const char RSVD1[3];    volatile Uint8 IIR_FCR_EFR;    const char RSVD2[3];    volatile Uint8 LCR;    const char RSVD3[3];    volatile Uint8 MCR_XON1;    const char RSVD4[3];    volatile Uint8 LSR_XON2;    const char RSVD5[3];    volatile Uint8 MSR_TCR_XOFF1;    const char RSVD6[3];    volatile Uint8 SPR_TLR_XOFF2;    const char RSVD7[3];    volatile Uint8 MDR1;    const char RSVD8[23];    volatile Uint8 UASR;    const char RSVD9[7];    volatile Uint8 SCR;    const char RSVD10[3];    volatile Uint8 SSR;    const char RSVD11[11];    volatile Uint8 MVR;    const char RSVD12[3];    volatile Uint8 SYSC;    const char RSVD13[3];    volatile Uint8 SYSS;    const char RSVD14[3];    volatile Uint8 WER;} CSL_UartRegs;/**************************************************************************\* Overlay structure typedef definition\**************************************************************************/typedef volatile CSL_UartRegs  * CSL_UartRegsOvly;/**************************************************************************\* Field Definition Macros\**************************************************************************//* RHR_THR_DLL */#define CSL_UART_RHR_THR_DLL_RHR_THR_DLL_MASK (0x000000FFu)#define CSL_UART_RHR_THR_DLL_RHR_THR_DLL_SHIFT (0x00000000u)#define CSL_UART_RHR_THR_DLL_RHR_THR_DLL_RESETVAL (0x00000000u)#define CSL_UART_RHR_THR_DLL_RESETVAL    (0x00000000u)/* RHR */#define CSL_UART_RHR_RHR_MASK            (0x000000FFu)#define CSL_UART_RHR_RHR_SHIFT           (0x00000000u)#define CSL_UART_RHR_RHR_RESETVAL        (0x00000000u)#define CSL_UART_RHR_RESETVAL            (0x00000000u)/* THR */#define CSL_UART_THR_THR_MASK            (0x000000FFu)#define CSL_UART_THR_THR_SHIFT           (0x00000000u)#define CSL_UART_THR_THR_RESETVAL        (0x00000000u)#define CSL_UART_THR_RESETVAL            (0x00000000u)/* DLL */#define CSL_UART_DLL_CLOCK_LSB_MASK      (0x000000FFu)#define CSL_UART_DLL_CLOCK_LSB_SHIFT     (0x00000000u)#define CSL_UART_DLL_CLOCK_LSB_RESETVAL  (0x00000000u)#define CSL_UART_DLL_RESETVAL            (0x00000000u)/* IER_DLH */#define CSL_UART_IER_DLH_IER_DLH_MASK    (0x000000FFu)#define CSL_UART_IER_DLH_IER_DLH_SHIFT   (0x00000000u)#define CSL_UART_IER_DLH_IER_DLH_RESETVAL (0x00000000u)#define CSL_UART_IER_DLH_RESETVAL        (0x00000000u)/* IER */#define CSL_UART_IER_CTS_IT_MASK         (0x00000080u)#define CSL_UART_IER_CTS_IT_SHIFT        (0x00000007u)#define CSL_UART_IER_CTS_IT_RESETVAL     (0x00000000u)#define CSL_UART_IER_RTS_IT_MASK         (0x00000040u)#define CSL_UART_IER_RTS_IT_SHIFT        (0x00000006u)#define CSL_UART_IER_RTS_IT_RESETVAL     (0x00000000u)#define CSL_UART_IER_XOFF_IT_MASK        (0x00000020u)#define CSL_UART_IER_XOFF_IT_SHIFT       (0x00000005u)#define CSL_UART_IER_XOFF_IT_RESETVAL    (0x00000000u)#define CSL_UART_IER_SLEEP_MODE_MASK     (0x00000010u)#define CSL_UART_IER_SLEEP_MODE_SHIFT    (0x00000004u)#define CSL_UART_IER_SLEEP_MODE_RESETVAL (0x00000000u)#define CSL_UART_IER_MODEM_STS_IT_MASK   (0x00000008u)#define CSL_UART_IER_MODEM_STS_IT_SHIFT  (0x00000003u)#define CSL_UART_IER_MODEM_STS_IT_RESETVAL (0x00000000u)#define CSL_UART_IER_LINE_STS_IT_MASK    (0x00000004u)#define CSL_UART_IER_LINE_STS_IT_SHIFT   (0x00000002u)#define CSL_UART_IER_LINE_STS_IT_RESETVAL (0x00000000u)#define CSL_UART_IER_THR_IT_MASK         (0x00000002u)#define CSL_UART_IER_THR_IT_SHIFT        (0x00000001u)#define CSL_UART_IER_THR_IT_RESETVAL     (0x00000000u)#define CSL_UART_IER_RHR_IT_MASK         (0x00000001u)#define CSL_UART_IER_RHR_IT_SHIFT        (0x00000000u)#define CSL_UART_IER_RHR_IT_RESETVAL     (0x00000000u)#define CSL_UART_IER_RESETVAL            (0x00000000u)/* DLH */#define CSL_UART_DLH_CLOCK_MSB_MASK      (0x0000003Fu)#define CSL_UART_DLH_CLOCK_MSB_SHIFT     (0x00000000u)#define CSL_UART_DLH_CLOCK_MSB_RESETVAL  (0x00000000u)#define CSL_UART_DLH_RESETVAL            (0x00000000u)/* IIR_FCR_EFR */#define CSL_UART_IIR_FCR_EFR_IIR_FCR_EFR_MASK (0x000000FFu)#define CSL_UART_IIR_FCR_EFR_IIR_FCR_EFR_SHIFT (0x00000000u)#define CSL_UART_IIR_FCR_EFR_IIR_FCR_EFR_RESETVAL (0x00000000u)#define CSL_UART_IIR_FCR_EFR_RESETVAL    (0x00000000u)/* IIR */#define CSL_UART_IIR_FCR_MIRROR_MASK     (0x000000C0u)#define CSL_UART_IIR_FCR_MIRROR_SHIFT    (0x00000006u)#define CSL_UART_IIR_FCR_MIRROR_RESETVAL (0x00000000u)#define CSL_UART_IIR_FCR_MIRROR_DISABLE  (0x00000000u)#define CSL_UART_IIR_FCR_MIRROR_ENABLE   (0x00000003u)#define CSL_UART_IIR_IT_TYPE_MASK        (0x0000003Eu)#define CSL_UART_IIR_IT_TYPE_SHIFT       (0x00000001u)#define CSL_UART_IIR_IT_TYPE_RESETVAL    (0x00000000u)#define CSL_UART_IIR_IT_TYPE_RX_LINE_STATUS (0x00000003u)#define CSL_UART_IIR_IT_TYPE_RX_TIMEOUT  (0x00000006u)#define CSL_UART_IIR_IT_TYPE_RHR         (0x00000002u)#define CSL_UART_IIR_IT_TYPE_THR         (0x00000001u)#define CSL_UART_IIR_IT_TYPE_MSR         (0x00000000u)#define CSL_UART_IIR_IT_TYPE_XOFF_SPCHAR (0x00000008u)#define CSL_UART_IIR_IT_TYPE_RCD         (0x00000010u)#define CSL_UART_IIR_IT_PENDING_MASK     (0x00000001u)#define CSL_UART_IIR_IT_PENDING_SHIFT    (0x00000000u)#define CSL_UART_IIR_IT_PENDING_RESETVAL (0x00000001u)#define CSL_UART_IIR_IT_PENDING_NONE     (0x00000001u)#define CSL_UART_IIR_IT_PENDING_PEND     (0x00000000u)#define CSL_UART_IIR_RESETVAL            (0x00000001u)/* EFR */#define CSL_UART_EFR_AUTO_CTS_EN_MASK    (0x00000080u)#define CSL_UART_EFR_AUTO_CTS_EN_SHIFT   (0x00000007u)#define CSL_UART_EFR_AUTO_CTS_EN_RESETVAL (0x00000000u)#define CSL_UART_EFR_AUTO_CTS_EN_DISABLE (0x00000000u)#define CSL_UART_EFR_AUTO_CTS_EN_ENABLE  (0x00000001u)#define CSL_UART_EFR_AUTO_RTS_EN_MASK    (0x00000040u)#define CSL_UART_EFR_AUTO_RTS_EN_SHIFT   (0x00000006u)#define CSL_UART_EFR_AUTO_RTS_EN_RESETVAL (0x00000000u)#define CSL_UART_EFR_AUTO_RTS_EN_DISABLE (0x00000000u)#define CSL_UART_EFR_AUTO_RTS_EN_ENABLE  (0x00000001u)#define CSL_UART_EFR_SPECIAL_CHAR_DETECT_MASK (0x00000020u)#define CSL_UART_EFR_SPECIAL_CHAR_DETECT_SHIFT (0x00000005u)#define CSL_UART_EFR_SPECIAL_CHAR_DETECT_RESETVAL (0x00000000u)#define CSL_UART_EFR_SPECIAL_CHAR_DETECT_DISABLE (0x00000000u)#define CSL_UART_EFR_SPECIAL_CHAR_DETECT_ENABLE (0x00000001u)#define CSL_UART_EFR_ENHANCED_EN_MASK    (0x00000010u)#define CSL_UART_EFR_ENHANCED_EN_SHIFT   (0x00000004u)#define CSL_UART_EFR_ENHANCED_EN_RESETVAL (0x00000000u)#define CSL_UART_EFR_ENHANCED_EN_DISABLE (0x00000000u)#define CSL_UART_EFR_ENHANCED_EN_ENABLE  (0x00000001u)#define CSL_UART_EFR_SW_FLOW_CONTROL_MASK (0x0000000Fu)#define CSL_UART_EFR_SW_FLOW_CONTROL_SHIFT (0x00000000u)#define CSL_UART_EFR_SW_FLOW_CONTROL_RESETVAL (0x00000000u)#define CSL_UART_EFR_RESETVAL            (0x00000000u)/* FCR */#define CSL_UART_FCR_RX_FIFO_TRIG_MASK   (0x000000C0u)#define CSL_UART_FCR_RX_FIFO_TRIG_SHIFT  (0x00000006u)#define CSL_UART_FCR_RX_FIFO_TRIG_RESETVAL (0x00000000u)#define CSL_UART_FCR_TX_FIFO_TRIG_MASK   (0x00000030u)#define CSL_UART_FCR_TX_FIFO_TRIG_SHIFT  (0x00000004u)#define CSL_UART_FCR_TX_FIFO_TRIG_RESETVAL (0x00000000u)#define CSL_UART_FCR_DMA_MODE_MASK       (0x00000008u)#define CSL_UART_FCR_DMA_MODE_SHIFT      (0x00000003u)#define CSL_UART_FCR_DMA_MODE_RESETVAL   (0x00000000u)#define CSL_UART_FCR_TX_FIFO_CLEAR_MASK  (0x00000004u)#define CSL_UART_FCR_TX_FIFO_CLEAR_SHIFT (0x00000002u)#define CSL_UART_FCR_TX_FIFO_CLEAR_RESETVAL (0x00000000u)#define CSL_UART_FCR_TX_FIFO_CLEAR_DISABLE (0x00000000u)#define CSL_UART_FCR_TX_FIFO_CLEAR_ENABLE (0x00000001u)#define CSL_UART_FCR_RX_FIFO_CLEAR_MASK  (0x00000002u)#define CSL_UART_FCR_RX_FIFO_CLEAR_SHIFT (0x00000001u)#define CSL_UART_FCR_RX_FIFO_CLEAR_RESETVAL (0x00000000u)#define CSL_UART_FCR_RX_FIFO_CLEAR_DISABLE (0x00000000u)#define CSL_UART_FCR_RX_FIFO_CLEAR_ENABLE (0x00000001u)#define CSL_UART_FCR_FIFO_EN_MASK        (0x00000001u)#define CSL_UART_FCR_FIFO_EN_SHIFT       (0x00000000u)#define CSL_UART_FCR_FIFO_EN_RESETVAL    (0x00000000u)#define CSL_UART_FCR_FIFO_EN_DISABLE     (0x00000000u)#define CSL_UART_FCR_FIFO_EN_ENABLE      (0x00000001u)#define CSL_UART_FCR_RESETVAL            (0x00000000u)/* LCR */#define CSL_UART_LCR_DIV_EN_MASK         (0x00000080u)#define CSL_UART_LCR_DIV_EN_SHIFT        (0x00000007u)#define CSL_UART_LCR_DIV_EN_RESETVAL     (0x00000000u)#define CSL_UART_LCR_DIV_EN_DISABLE      (0x00000000u)#define CSL_UART_LCR_DIV_EN_ENABLE       (0x00000001u)#define CSL_UART_LCR_BREAK_EN_MASK       (0x00000040u)#define CSL_UART_LCR_BREAK_EN_SHIFT      (0x00000006u)#define CSL_UART_LCR_BREAK_EN_RESETVAL   (0x00000000u)#define CSL_UART_LCR_BREAK_EN_DISABLE    (0x00000000u)#define CSL_UART_LCR_BREAK_EN_ENABLE     (0x00000001u)#define CSL_UART_LCR_PARITY_TYPE2_MASK   (0x00000020u)#define CSL_UART_LCR_PARITY_TYPE2_SHIFT  (0x00000005u)#define CSL_UART_LCR_PARITY_TYPE2_RESETVAL (0x00000000u)#define CSL_UART_LCR_PARITY_TYPE1_MASK   (0x00000010u)#define CSL_UART_LCR_PARITY_TYPE1_SHIFT  (0x00000004u)#define CSL_UART_LCR_PARITY_TYPE1_RESETVAL (0x00000000u)#define CSL_UART_LCR_PARITY_EN_MASK      (0x00000008u)#define CSL_UART_LCR_PARITY_EN_SHIFT     (0x00000003u)#define CSL_UART_LCR_PARITY_EN_RESETVAL  (0x00000000u)#define CSL_UART_LCR_NB_STOP_MASK        (0x00000004u)#define CSL_UART_LCR_NB_STOP_SHIFT       (0x00000002u)#define CSL_UART_LCR_NB_STOP_RESETVAL    (0x00000000u)#define CSL_UART_LCR_NB_STOP_01          (0x00000000u)#define CSL_UART_LCR_NB_STOP_1_5         (0x00000001u)#define CSL_UART_LCR_NB_STOP_02          (0x00000001u)#define CSL_UART_LCR_CHAR_LENGTH_MASK    (0x00000003u)#define CSL_UART_LCR_CHAR_LENGTH_SHIFT   (0x00000000u)#define CSL_UART_LCR_CHAR_LENGTH_RESETVAL (0x00000000u)#define CSL_UART_LCR_CHAR_LENGTH_05      (0x00000000u)#define CSL_UART_LCR_CHAR_LENGTH_06      (0x00000001u)#define CSL_UART_LCR_CHAR_LENGTH_07      (0x00000002u)#define CSL_UART_LCR_CHAR_LENGTH_08      (0x00000003u)#define CSL_UART_LCR_RESETVAL            (0x00000000u)/* MCR_XON1 */#define CSL_UART_MCR_XON1_MCR_XON1_MASK  (0x000000FFu)#define CSL_UART_MCR_XON1_MCR_XON1_SHIFT (0x00000000u)#define CSL_UART_MCR_XON1_MCR_XON1_RESETVAL (0x00000000u)#define CSL_UART_MCR_XON1_RESETVAL       (0x00000000u)/* MCR */#define CSL_UART_MCR_TCR_TLR_MASK        (0x00000040u)#define CSL_UART_MCR_TCR_TLR_SHIFT       (0x00000006u)#define CSL_UART_MCR_TCR_TLR_RESETVAL    (0x00000000u)#define CSL_UART_MCR_TCR_TLR_DISABLE     (0x00000000u)#define CSL_UART_MCR_TCR_TLR_ENABLE      (0x00000001u)#define CSL_UART_MCR_XON_EN_MASK         (0x00000020u)#define CSL_UART_MCR_XON_EN_SHIFT        (0x00000005u)#define CSL_UART_MCR_XON_EN_RESETVAL     (0x00000000u)#define CSL_UART_MCR_XON_EN_DISABLE      (0x00000000u)#define CSL_UART_MCR_XON_EN_ENABLE       (0x00000001u)#define CSL_UART_MCR_LOOPBACK_EN_MASK    (0x00000010u)#define CSL_UART_MCR_LOOPBACK_EN_SHIFT   (0x00000004u)#define CSL_UART_MCR_LOOPBACK_EN_RESETVAL (0x00000000u)#define CSL_UART_MCR_LOOPBACK_EN_DISABLE (0x00000000u)#define CSL_UART_MCR_LOOPBACK_EN_ENABLE  (0x00000001u)#define CSL_UART_MCR_CD_STS_CH_MASK      (0x00000008u)#define CSL_UART_MCR_CD_STS_CH_SHIFT     (0x00000003u)#define CSL_UART_MCR_CD_STS_CH_RESETVAL  (0x00000000u)#define CSL_UART_MCR_CD_STS_CH_HIGH      (0x00000000u)#define CSL_UART_MCR_CD_STS_CH_LOW       (0x00000001u)#define CSL_UART_MCR_RI_STS_CH_MASK      (0x00000004u)#define CSL_UART_MCR_RI_STS_CH_SHIFT     (0x00000002u)#define CSL_UART_MCR_RI_STS_CH_RESETVAL  (0x00000000u)#define CSL_UART_MCR_RI_STS_CH_HIGH      (0x00000000u)#define CSL_UART_MCR_RI_STS_CH_LOW       (0x00000001u)#define CSL_UART_MCR_RTS_MASK            (0x00000002u)#define CSL_UART_MCR_RTS_SHIFT           (0x00000001u)#define CSL_UART_MCR_RTS_RESETVAL        (0x00000000u)#define CSL_UART_MCR_RTS_DISABLE         (0x00000000u)#define CSL_UART_MCR_RTS_ENABLE          (0x00000001u)#define CSL_UART_MCR_DTR_MASK            (0x00000001u)#define CSL_UART_MCR_DTR_SHIFT           (0x00000000u)#define CSL_UART_MCR_DTR_RESETVAL        (0x00000000u)#define CSL_UART_MCR_DTR_DISABLE         (0x00000000u)#define CSL_UART_MCR_DTR_ENABLE          (0x00000001u)#define CSL_UART_MCR_RESETVAL            (0x00000000u)/* XON1 */#define CSL_UART_XON1_XON_WORD1_MASK     (0x000000FFu)#define CSL_UART_XON1_XON_WORD1_SHIFT    (0x00000000u)#define CSL_UART_XON1_XON_WORD1_RESETVAL (0x00000000u)#define CSL_UART_XON1_RESETVAL           (0x00000000u)/* LSR_XON2 */#define CSL_UART_LSR_XON2_LSR_XON2_MASK  (0x000000FFu)#define CSL_UART_LSR_XON2_LSR_XON2_SHIFT (0x00000000u)#define CSL_UART_LSR_XON2_LSR_XON2_RESETVAL (0x00000000u)#define CSL_UART_LSR_XON2_RESETVAL       (0x00000000u)/* LSR */#define CSL_UART_LSR_RX_FIFO_STS_MASK    (0x00000080u)#define CSL_UART_LSR_RX_FIFO_STS_SHIFT   (0x00000007u)#define CSL_UART_LSR_RX_FIFO_STS_RESETVAL (0x00000000u)#define CSL_UART_LSR_TX_SR_E_MASK        (0x00000040u)
cslr_uart.h - 源码说明

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