csl_ulpdaux.h

来自「dsp在音频处理中的运用」· C头文件 代码 · 共 624 行 · 第 1/2 页

 */
static inline 
void CSL_ulpdSwdUpldPllClkReqConfig(
    CSL_UlpdHandle    hUlpd,
    Bool              val
    )

{
    /* BCLK clock software request config */
    CSL_FINS(hUlpd->regs->SDW_CLK_DIV_CTRL_SEL, ULPD_SDW_CLK_DIV_CTRL_SEL_SDW_ULPD_PLL_CLK_REQ, val);
}

/* ============================================================================
 *   @n@b CSL_ulpdSwdClkConfig
 *
 *   @b Description
 *   @n Select APLL clock or SYSTEM Clock for BCLK output.
 *      FALSE request APLL clock
 *      TRUE  request SYSTEM clock
 *
 *
 *   @b Example
 *   @verbatim
        CSL_UlpdHandle    hUlpd;
        
        ...
        CSL_ulpdSwdClkConfig(hUlpd, TRUE);        ...
        
     @endverbatim
 * ===========================================================================
 */
static inline 
void CSL_ulpdSwdClkConfig(
    CSL_UlpdHandle    hUlpd,
    Bool              val
    )

{
    /* Select APLL clock or SYSTEM Clock for BCLK output */
    CSL_FINS(hUlpd->regs->SDW_CLK_DIV_CTRL_SEL, ULPD_SDW_CLK_DIV_CTRL_SEL_SDW_SYSCLK_PLLCLK_SEL, val);
}


/* ============================================================================
 *   @n@b CSL_ulpdComRatioSel
 *
 *   @b Description
 *   @n This routine is used to Select the frequency to be configured for the 
 *      divider ratio feild which is applied to the APLL output clock to generate MCLK..
 *
 *   @b Example
 *   @verbatim
        CSL_UlpdHandle    hUlpd;
        CSL_UlpdMclkFreq  mclkFreqVal = CSL_ULPD_COM_DIV_RATIO_48MHZ;          
        ...
        CSL_ulpdComRatioSel(hUlpd, bclkFreqVal);
        ...
        
     @endverbatim
 * ===========================================================================
 */
static inline 
void CSL_ulpdComRatioSel(
    CSL_UlpdHandle    hUlpd,
    CSL_UlpdMclkFreq  mclkFreqVal
)

{
    /* configure MCLK ratio */
    CSL_FINS(hUlpd->regs->COM_CLK_DIV_CTRL_SEL, ULPD_COM_CLK_DIV_CTRL_SEL_COM_RATIO_SEL, mclkFreqVal);
}

/* ============================================================================
 *   @n@b CSL_ulpdComUpldPllClkReqConfig
 *
 *   @b Description
 *   @n MCLK clock software request configuaration.
 *      FALSE request Inactive
 *      TRUE  request Active  
 *
 *   @b Example
 *   @verbatim
        CSL_UlpdHandle    hUlpd;
        
        ...
        CSL_ulpdComUpldPllClkReqConfig(hUlpd, TRUE/FALSE);
        ...
        
     @endverbatim
 * ===========================================================================
 */
static inline 
void CSL_ulpdComUpldPllClkReqConfig(
    CSL_UlpdHandle    hUlpd,
    Bool              val
    )

{
    /* MCLK clock software request config */
    CSL_FINS(hUlpd->regs->COM_CLK_DIV_CTRL_SEL, ULPD_COM_CLK_DIV_CTRL_SEL_COM_ULPD_PLL_CLK_REQ, val);
}

/* ============================================================================
 *   @n@b CSL_ulpdComClkConfig
 *
 *   @b Description
 *   @n Select APLL clock or SYSTEM Clock for MCLK output.
 *      FALSE request APLL clock
 *      TRUE  request SYSTEM clock
 *
 *   @b Example
 *   @verbatim
        CSL_UlpdHandle    hUlpd;
        
        ...
        CSL_ulpdComClkConfig(hUlpd, TRUE);        ...
        
     @endverbatim
 * ===========================================================================
 */
static inline 
void CSL_ulpdComClkConfig(
    CSL_UlpdHandle    hUlpd,
    Bool              val
    )

{
    /* Select APLL clock or SYSTEM Clock for MCLK output */
    CSL_FINS(hUlpd->regs->COM_CLK_DIV_CTRL_SEL, ULPD_COM_CLK_DIV_CTRL_SEL_COM_SYSCLK_PLLCLK_SEL, val);
}

/* ============================================================================
 *   @n@b CSL_ulpdSystemClkEnDis
 *
 *   @b Description
 *   @n Clock enable/disable of the system clock for GPIO modules
 *      FALSE: Clock disabled
 *      TRUE: Clock enabled
 *
 *   @b Example
 *   @verbatim
        CSL_UlpdHandle    hUlpd,         
        ...
        CSL_ulpdSystemClkEnDis(hUlpd, TRUE);
        ...
        
     @endverbatim
 * ===========================================================================
 */
static inline 
void CSL_ulpdSystemClkEnDis(
    CSL_UlpdHandle    hUlpd,
    Bool              val
)

{
    /* Clock enable/disable of the system clock for GPIO modules. */
    CSL_FINS(hUlpd->regs->CAM_CLK_CTRL, ULPD_CAM_CLK_CTRL_SYSTEM_CLK_EN, val);
}

/* ============================================================================
 *   @n@b CSL_ulpdCamClkDivConfig
 *
 *   @b Description
 *   @n When 0, the CAM.CLKOUT is the system clock, 
        When 1, the CAM.CLKOUT is the system clock.
 *
 *   @b Example
 *   @verbatim
        CSL_UlpdHandle    hUlpd,         
        ...
        CSL_ulpdCamClkDivConfig(hUlpd, 0x1);
        ...
        
     @endverbatim
 * ===========================================================================
 */
static inline 
void CSL_ulpdCamClkDivConfig(
    CSL_UlpdHandle    hUlpd,
    Bool              val
)
{
    /* 
     * When 0, the CAM.CLKOUT is the system clock, 
     * When 1, the CAM.CLKOUT is the system clock. 
     */
    CSL_FINS(hUlpd->regs->CAM_CLK_CTRL, ULPD_CAM_CLK_CTRL_CAM_CLK_DIV, val);
}


/* ============================================================================
 *   @n@b CSL_ulpdCamClkEnDis
 *
 *   @b Description
 *   @n Enable/Disable of the CAM.CLKOUT
 *
 *   @b Example
 *   @verbatim
        CSL_UlpdHandle    hUlpd,         
        ...
        CSL_ulpdCamClkEnDis(hUlpd, TRUE);
        ...
        
     @endverbatim
 * ===========================================================================
 */
static inline 
void CSL_ulpdCamClkEnDis(
    CSL_UlpdHandle    hUlpd,
    Bool              val
)

{
    /* Enable/Disable of the CAM.CLKOUT. */
    CSL_FINS(hUlpd->regs->CAM_CLK_CTRL, ULPD_CAM_CLK_CTRL_CAM_CLOCK_EN, val);
}

/* Get divider ratio applied to the APLL output clock to generate BCLK
 *  : response type @a CSL_UlpdBclkFreq
 */
static inline
CSL_UlpdBclkFreq CSL_ulpdGetBclkRatio(
        CSL_UlpdHandle    hUlpd
)
{
 return ((CSL_UlpdBclkFreq)CSL_FEXT(hUlpd->regs->SDW_CLK_DIV_CTRL_SEL, ULPD_SDW_CLK_DIV_CTRL_SEL_SDW_RATIO_SEL));
}

/* Get BCLK clock software request Status */
static inline
Uint32 CSL_ulpdGetBclkPllClkReq(
        CSL_UlpdHandle    hUlpd
)
{
 return ((Uint32)CSL_FEXT(hUlpd->regs->SDW_CLK_DIV_CTRL_SEL, ULPD_SDW_CLK_DIV_CTRL_SEL_SDW_ULPD_PLL_CLK_REQ));
}

/* Get clock selection for BCLK */
static inline
Uint32 CSL_ulpdGetBclkClkSelect(
        CSL_UlpdHandle    hUlpd
)
{
 return ((Uint32)CSL_FEXT(hUlpd->regs->SDW_CLK_DIV_CTRL_SEL, ULPD_SDW_CLK_DIV_CTRL_SEL_SDW_SYSCLK_PLLCLK_SEL ));
}

/* Get divider ratio applied to the APLL output clock to generate MCLK
 *  : response type @a CSL_UlpdMclkFreq
 */
static inline
CSL_UlpdMclkFreq CSL_ulpdGetMclkRatio(
        CSL_UlpdHandle    hUlpd
)
{
 return ((CSL_UlpdMclkFreq)CSL_FEXT(hUlpd->regs->COM_CLK_DIV_CTRL_SEL, ULPD_COM_CLK_DIV_CTRL_SEL_COM_RATIO_SEL));
}

/* Get MCLK clock software request Status */
static inline
Uint32 CSL_ulpdGetMclkPllClkReq(
        CSL_UlpdHandle    hUlpd
)
{
 return ((Uint32)CSL_FEXT(hUlpd->regs->COM_CLK_DIV_CTRL_SEL, ULPD_COM_CLK_DIV_CTRL_SEL_COM_ULPD_PLL_CLK_REQ));
}

/* Get clock selection for MCLK */
static inline
Uint32 CSL_ulpdGetMclkClkSelect(
        CSL_UlpdHandle    hUlpd
)
{
 return ((Uint32)CSL_FEXT(hUlpd->regs->COM_CLK_DIV_CTRL_SEL, ULPD_COM_CLK_DIV_CTRL_SEL_COM_SYSCLK_PLLCLK_SEL ));
}

/* Get Clock enable status of the system clock for GPIO modules*/
static inline
Uint32 CSL_ulpdGetSysClkEn(
        CSL_UlpdHandle    hUlpd
)
{
 return ((Uint32)CSL_FEXT(hUlpd->regs->CAM_CLK_CTRL, ULPD_CAM_CLK_CTRL_SYSTEM_CLK_EN ));
}

/* to Get the clock chosen as CAM.CLKOUT */
static inline
Uint32 CSL_ulpdGetCamClkDiv(
        CSL_UlpdHandle    hUlpd
)
{
 return ((Uint32)CSL_FEXT(hUlpd->regs->CAM_CLK_CTRL, ULPD_CAM_CLK_CTRL_CAM_CLK_DIV));
}

/* Get CAM.CLKOUT status */
static inline
Uint32 CSL_ulpdGetCamClockEn(
        CSL_UlpdHandle    hUlpd
)
{
 return ((Uint32)CSL_FEXT(hUlpd->regs->CAM_CLK_CTRL, ULPD_CAM_CLK_CTRL_CAM_CLOCK_EN ));
}



#ifdef __cplusplus
}
#endif


#endif