csl_ulpdaux.h

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#ifndef _CSL_ULPDAUX_H
#define _CSL_ULPDAUX_H

#ifdef __cplusplus
extern "C" {
#endif

/* Enable gauging   */
static inline
void
	CSL_ulpdGaugeEnable (
		CSL_UlpdHandle                         hUlpd
)
{
	CSL_FINS(hUlpd->regs->GAUGING_CTRL_REG,ULPD_GAUGING_CTRL_REG_GAUGING_EN,0x1);
}

/* Disable gauging  */
static inline
void
	CSL_ulpdGaugeDisable (
		CSL_UlpdHandle                         hUlpd
)
{
	CSL_FINS(hUlpd->regs->GAUGING_CTRL_REG,ULPD_GAUGING_CTRL_REG_GAUGING_EN,0x0);
}

/* Select auxiliary gauging clock */
static inline
void
	CSL_ulpdGaugeAuxClock (
		CSL_UlpdHandle                         hUlpd
)
{
	CSL_FINS(hUlpd->regs->GAUGING_CTRL_REG,ULPD_GAUGING_CTRL_REG_SELECT_HI_FREQ_CLOCK,0x1);
}

/* Select 12-Mhz clock */
static inline
void
	CSL_ulpdGauge12MhzClock (
		CSL_UlpdHandle                         hUlpd
)
{
	CSL_FINS(hUlpd->regs->GAUGING_CTRL_REG,ULPD_GAUGING_CTRL_REG_SELECT_HI_FREQ_CLOCK,0x0);
}

/* Software request active for clock */
static inline
void
	CSL_ulpdSoftClockReqActive (
		CSL_UlpdHandle                         hUlpd,
		CSL_UlpdSoftReq 				   req
)
{
	    hUlpd->regs->SOFT_REQ_REG = hUlpd->regs->SOFT_REQ_REG | req ;
}

/* Inactivate the Software request for clock */
static inline
void
	CSL_ulpdSoftClockReqInActive (
		CSL_UlpdHandle                         hUlpd,
		CSL_UlpdSoftReq 				   req
)
{
	Uint16 temp = req;
 	hUlpd->regs->SOFT_REQ_REG = hUlpd->regs->SOFT_REQ_REG &  ~temp ;
}

/* Low power request */
static inline
void
	CSL_ulpdLowPwrRequest (
		CSL_UlpdHandle                         hUlpd
)
{
	CSL_FINS(hUlpd->regs->POWER_CTRL_REG,ULPD_POWER_CTRL_REG_LOW_PWR_REQ,0x1);
}

/* Clear Low power request */
static inline
void
	CSL_ulpdLowPwrRequestClear (
		CSL_UlpdHandle                         hUlpd
)
{
	CSL_FINS(hUlpd->regs->POWER_CTRL_REG,ULPD_POWER_CTRL_REG_LOW_PWR_REQ,0x0);
}

/* Deep Sleep transition enable */
static inline
void
	CSL_ulpdDeepSleepTranEnable (
		CSL_UlpdHandle                         hUlpd
)
{
	CSL_FINS(hUlpd->regs->POWER_CTRL_REG,ULPD_POWER_CTRL_REG_DEEP_SLEEP_TRANSITION_EN,0x1);
}

/* Deep Sleep transition disable */
static inline
void
	CSL_ulpdDeepSleepTranDisable (
		CSL_UlpdHandle                         hUlpd
)
{
	CSL_FINS(hUlpd->regs->POWER_CTRL_REG,ULPD_POWER_CTRL_REG_DEEP_SLEEP_TRANSITION_EN,0x0);
}

/* Low power modes are enable  */
static inline
void
	CSL_ulpdLowPowerEnable (
		CSL_UlpdHandle                         hUlpd
)
{
	CSL_FINS(hUlpd->regs->POWER_CTRL_REG,ULPD_POWER_CTRL_REG_LOW_PWR_EN,0x1);
}

/* Low power modes are disable */
static inline
void
	CSL_ulpdLowPowerDisable (
		CSL_UlpdHandle                         hUlpd
)
{
	CSL_FINS(hUlpd->regs->POWER_CTRL_REG,ULPD_POWER_CTRL_REG_LOW_PWR_EN,0x0);
}

/* Clear the reset status bits */
static inline
void
	CSL_ulpdClearResetStatus (
		CSL_UlpdHandle                         hUlpd,
		CSL_UlpdRstSrc 				   src
)
{	Uint16 temp = src ;
	hUlpd->regs->RESET_STATUS = hUlpd->regs->RESET_STATUS & ~temp ;
}

/* Disable the H/W Clock request from Software */
static inline
void
	CSL_ulpdHwClkReqDisable (
		CSL_UlpdHandle                         hUlpd,
		CSL_UlpdSoftReq  				   req
)
{
	if(req & CSL_ULPD_MMC_DPLL_REQ)
		CSL_FINS(hUlpd->regs->SOFT_DISABLE_REQ_REG,ULPD_SOFT_DISABLE_REQ_REG_DIS_MMC_DPLL_REQ,TRUE);

	  if(req & CSL_ULPD_UART3_DPLL_REQ)
		  CSL_FINS(hUlpd->regs->SOFT_DISABLE_REQ_REG,ULPD_SOFT_DISABLE_REQ_REG_DIS_UART3_DPLL_REQ,TRUE);

	  if(req & CSL_ULPD_UART2_DPLL_REQ)
		  CSL_FINS(hUlpd->regs->SOFT_DISABLE_REQ_REG,ULPD_SOFT_DISABLE_REQ_REG_DIS_UART2_DPLL_REQ,TRUE);

	  if(req & CSL_ULPD_UART1_DPLL_REQ)
		  CSL_FINS(hUlpd->regs->SOFT_DISABLE_REQ_REG,ULPD_SOFT_DISABLE_REQ_REG_DIS_UART1_DPLL_REQ,TRUE);

	  if(req & CSL_ULPD_USB_OTG_DPLL_REQ)
		  CSL_FINS(hUlpd->regs->SOFT_DISABLE_REQ_REG,ULPD_SOFT_DISABLE_REQ_REG_DIS_USB_HOST_DPLL_REQ,TRUE);

	  if(req & CSL_ULPD_PERIPH_NREQ)
		  CSL_FINS(hUlpd->regs->SOFT_DISABLE_REQ_REG,ULPD_SOFT_DISABLE_REQ_REG_DIS_PERIPH_NREQ,TRUE);
}

/* Enable the H/W Clock request from Software */
static inline
void
	CSL_ulpdHwClkReqEnable (
		CSL_UlpdHandle                         hUlpd,
		CSL_UlpdSoftReq  				   req
)
{
	if(req & CSL_ULPD_MMC_DPLL_REQ)
		CSL_FINS(hUlpd->regs->SOFT_DISABLE_REQ_REG,ULPD_SOFT_DISABLE_REQ_REG_DIS_MMC_DPLL_REQ,FALSE);

	  if(req & CSL_ULPD_UART3_DPLL_REQ)
		  CSL_FINS(hUlpd->regs->SOFT_DISABLE_REQ_REG,ULPD_SOFT_DISABLE_REQ_REG_DIS_UART3_DPLL_REQ,FALSE);

	  if(req & CSL_ULPD_UART2_DPLL_REQ)
		  CSL_FINS(hUlpd->regs->SOFT_DISABLE_REQ_REG,ULPD_SOFT_DISABLE_REQ_REG_DIS_UART2_DPLL_REQ,FALSE);

	  if(req & CSL_ULPD_UART1_DPLL_REQ)
		  CSL_FINS(hUlpd->regs->SOFT_DISABLE_REQ_REG,ULPD_SOFT_DISABLE_REQ_REG_DIS_UART1_DPLL_REQ,FALSE);

	  if(req & CSL_ULPD_USB_OTG_DPLL_REQ)
		  CSL_FINS(hUlpd->regs->SOFT_DISABLE_REQ_REG,ULPD_SOFT_DISABLE_REQ_REG_DIS_USB_HOST_DPLL_REQ,FALSE);

	  if(req & CSL_ULPD_PERIPH_NREQ)
		  CSL_FINS(hUlpd->regs->SOFT_DISABLE_REQ_REG,ULPD_SOFT_DISABLE_REQ_REG_DIS_PERIPH_NREQ,FALSE);
}

/* Get the Interrupt status information. */
static inline
CSL_UlpdIntStat
	CSL_ulpdGetIntStatus(
		CSL_UlpdHandle                         hUlpd
)
{
	return ((CSL_UlpdIntStat)(hUlpd->regs->IT_STATUS_REG & 0x000F));
}

/* Clock request status information */
static inline
CSL_UlpdStsReq
	CSL_ulpdGetClockReqStatus(
		CSL_UlpdHandle                         hUlpd
)
{
	return ((CSL_UlpdStsReq)hUlpd->regs->STATUS_REQ_REG);
}

/* ULPD PLL lock status.  */
static inline
Uint16
	CSL_ulpdGetLockStatus(
		CSL_UlpdHandle                         hUlpd
)
{
 return ((Uint16)CSL_FEXT(hUlpd->regs->ULPD_PLL_CTRL_STATUS,ULPD_ULPD_PLL_CTRL_STATUS_LOCK_STATUS));
}

/* Sleep status.  */
static inline
Uint16
	CSL_ulpdGetSleepStatus(
		CSL_UlpdHandle                         hUlpd
)
{
	return ((Uint16)hUlpd->regs->SLEEP_STATUS & 0x0003);
}

/* Get the cause for reset. */
static inline
CSL_UlpdRstSrc
	CSL_ulpdGetResetEvent(
		CSL_UlpdHandle                         hUlpd
)
{
	return ((CSL_UlpdRstSrc)(hUlpd->regs->RESET_STATUS & 0x000F));
}

/* Get the number of clock cycles of 32-Khz clock during Gauging time */
static inline
Uint32
	CSL_ulpdGet32khzCounter (
		CSL_UlpdHandle                         hUlpd
)
{
	return ((Uint32)((hUlpd->regs->COUNTER_32_MSB_REG << 16) | hUlpd->regs->COUNTER_32_LSB_REG) & 0x000FFFFF);
}

/* Get the number of clock cycles of high freq clock during Gauging time */
static inline
Uint32
	CSL_ulpdGetHighFreqCounter(
		CSL_UlpdHandle                         hUlpd
)
{
	return ((Uint32)((hUlpd->regs->COUNTER_HIGH_FREQ_MSB_REG << 16) | hUlpd->regs->COUNTER_HIGH_FREQ_LSB_REG) & 0x003FFFFF);
}

/* ============================================================================
 *   @n@b CSL_ulpdSwdRatioSel
 *
 *   @b Description
 *   @n This routine is used to Select the frequency to be configured for the 
 *      divider ratio feild which is applied to the APLL output clock to generate BCLK..
 *
 *   @b Example
 *   @verbatim
        CSL_UlpdHandle    hUlpd;
        CSL_UlpdBclkFreq  bclkFreqVal = CSL_ULPD_SDW_DIV_RATIO_48MHZ;          
        ...
        CSL_ulpdSwdRatioSel(hUlpd, bclkFreqVal);
        ...
        
     @endverbatim
 * ===========================================================================
 */
static inline 
void CSL_ulpdSwdRatioSel(
    CSL_UlpdHandle    hUlpd,
    CSL_UlpdBclkFreq  bclkFreqVal
)

{
    /* configure BCLK ratio */
    CSL_FINS(hUlpd->regs->SDW_CLK_DIV_CTRL_SEL, ULPD_SDW_CLK_DIV_CTRL_SEL_SDW_RATIO_SEL, bclkFreqVal);
}

/* ============================================================================
 *   @n@b CSL_ulpdSwdUpldPllClkReqConfig
 *
 *   @b Description
 *   @n BCLK clock software request configuaration.
 *      FALSE request Inactive
 *      TRUE  request Active  
 *
 *   @b Example
 *   @verbatim
        CSL_UlpdHandle    hUlpd;
        
        ...
        CSL_ulpdSwdUpldPllClkReqConfig(hUlpd, TRUE/FALSE);
        ...
        
     @endverbatim
 * ===========================================================================