cslr_gptimer.h

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#define CSL_GPTIMER_TWER_TCAR_WUP_ENA_DISABLE (0x00000000u)
/** Token to enable wakeup on capture */
#define CSL_GPTIMER_TWER_TCAR_WUP_ENA_ENABLE (0x00000001u)

/** overflow wakeup enable field mask*/
#define CSL_GPTIMER_TWER_OVF_WUP_ENA_MASK (0x00000002u)
/** overflow wakeup enable field shift*/
#define CSL_GPTIMER_TWER_OVF_WUP_ENA_SHIFT (0x00000001u)
/** overflow wakeup enable field reset value*/
#define CSL_GPTIMER_TWER_OVF_WUP_ENA_RESETVAL (0x00000000u)
/** Token to disable wakeup on overflow */
#define CSL_GPTIMER_TWER_OVF_WUP_ENA_DISABLE (0x00000000u)
/** Token to enable wakeup on overflow */
#define CSL_GPTIMER_TWER_OVF_WUP_ENA_ENABLE (0x00000001u)

/** match wakeup enable field mask*/
#define CSL_GPTIMER_TWER_MAT_WUP_ENA_MASK (0x00000001u)
/** match wakeup enable field shift*/
#define CSL_GPTIMER_TWER_MAT_WUP_ENA_SHIFT (0x00000000u)
/** match wakeup enable field reset value*/
#define CSL_GPTIMER_TWER_MAT_WUP_ENA_RESETVAL (0x00000000u)
/** Token to disable wakeup on match */
#define CSL_GPTIMER_TWER_MAT_WUP_ENA_DISABLE (0x00000000u)
/** Token to enable wakeup on match */
#define CSL_GPTIMER_TWER_MAT_WUP_ENA_ENABLE (0x00000001u)

/** Reset value for TWER register */
#define CSL_GPTIMER_TWER_RESETVAL        (0x00000000u)

/** TCLR */

/** Pulse /toggle selection bit field mask */
#define CSL_GPTIMER_TCLR_PT_MASK         (0x00001000u)
/** Pulse /toggle selection bit field shift */
#define CSL_GPTIMER_TCLR_PT_SHIFT        (0x0000000Cu)
/** Pulse /toggle selection bit field reset value */
#define CSL_GPTIMER_TCLR_PT_RESETVAL     (0x00000000u)
/** Token to select pulse */
#define CSL_GPTIMER_TCLR_PT_PULSE        (0x00000000u)
/** Token to select toggle */
#define CSL_GPTIMER_TCLR_PT_TOGGLE       (0x00000001u)

/** PWM trigger bit field mask */
#define CSL_GPTIMER_TCLR_TRG_MASK        (0x00000C00u)
/** PWM trigger bit field shift */
#define CSL_GPTIMER_TCLR_TRG_SHIFT       (0x0000000Au)
/** PWM trigger bit field reset value */
#define CSL_GPTIMER_TCLR_TRG_RESETVAL    (0x00000000u)
/** Token for no trigger */
#define CSL_GPTIMER_TCLR_TRG_NOTRIG      (0x00000000u)
/** Token for trigger on overflow */
#define CSL_GPTIMER_TCLR_TRG_TRIGONOVF   (0x00000001u)
/** Token for trigger on overflow or match*/
#define CSL_GPTIMER_TCLR_TRG_TRIGONOVFORMATCH (0x00000002u)

/** Transition capture moder bit field mask */
#define CSL_GPTIMER_TCLR_TCM_MASK        (0x00000300u)
/** Transition capture moder bit field shift */
#define CSL_GPTIMER_TCLR_TCM_SHIFT       (0x00000008u)
/** Transition capture moder bit field reset value */
#define CSL_GPTIMER_TCLR_TCM_RESETVAL    (0x00000000u)
/** Token for no signal capture */
#define CSL_GPTIMER_TCLR_TCM_NOCAPT      (0x00000000u)
/** Token for signal capture on low to high transition*/
#define CSL_GPTIMER_TCLR_TCM_CAPTONLOWTOHIGH (0x00000001u)
/** Token for signal capture on high to low transition*/
#define CSL_GPTIMER_TCLR_TCM_CAPTONHIGHTOLOW (0x00000002u)
/** Token for signal capture on either transition*/
#define CSL_GPTIMER_TCLR_TCM_CAPTONBOTH  (0x00000003u)

/** Set/clear PWM  bit field mask */
#define CSL_GPTIMER_TCLR_SCPWM_MASK      (0x00000080u)
/** Set/clear PWM  bit field shift */
#define CSL_GPTIMER_TCLR_SCPWM_SHIFT     (0x00000007u)
/** Set/clear PWM  bit field reset value */
#define CSL_GPTIMER_TCLR_SCPWM_RESETVAL  (0x00000000u)
/** Token to clear the PWM signal */ 
#define CSL_GPTIMER_TCLR_SCPWM_CLEAR     (0x00000000u)
/** Token to set the PWM signal */
#define CSL_GPTIMER_TCLR_SCPWM_SET       (0x00000001u)

/** compare enable bit field mask */
#define CSL_GPTIMER_TCLR_CE_MASK         (0x00000040u)
/** compare enable bit field shift */
#define CSL_GPTIMER_TCLR_CE_SHIFT        (0x00000006u)
/** compare enable bit field reset value */
#define CSL_GPTIMER_TCLR_CE_RESETVAL     (0x00000000u)
/** Token to disable compare mode */
#define CSL_GPTIMER_TCLR_CE_DISABLE      (0x00000000u)
/** Token to enable compare mode */
#define CSL_GPTIMER_TCLR_CE_ENABLE       (0x00000001u)

/** Prescale enable bit field mask */
#define CSL_GPTIMER_TCLR_PRE_MASK        (0x00000020u)
/** Prescale enable bit field shift */
#define CSL_GPTIMER_TCLR_PRE_SHIFT       (0x00000005u)
/** Prescale enable bit field reset value */
#define CSL_GPTIMER_TCLR_PRE_RESETVAL    (0x00000000u)
/** Token to disable prescaling */
#define CSL_GPTIMER_TCLR_PRE_DISABLE     (0x00000000u)
/** Token to enable prescaling */
#define CSL_GPTIMER_TCLR_PRE_ENABLE      (0x00000001u)

/** Prescale value bit field mask */
#define CSL_GPTIMER_TCLR_PTV_MASK        (0x0000001Cu)
/** Prescale value bit field shift */
#define CSL_GPTIMER_TCLR_PTV_SHIFT       (0x00000002u)
/** Prescale value bit field reset value */
#define CSL_GPTIMER_TCLR_PTV_RESETVAL    (0x00000000u)
/** Select divide by 2 for prescaling */
#define CSL_GPTIMER_TCLR_PTV_CLKBY2      (0x00000000u)
/** Select divide by 4 for prescaling */
#define CSL_GPTIMER_TCLR_PTV_CLKBY4      (0x00000001u)
/** Select divide by 8 for prescaling */
#define CSL_GPTIMER_TCLR_PTV_CLKBY8      (0x00000002u)
/** Select divide by 16 for prescaling */
#define CSL_GPTIMER_TCLR_PTV_CLKBY16     (0x00000003u)
/** Select divide by 32 for prescaling */
#define CSL_GPTIMER_TCLR_PTV_CLKBY32     (0x00000004u)
/** Select divide by 64 for prescaling */
#define CSL_GPTIMER_TCLR_PTV_CLKBY64     (0x00000005u)
/** Select divide by 128 for prescaling */
#define CSL_GPTIMER_TCLR_PTV_CLKBY128    (0x00000006u)
/** Select divide by 256 for prescaling */
#define CSL_GPTIMER_TCLR_PTV_CLKBY256    (0x00000007u)

/** Auto reload bit field mask */
#define CSL_GPTIMER_TCLR_AR_MASK         (0x00000002u)
/** Auto reload bit field shift */
#define CSL_GPTIMER_TCLR_AR_SHIFT        (0x00000001u)
/** Auto reload bit field reset value */
#define CSL_GPTIMER_TCLR_AR_RESETVAL     (0x00000000u)
/** Token for selecting one shot mode */
#define CSL_GPTIMER_TCLR_AR_ONESHOT      (0x00000000u)
/** Token for selecting autoreload mode */
#define CSL_GPTIMER_TCLR_AR_AUTORELOAD   (0x00000001u)

/** Start bit field mask */
#define CSL_GPTIMER_TCLR_ST_MASK         (0x00000001u)
/** Start bit field shift */
#define CSL_GPTIMER_TCLR_ST_SHIFT        (0x00000000u)
/** Start bit field reset value */
#define CSL_GPTIMER_TCLR_ST_RESETVAL     (0x00000000u)
/** Token to stop the timer */
#define CSL_GPTIMER_TCLR_ST_STOP         (0x00000000u)
/** Token to stop the timer */
#define CSL_GPTIMER_TCLR_ST_START        (0x00000001u)

/** Reset value for TCLR */
#define CSL_GPTIMER_TCLR_RESETVAL        (0x00000000u)

/** TCRR */
/** TCRR register mask */
#define CSL_GPTIMER_TCRR_TIME_COUNTER_MASK (0xFFFFFFFFu)
/** TCRR register shift */
#define CSL_GPTIMER_TCRR_TIME_COUNTER_SHIFT (0x00000000u)
/** TCRR register reset value */
#define CSL_GPTIMER_TCRR_TIME_COUNTER_RESETVAL (0x00000000u)
/** Reset value for the TCRR register */
#define CSL_GPTIMER_TCRR_RESETVAL        (0x00000000u)

/** TLDR */
/** TLDR register mask */
#define CSL_GPTIMER_TLDR_TIME_VALUE_MASK (0xFFFFFFFFu)
/** TLDR register shift */
#define CSL_GPTIMER_TLDR_TIME_VALUE_SHIFT (0x00000000u)
/** TLDR register reset value */
#define CSL_GPTIMER_TLDR_TIME_VALUE_RESETVAL (0x00000000u)
/** Reset value for the TLDR register */
#define CSL_GPTIMER_TLDR_RESETVAL        (0x00000000u)

/** TTGR */
/** TTGR register mask */
#define CSL_GPTIMER_TTGR_TTGR_VALUE_MASK (0xFFFFFFFFu)
/** TTGR register shift */
#define CSL_GPTIMER_TTGR_TTGR_VALUE_SHIFT (0x00000000u)
/** TTGR register reset value */
#define CSL_GPTIMER_TTGR_TTGR_VALUE_RESETVAL (0x00000000u)
/** Reset value for the TTGR register */
#define CSL_GPTIMER_TTGR_RESETVAL        (0x00000000u)

/** TWPS */
/** TMAR write pend status bit field mask*/
#define CSL_GPTIMER_TWPS_W_PEND_TMAR_MASK (0x00000010u)
/** TMAR write pend status bit field shift*/
#define CSL_GPTIMER_TWPS_W_PEND_TMAR_SHIFT (0x00000004u)
/** TMAR write pend status bit field reset value*/
#define CSL_GPTIMER_TWPS_W_PEND_TMAR_RESETVAL (0x00000000u)

/** TTGR write pend status bit field mask*/
#define CSL_GPTIMER_TWPS_W_PEND_TTGR_MASK (0x00000008u)
/** TTGR write pend status bit field shift*/
#define CSL_GPTIMER_TWPS_W_PEND_TTGR_SHIFT (0x00000003u)
/** TTGR write pend status bit field reset value*/
#define CSL_GPTIMER_TWPS_W_PEND_TTGR_RESETVAL (0x00000000u)

/** TLDR write pend status bit field mask*/
#define CSL_GPTIMER_TWPS_W_PEND_TLDR_MASK (0x00000004u)
/** TLDR write pend status bit field shift*/
#define CSL_GPTIMER_TWPS_W_PEND_TLDR_SHIFT (0x00000002u)
/** TLDR write pend status bit field reset value*/
#define CSL_GPTIMER_TWPS_W_PEND_TLDR_RESETVAL (0x00000000u)

/** TCRR write pend status bit field mask*/
#define CSL_GPTIMER_TWPS_W_PEND_TCRR_MASK (0x00000002u)
/** TCRR write pend status bit field shift*/
#define CSL_GPTIMER_TWPS_W_PEND_TCRR_SHIFT (0x00000001u)
/** TCRR write pend status bit field reset value*/
#define CSL_GPTIMER_TWPS_W_PEND_TCRR_RESETVAL (0x00000000u)

/** TCLR write pend status bit field mask*/
#define CSL_GPTIMER_TWPS_W_PEND_TCLR_MASK (0x00000001u)
/** TCLR write pend status bit field shift*/
#define CSL_GPTIMER_TWPS_W_PEND_TCLR_SHIFT (0x00000000u)
/** TCLR write pend status bit field reset value*/
#define CSL_GPTIMER_TWPS_W_PEND_TCLR_RESETVAL (0x00000000u)

/** Write pend status register reset value*/
#define CSL_GPTIMER_TWPS_RESETVAL        (0x00000000u)

/** TMAR */
/** TMAR register mask */
#define CSL_GPTIMER_TMAR_COMPARE_VALUE_MASK (0xFFFFFFFFu)
/** TMAR register shift */
#define CSL_GPTIMER_TMAR_COMPARE_VALUE_SHIFT (0x00000000u)
/** TMAR register reset value */
#define CSL_GPTIMER_TMAR_COMPARE_VALUE_RESETVAL (0x00000000u)
/** Reset value for the TMAR register */
#define CSL_GPTIMER_TMAR_RESETVAL        (0x00000000u)

/** TCAR */
/** TCAR register mask */
#define CSL_GPTIMER_TCAR_CAPTURED_VALUE_MASK (0xFFFFFFFFu)
/** TCAR register shift */
#define CSL_GPTIMER_TCAR_CAPTURED_VALUE_SHIFT (0x00000000u)
/** TCAR register reset value */
#define CSL_GPTIMER_TCAR_CAPTURED_VALUE_RESETVAL (0x00000000u)
/** Reset value for the TCAR register */
#define CSL_GPTIMER_TCAR_RESETVAL        (0x00000000u)

/** TSICR */

/** Posted mode bit field mask */
#define CSL_GPTIMER_TSICR_POSTED_MASK    (0x00000004u)
/** Posted mode bit field shift */
#define CSL_GPTIMER_TSICR_POSTED_SHIFT   (0x00000002u)
/** Posted mode bit filed reset value */
#define CSL_GPTIMER_TSICR_POSTED_RESETVAL (0x00000001u)
/** Token to select non posted mode*/
#define CSL_GPTIMER_TSICR_POSTED_INACTIVE (0x00000000u)
/** Token to slect posted mode*/
#define CSL_GPTIMER_TSICR_POSTED_ACTIVE  (0x00000001u)

/** software reset bit field mask */
#define CSL_GPTIMER_TSICR_SFT_MASK       (0x00000002u)
/** Software reset bit field shift */
#define CSL_GPTIMER_TSICR_SFT_SHIFT      (0x00000001u)
/** Software reset bit field reset value */
#define CSL_GPTIMER_TSICR_SFT_RESETVAL   (0x00000000u)
/** Software reset is disabled */
#define CSL_GPTIMER_TSICR_SFT_DISABLE    (0x00000000u)
/** Software reset is enabled */
#define CSL_GPTIMER_TSICR_SFT_ENABLE     (0x00000001u)
/** TSICR register reset value */
#define CSL_GPTIMER_TSICR_RESETVAL       (0x00000004u)

#endif  /* _CSLR_GPTIMER_H_ */