cslr_gptimer.h

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/** ============================================================================
 *   @file  cslr_gptimer.h
 *
 *   @path  $(CSLPATH)\arm\gptimer\src
 *
 *   @desc  Register layer header file for the general purpose timer CSL on ARM 
 *          side
 *
 */

/*  ============================================================================
 *   Copyright (c) Texas Instruments Inc 2002, 2003, 2004
 *
 *   Use of this software is controlled by the terms and conditions found in the
 *   license agreement under which this software has been supplied.
 *   ===========================================================================
 */
 
/*  @(#) PSP/CSL 3.00.01.00[5912] (2004-06-02)  */

/* =============================================================================
 *  Revision History
 *  ================
 *  28-jun-2004 Ar Incoporated changes according to modified CSL architecture
 *  25-Apr-2004 Ar File Created.
 *
 * =============================================================================
 */

#ifndef _CSLR_GPTIMER_H_
#define _CSLR_GPTIMER_H_

#include <cslr.h>
#include <tistdtypes.h>

/**
 * Register Overlay Structure
 */
typedef struct  {
    /** Timer identification register */
    volatile Uint32 TIDR;
    const char RSVD0[12];
    /** Timer OCP configuration register */
    volatile Uint32 TIOCP_CFG;
    /** Timer system status register */
    volatile Uint32 TISTAT;
    /** Timer event status register */
    volatile Uint32 TISR;
    /** Timer Interrupt enable register */
    volatile Uint32 TIER;
    /** Timer wakeup enable register */
    volatile Uint32 TWER;
    /** Timer control register */
    volatile Uint32 TCLR;
    /** Timer counter register */
    volatile Uint32 TCRR;
    /** Timer load register */
    volatile Uint32 TLDR;
    /** Timer trigger register */
    volatile Uint32 TTGR;
    /** Timer write pending status register */
    volatile Uint32 TWPS;
    /** Timer match register */
    volatile Uint32 TMAR;
    /** Timer capture register */
    volatile Uint32 TCAR;
    /** Timer synchronization interface control register */
    volatile Uint32 TSICR;
} CSL_GptimerRegs;

/**
 * Overlay structure typedef definition
 */
typedef volatile CSL_GptimerRegs * CSL_GptimerRegsOvly;

/**************************************************************************\
* Register Id's
\**************************************************************************/
typedef enum  {
   /** Timer identification register ID*/
   CSL_GPTIMER_TIDR = 0x0000u,
   /** Timer OCP configuration register ID*/
   CSL_GPTIMER_TIOCP_CFG = 0x0010u,
   /** Timer system status register ID*/
   CSL_GPTIMER_TISTAT = 0x0014u,
   /** Timer event status register ID*/
   CSL_GPTIMER_TISR = 0x0018u,
   /** Timer interrupt enable register ID*/
   CSL_GPTIMER_TIER = 0x001cu,
   /** Timer wakeup enable register ID*/
   CSL_GPTIMER_TWER = 0x0020u,
   /** Timer control register ID */
   CSL_GPTIMER_TCLR = 0x0024u,
   /** Timer counter register ID*/
   CSL_GPTIMER_TCRR = 0x0028u,
   /** Timer load register ID*/
   CSL_GPTIMER_TLDR = 0x002cu,
   /** Timer trigger register ID*/
   CSL_GPTIMER_TTGR = 0x0030u,
   /** Timer write pending status register ID*/
   CSL_GPTIMER_TWPS = 0x0034u,
   /** Timer match register ID*/
   CSL_GPTIMER_TMAR = 0x0038u,
   /** Timer capture register ID*/
   CSL_GPTIMER_TCAR = 0x003cu,
   /** Timer synchronization interface control register ID*/
   CSL_GPTIMER_TSICR = 0x0040u
} CSL_GptimerRegIds;

/**************************************************************************\
* Field Definition Macros
\**************************************************************************/

/** TIDR */
/** REV field mask */
#define CSL_GPTIMER_TIDR_TID_REV_MASK    (0x000000FFu)
/** REV field shift */
#define CSL_GPTIMER_TIDR_TID_REV_SHIFT   (0x00000000u)
/** REV field reset value */
#define CSL_GPTIMER_TIDR_TID_REV_RESETVAL (0x00000000u)
/** TIDR register reset value */
#define CSL_GPTIMER_TIDR_RESETVAL        (0x00000000u)

/** TIOCP_CFG */

/** EMUFREE field mask */
#define CSL_GPTIMER_TIOCP_CFG_EMUFREE_MASK (0x00000020u)
/** EMUFREE field shift */
#define CSL_GPTIMER_TIOCP_CFG_EMUFREE_SHIFT (0x00000005u)
/** EMUFREE field reset value */
#define CSL_GPTIMER_TIOCP_CFG_EMUFREE_RESETVAL (0x00000000u)
/** Token to disable EMUFREE  */
#define CSL_GPTIMER_TIOCP_CFG_EMUFREE_DISABLE (0x00000000u)
/** Token to enable EMUFREE  */
#define CSL_GPTIMER_TIOCP_CFG_EMUFREE_ENABLE (0x00000001u)

/** Idle mode field mask */
#define CSL_GPTIMER_TIOCP_CFG_IDLEMODE_MASK (0x00000018u)
/** Idle mode field shift */
#define CSL_GPTIMER_TIOCP_CFG_IDLEMODE_SHIFT (0x00000003u)
/** Idle mode field reset value */
#define CSL_GPTIMER_TIOCP_CFG_IDLEMODE_RESETVAL (0x00000000u)
/** Token to select force-Idle for idle mode field */
#define CSL_GPTIMER_TIOCP_CFG_IDLEMODE_FORCEIDLE (0x00000000u)
/** Token to select NO-Idle for idle mode field */
#define CSL_GPTIMER_TIOCP_CFG_IDLEMODE_NOIDLE (0x00000001u)
/** Token to select smart-Idle for idle mode field */
#define CSL_GPTIMER_TIOCP_CFG_IDLEMODE_SMARTIDLE (0x00000002u)

/** Wakeup field mask */
#define CSL_GPTIMER_TIOCP_CFG_ENAWAKEUP_MASK (0x00000004u)
/** Wakeup field shift */
#define CSL_GPTIMER_TIOCP_CFG_ENAWAKEUP_SHIFT (0x00000002u)
/** Wakeup field reset value */
#define CSL_GPTIMER_TIOCP_CFG_ENAWAKEUP_RESETVAL (0x00000000u)
/** Token to enable Wakeup feature */
#define CSL_GPTIMER_TIOCP_CFG_ENAWAKEUP_DISABLE (0x00000000u)
/** Token to enable disable feature */
#define CSL_GPTIMER_TIOCP_CFG_ENAWAKEUP_ENABLE (0x00000001u)

/** Soft reset field mask */
#define CSL_GPTIMER_TIOCP_CFG_SOFTRESET_MASK (0x00000002u)
/** Soft reset field shift */
#define CSL_GPTIMER_TIOCP_CFG_SOFTRESET_SHIFT (0x00000001u)
/** Soft reset field reset value */
#define CSL_GPTIMER_TIOCP_CFG_SOFTRESET_RESETVAL (0x00000000u)
/** Set the soft reset bit */
#define CSL_GPTIMER_TIOCP_CFG_SOFTRESET_RESET (0x00000001u)

/** Auto idle bit field mask */
#define CSL_GPTIMER_TIOCP_CFG_AUTOIDLE_MASK (0x00000001u)
/** Auto idle bit field shift */
#define CSL_GPTIMER_TIOCP_CFG_AUTOIDLE_SHIFT (0x00000000u)
/** Auto idle bit field reset value */
#define CSL_GPTIMER_TIOCP_CFG_AUTOIDLE_RESETVAL (0x00000000u)
/** Token to set Auto idle as free running */
#define CSL_GPTIMER_TIOCP_CFG_AUTOIDLE_FREE (0x00000000u)
/** Token to enable auto idle */
#define CSL_GPTIMER_TIOCP_CFG_AUTOIDLE_AUTO (0x00000001u)

/** Reset value for TIOCP_CFG register */
#define CSL_GPTIMER_TIOCP_CFG_RESETVAL   (0x00000000u)

/** TISTAT */
/** Reset done field mask */
#define CSL_GPTIMER_TISTAT_RESETDONE_MASK (0x00000001u)
/** Reset done field shift */
#define CSL_GPTIMER_TISTAT_RESETDONE_SHIFT (0x00000000u)
/** Reset done field reset value */
#define CSL_GPTIMER_TISTAT_RESETDONE_RESETVAL (0x00000001u)

/** Reset value  for TISTAT register*/
#define CSL_GPTIMER_TISTAT_RESETVAL      (0x00000001u)

/** TISR */
/** Capture interrupt status field mask*/
#define CSL_GPTIMER_TISR_TCAR_IT_FLAG_MASK (0x00000004u)
/** Capture interrupt status field shift*/
#define CSL_GPTIMER_TISR_TCAR_IT_FLAG_SHIFT (0x00000002u)
/** Capture interrupt status field reset value*/
#define CSL_GPTIMER_TISR_TCAR_IT_FLAG_RESETVAL (0x00000000u)
/** Token to clear Capture interrupt status field*/
#define CSL_GPTIMER_TISR_TCAR_IT_FLAG_CLEAR (0x00000001u)

/** Overflow interrupt status field mask*/
#define CSL_GPTIMER_TISR_OVF_IT_FLAG_MASK (0x00000002u)
/** Overflow interrupt status field shift*/
#define CSL_GPTIMER_TISR_OVF_IT_FLAG_SHIFT (0x00000001u)
/** Overflow interrupt status field reset value*/
#define CSL_GPTIMER_TISR_OVF_IT_FLAG_RESETVAL (0x00000000u)
/** Token to clear overflow interrupt status field*/
#define CSL_GPTIMER_TISR_OVF_IT_FLAG_CLEAR (0x00000001u)

/** Match interrupt status field mask*/
#define CSL_GPTIMER_TISR_MAT_IT_FLAG_MASK (0x00000001u)
/** Match interrupt status field shift*/
#define CSL_GPTIMER_TISR_MAT_IT_FLAG_SHIFT (0x00000000u)
/** Match interrupt status field reset value*/
#define CSL_GPTIMER_TISR_MAT_IT_FLAG_RESETVAL (0x00000000u)
/** Token to clear Match interrupt status field*/
#define CSL_GPTIMER_TISR_MAT_IT_FLAG_CLEAR (0x00000001u)
/** Reset value for the TISR register */
#define CSL_GPTIMER_TISR_RESETVAL        (0x00000000u)

/** TIER */
/** Capture interrupt enable field mask*/
#define CSL_GPTIMER_TIER_TCAR_IT_ENA_MASK (0x00000004u)
/** Capture interrupt enable field shift*/
#define CSL_GPTIMER_TIER_TCAR_IT_ENA_SHIFT (0x00000002u)
/** Capture interrupt enable field reset value*/
#define CSL_GPTIMER_TIER_TCAR_IT_ENA_RESETVAL (0x00000000u)
/** Token to disable capture interrupt */
#define CSL_GPTIMER_TIER_TCAR_IT_ENA_DISABLE (0x00000000u)
/** Token to enable capture interrupt */
#define CSL_GPTIMER_TIER_TCAR_IT_ENA_ENABLE (0x00000001u)

/** Overflow interrupt enable field mask*/
#define CSL_GPTIMER_TIER_OVF_IT_ENA_MASK (0x00000002u)
/** Overflow interrupt enable field shift*/
#define CSL_GPTIMER_TIER_OVF_IT_ENA_SHIFT (0x00000001u)
/** Overflow interrupt enable field reset value*/
#define CSL_GPTIMER_TIER_OVF_IT_ENA_RESETVAL (0x00000000u)
/** Token to disable overflow interrupt */
#define CSL_GPTIMER_TIER_OVF_IT_ENA_DISABLE (0x00000000u)
/** Token to enable overflow interrupt */
#define CSL_GPTIMER_TIER_OVF_IT_ENA_ENABLE (0x00000001u)

/** Match interrupt enable field mask*/
#define CSL_GPTIMER_TIER_MAT_IT_ENA_MASK (0x00000001u)
/** Match interrupt enable field shift*/
#define CSL_GPTIMER_TIER_MAT_IT_ENA_SHIFT (0x00000000u)
/** Match interrupt enable field reset value*/
#define CSL_GPTIMER_TIER_MAT_IT_ENA_RESETVAL (0x00000000u)
/** Token to disable match interrupt */
#define CSL_GPTIMER_TIER_MAT_IT_ENA_DISABLE (0x00000000u)
/** Token to enable match interrupt */
#define CSL_GPTIMER_TIER_MAT_IT_ENA_ENABLE (0x00000001u)
/** Reset value for TIER register */
#define CSL_GPTIMER_TIER_RESETVAL        (0x00000000u)

/** TWER */
/** Capture wakeup enable field mask*/
#define CSL_GPTIMER_TWER_TCAR_WUP_ENA_MASK (0x00000004u)
/** Capture wakeup enable field shift*/
#define CSL_GPTIMER_TWER_TCAR_WUP_ENA_SHIFT (0x00000002u)
/** Capture wakeup enable field reset value*/
#define CSL_GPTIMER_TWER_TCAR_WUP_ENA_RESETVAL (0x00000000u)
/** Token to disable wakeup on capture */