csl_cache.h

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/** ==========================================================================
 *   @file  csl_cache.h
 *
 *   @path  $(CSLPATH)\arm\cache\src
 *
 *   @desc  API header file for Cache CSL
 *
 */
 
 /*  ===========================================================================
 *   Copyright (c) Texas Instruments Inc 2002, 2003, 2004
 *
 *   Use of this software is controlled by the terms and conditions found in 
 *   the license agreement under which this software has been supplied.
 *   ==========================================================================
 */
  
/*  @(#) PSP/CSL 3.00.01.00[5912] (2004-05-27)  */

/* ===========================================================================
 *  Revision History
 *  ===============
 *  06-Jul-2004  rr  Made modifications to support changes in CSL architecture
 *  24-may-2004  ar  Changed the enumeration value name from CSL_CACHE_ANY to
 *                   CSL_CACHE_PER_ANY
 *  18-may-2004  ar  Added enumeration for cache instance,
 *                   added instance number to the argument list of 
 *                   prototype for CSL_cacheOpen
 *  06-may-2004  ar  File Created.
 * =============================================================================
 */

#ifndef _CSL_CACHE_H_
#define _CSL_CACHE_H_

#ifdef __cplusplus
extern "C" {
#endif

#include <csl.h>

/**Starting Error code for Cache module  */
#define CSL_ECACHE_FIRST    -( ((CSL_CACHE_ID + 1) << 5 ) + 1 )

/**
 * Error code returned by CSL_CACHE_CMD_TEST_AND_CLEAN command 
 * if no dirty lines are found
 */
#define CSL_ECACHE_NODIRTYLINE   (CSL_ECACHE_FIRST - 1)

/**
 *  Cache global typedef declarations 
 */

/**
 * Enumeration for Cache Control commands
 */
typedef enum {
    /**
     * @brief Enable cache 
     * @param ( CSL_CacheType *) 
     */
    CSL_CACHE_CMD_ENABLE                             = 0,
    /** 
     * @brief Disable cache 
     * @param ( CSL_CacheType *) 
     */
    CSL_CACHE_CMD_DISABLE                            = 1,
    /** 
    * @brief Invalidate cache 
    * @param ( CSL_CacheType * ) 
    */
    CSL_CACHE_CMD_INVALIDATE                         = 2, 
    /** 
    * @brief Invalidate cache line 
    * @param ( CSL_CacheLineInvAddr * )
    */
    CSL_CACHE_CMD_INVLINE_ADDR                       = 3,
    /** 
    * @brief Invalidate cache line 
    * @param ( CSL_CacheLineInvSetWay * )
    */
    CSL_CACHE_CMD_INVLINE_SETWAY                     = 4,
    /** 
    * @brief Prefetch instruction into cache 
    * @param ( Uint32)
    */
    CSL_CACHE_CMD_INS_PREFETCH                       = 5,
    /** 
    * @brief Clean data cache line 
    * @param ( Uint32 * )
    */
    CSL_CACHE_CMD_CLEAN_ADDR                         = 6,
    /** 
    * @brief Clean data cache line 
    * @param ( CSL_CacheLineCleanAddr *)
    */
    CSL_CACHE_CMD_CLEAN_SETWAY                       = 7,
    /** 
    * @brief Clean data cache line 
    * @param ( CSL_CacheLineCleanSetWay *)
    */
    CSL_CACHE_CMD_TEST_AND_CLEAN                     = 8,
    /** 
    * @brief Test clean and invalidate 
    * @param ( CSL_CacheWayLockDesc * )
    */
    CSL_CACHE_CMD_CACHEWAY_LOCK                      = 9,
    /** 
    * @brief Lock cache way 
    * @param ( CSL_CacheWayLockDesc * )
    */
    CSL_CACHE_CMD_CACHEWAY_UNLOCK                    = 10,
    /** 
    * @brief Unlock cache way 
    * @param ( Bool * )
    */
    CSL_CACHE_CMD_DRAIN                              = 11
} CSL_CacheHwControlCmd;

/**
 *  Enumeration for Query Query commands
 */
typedef enum {
    /** 
    * @brief Get information about cache organization 
    * @param ( Uint32 *) 
    */
    CSL_CACHE_QUERY_INFO                          = 0,
    /** 
    * @brief Query Instruction cache status
    * @param ( Bool *) 
    */
    CSL_CACHE_QUERY_ICACHE_STATUS                 = 1,
    /** 
    * @brief Query data cache status
    * @param ( Bool *)
    */
    CSL_CACHE_QUERY_DCACHE_STATUS                 = 2,
    /** 
    * @brief Query instruction cache lock status
    * @param ( Uint32 *) 
    */
    CSL_CACHE_QUERY_ICACHE_LOCK_STATUS            = 3,
    /** 
    * @brief Query data cache lock status
    * @param ( Uint32 *) 
    */
    CSL_CACHE_QUERY_DCACHE_LOCK_STATUS            = 4
 } CSL_CacheHwStatusQuery;

/**
 *  Enumeration for cache type
 */
typedef enum {
    /** Both instruction cache and data cache */
    CSL_CACHE_INSTR_AND_DATA           = 0,
    /** Instruction cache */
    CSL_CACHE_INSTR                    = 1,
    /** data cache */   
    CSL_CACHE_DATA                     = 2
} CSL_CacheType;

/**
 *  Enumeration for cache ways
 */
typedef enum {
    /** cache way 0 */
    CSL_CACHE_WAY_0           = 1,
    /** cache way 1 */
    CSL_CACHE_WAY_1           = 2,
    /** cache way 2 */
    CSL_CACHE_WAY_2           = 4,
    /** cache way 3 */
    CSL_CACHE_WAY_3           = 8
} CSL_CacheWay;

/**
 *  Structure used to pass virtual address for invalidating cache 
 */
typedef struct CSL_CacheLineInvAddr {
    /** cache type  */
     CSL_CacheType           type;
    /** Virtual address of cached line */
     Uint32                  virtAddress;  
} CSL_CacheLineInvAddr;

/**
 *  Structure used to pass set and way for invalidating cache 
 */
typedef struct CSL_CacheLineInvSetWay {
     /** Cache type */
     CSL_CacheType           type;
     /** set number. valid range 0 to 3 */
     Uint16                  set;  
     /** way number. valid range 0 to 3 */
     Uint16                  way; 
} CSL_CacheLineInvSetWay;

/**
 *  Structure used to pass virtual address for cleaning data cache entry 
 */
typedef struct CSL_CacheLineCleanAddr {
     /** Whether to invalidate or not */
     Bool                    invalidate;
     /** Virtual address of cached line */
     Uint32                  virtAddress;  
} CSL_CacheLineCleanAddr;

/**
 *  Structure used to pass set and way for cleaning data cache entry 
 */
typedef struct CSL_CacheLineCleanSetWay {
     /** Whether to invalidate or not */
     Bool                    invalidate;
     /** set number. valid range 0 to 3 */
     Uint16                  set;  
     /** way number. valid range 0 to 3 */
     Uint16                  way; 
} CSL_CacheLineCleanSetWay;

/**
 *  Structure used to pass cache way information for lock and unlock operation 
 */
typedef struct CSL_CacheWayLockDesc {
    /** Cache type */
     CSL_CacheType           type;
    /** way number. valid range 0 to 3 */
     Uint16                  way;  
} CSL_CacheWayLockDesc;

/** 
 * CACHE data object This object contains the reference to the instance of 
 * CACHE opened using the @a CSL_cacheOpen().
 *
 * The pointer to this, is passed to all CACHE CSL APIs.
 */
typedef struct CSL_CacheObj {
	/** This is the instance of CACHE being referred to by this object  */
	CSL_InstNum  	perNum;
} CSL_CacheObj;

/** This will have the base-address information for the peripheral
 *  instance
 */
typedef struct {
	/** Base-address of the Configuration registers of the peripheral
	 */
	Uint32	regs;
} CSL_CacheBaseAddress;


/** Module specific parameters. Present implementation doesn't have
 *  any module specific parameters.
 */
typedef struct{
	/** Bit mask to be used for module specific parameters.
         *  The below declaration is just a place-holder for future