csl_dma_lcd.h
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#ifndef _CSL_DMA_LCD_H_#define _CSL_DMA_LCD_H_/*****************************************************\ * Copyright 2003, Texas Instruments Incorporated. * * All rights reserved. * * Restricted rights to use, duplicate or disclose * * this code are granted through contract. * * * * "@(#) PSP/CSL 3.0.0.0 (2003-09-30) *\*****************************************************//** @file csl_dma_lcd.h * * @brief Header file for functional layer CSL of LCD DMA * * Description * - The different enumerations, structure definitions * and function declarations * */#ifdef __cplusplusextern "C" {#endif#include <csl_types.h>#include <tistdtypes.h>#include <csl_error.h>#include <csl_dma.h>#include <cslr_dma.h>#include <csl_dma_global.h>/**************************************************************************\* DMA global macro declarations\**************************************************************************//** The default value for @a CSL_DmaLcdDstPort */#define CSL_DMA_LCD_DSTPORT_DEFAULTS { \ CSL_DMA_LCD_OMAP_LCD_CONTROLLER \ }/** The default value for @a CSL_DmaLcdSetupSrcPortBlock1 structure */#define CSL_DMA_LCD_SETUPSRCPORTBLOCK1_DEFAULTS { \ CSL_DMA_LCD_SINGLE_ACCESS, \ CSL_DMA_LCD_PACKED_ACCESS_DISABLE, \ CSL_DMA_LCD_AMODE_POST_INCREMENT, \ 0, \ 0, \ 0, \ 0 \ }/** The default value for @a CSL_DmaLcdSetupSrcPortBlock2 structure */#define CSL_DMA_LCD_SETUPSRCPORTBLOCK2_DEFAULTS { \ CSL_DMA_LCD_SINGLE_ACCESS, \ CSL_DMA_LCD_PACKED_ACCESS_DISABLE, \ CSL_DMA_LCD_AMODE_POST_INCREMENT, \ 0, \ 0, \ 0, \ 0 \ }/** The default value for @a CSL_DmaLcdSetupSrcPort structure */#define CSL_DMA_LCD_SETUPSRCPORT_DEFAULTS { \ CSL_DMA_LCD_PORT_SDRAM, \ NULL, \ NULL \ }/** The default value for @a CSL_DmaLcdSetupChaBlock1 structure */#define CSL_DMA_LCD_SETUPCHABLOCK1_DEFAULTS { \ CSL_DMA_LCD_DATASIZE_8BIT, \ 0, \ 0 \ }/** The default value for @a CSL_DmaLcdSetupChaBlock2 structure */#define CSL_DMA_LCD_SETUPCHABLOCK2_DEFAULTS { \ CSL_DMA_LCD_DATASIZE_8BIT, \ 0, \ 0 \ }/** The default value for @a CSL_DmaLcdSetupChaCtrl structure */#define CSL_DMA_LCD_SETUPCHACTRL_DEFAULTS { \ CSL_DMA_LCD_BS_DISABLE, \ CSL_DMA_LCD_PRIORITY_LOW, \ CSL_DMA_LCD_AUTOINIT_DISABLE, \ CSL_DMA_LCD_ENDPROG_DISABLE, \ CSL_DMA_LCD_REPEAT_DISABLE, \ CSL_DMA_LCD_OMAP31_COMPATABILITY, \ }/** The default value for @a CSL_DmaLcdSetupChannel structure */#define CSL_DMA_LCD_SETUPCHANNEL_DEFAULTS { \ NULL, \ CSL_DMA_LCDLCHCTRL_LCHTYPE_RESETVAL, \ CSL_DMA_LCDCTRL_BLOCKMODE_RESETVAL, \ NULL, \ NULL, \ NULL, \ NULL \ }/** The default value for @a CSL_DmaLcdHwSetup structure */#define CSL_DMA_LCD_HWSETUP_DEFAULTS { \ NULL, \ NULL, \ NULL, \ NULL \ }/**************************************************************************\* DMA global typedef declarations\**************************************************************************//** @brief Enumerations for LCD Channel instances** There is one instance of the LCD DMA channel*//** @brief Enumerations for DMA LCD operations** The DMA Operations are split, currently, into 3 groups of 16 each* The groups being Port Commands,Channel Commands and Global Commands* There might not be 16 commands for each group. The gaps are left* for future use for addition of new port,channel or global command** These enums are passed as parameters to @a CSL_dmaLcdHwControl() to indicate* the action to be performed. The comments on the right of the enum* value indicate the data type to be allocated by the user for the* corresponding command. The address of the allocated data type* should be passed as a parameter to @a CSL_dmaLcdHwControl()*/typedef enum { /** Port Commands */ CSL_DMA_LCD_CMD_CHANGE_BLOCK1_TOP_ADDR = 0, /**< @a Uint32 */ CSL_DMA_LCD_CMD_CHANGE_BLOCK1_BOTTOM_ADDR = 1, /**< @a Uint32 */ CSL_DMA_LCD_CMD_CHANGE_BLOCK2_TOP_ADDR = 2, /**< @a Uint32 */ CSL_DMA_LCD_CMD_CHANGE_BLOCK2_BOTTOM_ADDR = 3, /**< @a Uint32 */ CSL_DMA_LCD_CMD_CHANGE_BLOCK1_ELEMENT_INDEX = 4, /**< @a Int16 */ CSL_DMA_LCD_CMD_CHANGE_BLOCK2_ELEMENT_INDEX = 5, /**< @a Int16 */ CSL_DMA_LCD_CMD_CHANGE_BLOCK1_FRAME_INDEX = 6, /**< @a Int32 */ CSL_DMA_LCD_CMD_CHANGE_BLOCK2_FRAME_INDEX = 7, /**< @a Int32 */ CSL_DMA_LCD_CMD_CHANGE_BLOCK1_AMODE = 8, /**< @a #CSL_DmaLcdAmode */ CSL_DMA_LCD_CMD_CHANGE_BLOCK2_AMODE = 9, /**< @a #CSL_DmaLcdAmode */ CSL_DMA_LCD_CMD_CHANGE_BLOCK1_SETUP = 10, /**< @a #CSL_DmaLcdSetupSrcPortBlock */ CSL_DMA_LCD_CMD_CHANGE_BLOCK2_SETUP = 11, /**< @a #CSL_DmaLcdSetupSrcPortBlock */ CSL_DMA_LCD_CMD_CHANGE_SRC_PORT = 12, /**< @a #CSL_DmaLcdPort */ CSL_DMA_LCD_CMD_CHANGE_DST_PORT = 13, /**< @a #CSL_DmaLcdDstPort */ /** Channel Commands */ CSL_DMA_LCD_CMD_CHANGE_CHANNEL_CTRL_SETUP = 16, /**< @a CSL_DmaLcdSetupChaCtrl */ CSL_DMA_LCD_CMD_ENABLE_INT = 17, /**< @a Uint16 : bit-vector formed by bit-wise OR of @a #CSL_DmaLcdIntEvents data type */ CSL_DMA_LCD_CMD_DISABLE_INT = 18, /**< @a Uint16 : bit-vector formed by bit-wise OR of @a #CSL_DmaLcdIntEvents data type */ CSL_DMA_LCD_CMD_CHANGE_LCH_TYPE = 19, /**< @a #CSL_DmaLcdLchType */ CSL_DMA_LCD_CMD_CHANGE_BLOCK_MODE = 20, /**< @a #CSL_DmaLcdBlockMode */ CSL_DMA_LCD_CMD_CHANGE_BLOCK1_ELEMENT_COUNT = 21, /**< @a Uint16 */ CSL_DMA_LCD_CMD_CHANGE_BLOCK2_ELEMENT_COUNT = 22, /**< @a Uint16 */ CSL_DMA_LCD_CMD_CHANGE_BLOCK1_FRAME_COUNT = 23, /**< @a Uint16 */ CSL_DMA_LCD_CMD_CHANGE_BLOCK2_FRAME_COUNT = 24, /**< @a Uint16 */ CSL_DMA_LCD_CMD_CHANGE_BLOCK1_DATA_TYPE = 25, /**< @a #CSL_DmaLcdDataType */ CSL_DMA_LCD_CMD_CHANGE_BLOCK2_DATA_TYPE = 26, /**< @a #CSL_DmaLcdDataType */ CSL_DMA_LCD_CMD_ENABLE_CHANNEL = 28, /**< @a NULL */ CSL_DMA_LCD_CMD_DISABLE_CHANNEL = 29, /**< @a NULL */ CSL_DMA_LCD_CMD_CHANGE_CHANNEL_BLOCK1_SETUP = 30, /**< @a CSL_DmaLcdSetupChaBlock */ CSL_DMA_LCD_CMD_CHANGE_CHANNEL_BLOCK2_SETUP = 31, /**< @a CSL_DmaLcdSetupChaBlock */ /** Global Commands */ CSL_DMA_LCD_CMD_CHANGE_GLOBAL_CONTROL_SETUP = 32, /**< @a CSL_DmaSetupGlobalControl */ CSL_DMA_LCD_CMD_CHANGE_COMPAT_MODE = 33, /**< @a #CSL_DmaOmapCompatMode */ CSL_DMA_LCD_CMD_GLOBAL_RESET = 34 /**< @a #CSL_DmaSwReset */} CSL_DmaLcdControlCmd;/** @brief Enumerations for LCD DMA Status Query operations * * The DMA Operations are split, currently, into 3 groups of 16 each * The groups being Port Queries, Channel Queries and Global Queries * There might not be 16 queries for each group. The gaps are left * for future use for addition of new port,channel or global Queries * * These enums are passed as parameters to @a CSL_dmaLcdGetHwStatus() to indicate * the action to be performed. The comments on the right of the enum * value indicate the data type to be allocated by the user for the * corresponding command. The address of the allocated data type * should be passed as a parameter to @a CSL_dmaLcdGetHwStatus() */typedef enum { /* Port Queries */ CSL_DMA_LCD_QUERY_SRC_PORT_SETUP = 0, /**< @a CSL_DmaLcdSetupSrcPort */ CSL_DMA_LCD_QUERY_BLOCK1_SETUP = 1, /**< @a CSL_DmaLcdSetupSrcPortBlock */ CSL_DMA_LCD_QUERY_BLOCK2_SETUP = 2, /**< @a CSL_DmaLcdSetupSrcPortBlock */ /* Channel Queries */ CSL_DMA_LCD_QUERY_CHANNEL_SETUP = 16, /**< @a CSL_DmaLcdSetupChannel */ CSL_DMA_LCD_QUERY_CHA_CTRL_SETUP = 17, /**< @a CSL_DmaLcdSetupChaCtrl */ CSL_DMA_LCD_QUERY_CHA_BLOCK1_SETUP = 18, /**< @a CSL_DmaLcdSetupChaBlock */ CSL_DMA_LCD_QUERY_CHA_BLOCK2_SETUP = 19, /**< @a CSL_DmaLcdSetupChaBlock */ CSL_DMA_LCD_QUERY_INTERRUPT_STATUS = 20, /**< @a Uint16 : it is a bit-wise OR of the @a #CSL _DmaLcdIntStatusEvents data type */ /* Global Queries */ CSL_DMA_LCD_QUERY_GLOBAL_SETUP = 32, /**< @a CSL_DmaSetupGlobal */ CSL_DMA_LCD_QUERY_PCH_STATUS = 33, /**< @a CSL_DmaPchStatus */ CSL_DMA_LCD_QUERY_GLOBAL_ID = 34, /**< @a CSL_DmaGlobalId */ CSL_DMA_LCD_QUERY_GLOBAL_CONTROL_SETUP = 35, /**< @a CSL_DmaSetupGlobalControl */ CSL_DMA_LCD_QUERY_CAPABILITY = 37 /**< @a CSL_DmaCapability */} CSL_DmaLcdHwStatusQuery;/** @brief Enumerations for status of events which generate interrupts * */typedef enum { CSL_DMA_LCD_BLOCK1_EVENT_STATUS = CSL_FMK(DMA_LCDCTRL_B1ITCOND,1), /**< End of block1 int detected */ CSL_DMA_LCD_BLOCK2_EVENT_STATUS = CSL_FMK(DMA_LCDCTRL_B2ITCOND,1), /**< End of block2 int detected */ CSL_DMA_LCD_BUS_ERROR_EVENT_STATUS = CSL_FMK(DMA_LCDCTRL_BUSERRITCOND,1) /**< Bus error interrupt detected */} CSL_DmaLcdIntStatusEvents;/** @brief Enumerations for events which generate interrupts * */typedef enum { CSL_DMA_LCD_BLOCK_EVENT = CSL_FMK(DMA_LCDCTRL_BLOCKITIE,1), /**< Enable block int events for either block 1 or 2*/ CSL_DMA_LCD_BUS_ERROR_EVENT = CSL_FMK(DMA_LCDCTRL_BUSERRITIE,1) /**< Bus error interrupt enable */} CSL_DmaLcdIntEvents;/** @brief Type of block mode used for LCD transfers * */typedef enum { CSL_DMA_LCD_ONE_BLOCK_BUFFER = 0, /**< Only registers relative to block 1 are used */ CSL_DMA_LCD_TWO_BLOCK_BUFFER = 1 /**< LCD Channel alternately reads the two blocks */} CSL_DmaLcdBlockMode;/** @brief Enumerations of the logical channel assignment relationship to * physical channels and associated features * */typedef enum { LCHD_ASSIGNED_PCHD = 4 /**< LCh-D PCh-D : This is the only possible configuration */} CSL_DmaLcdLchType;/** @brief Enumerations for Element size * */typedef enum { CSL_DMA_LCD_DATASIZE_8BIT = 0, /**< 8 bits scalar */ CSL_DMA_LCD_DATASIZE_16BIT = 1, /**< 16 bits scalar */ CSL_DMA_LCD_DATASIZE_32BIT = 2 /**< 32 bits scalar */} CSL_DmaLcdDataType;/** @brief LCD Channel Setup Structure * */typedef struct CSL_DmaLcdSetupChaBlock { CSL_DmaLcdDataType datatype; /**< Size of data transferred in the Channels for the Block */ Uint16 elementCount; /**< Number of elements in a frame for the block */ Uint16 frameCount; /**< Number of frames for the block */} CSL_DmaLcdSetupChaBlock;/** @brief Setup Channel Block1 * */typedef struct CSL_DmaLcdSetupChaBlock CSL_DmaLcdSetupChaBlock1;/** @brief Setup Channel Block2 * */typedef struct CSL_DmaLcdSetupChaBlock CSL_DmaLcdSetupChaBlock2;
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