cslr_mcsi.h

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#define CSL_MCSI_INTS_REG_MSK_IT_TX_MASK (0x00000200u)
/** Mask of transmit interrupt bit field shift */
#define CSL_MCSI_INTS_REG_MSK_IT_TX_SHIFT (0x00000009u)
/** Mask of transmit interrupt bit filed reset value */
#define CSL_MCSI_INTS_REG_MSK_IT_TX_RESETVAL (0x00000000u)
/** Mask of transmit interrupt active */
#define CSL_MCSI_INTS_REG_MSK_IT_TX_ACTV (0x00000000u)
/** Mask of transmit interrupt inactive */
#define CSL_MCSI_INTS_REG_MSK_IT_TX_INACTV (0x00000001u)

/** Mask of receive interrupt bit field mask */
#define CSL_MCSI_INTS_REG_MSK_IT_RX_MASK (0x00000100u)
/** Mask of receive interrupt bit field shift */
#define CSL_MCSI_INTS_REG_MSK_IT_RX_SHIFT (0x00000008u)
/** Mask of receive interrupt bit field reset value */
#define CSL_MCSI_INTS_REG_MSK_IT_RX_RESETVAL (0x00000000u)
/** Mask of receive interrupt active */
#define CSL_MCSI_INTS_REG_MSK_IT_RX_ACTV (0x00000000u)
/** Mask of receive interrupt inactive */
#define CSL_MCSI_INTS_REG_MSK_IT_RX_INACTV (0x00000001u)

/** Channel for IT_TX mask */
#define CSL_MCSI_INTS_REG_CHAN_NO_IT_TX_MASK (0x000000F0u)
/** Channel for IT_TX shift */
#define CSL_MCSI_INTS_REG_CHAN_NO_IT_TX_SHIFT (0x00000004u)
/** Channel for IT_TX reset value */
#define CSL_MCSI_INTS_REG_CHAN_NO_IT_TX_RESETVAL (0x00000000u)
/** Channel number 0 for transmit interrupt generation */
#define CSL_MCSI_INTS_REG_CHAN_NO_IT_TX_NO0 (0x00000000u)
/** Channel number 1 for transmit interrupt generation */
#define CSL_MCSI_INTS_REG_CHAN_NO_IT_TX_NO1 (0x00000001u)
/** Channel number 2 for transmit interrupt generation */
#define CSL_MCSI_INTS_REG_CHAN_NO_IT_TX_NO2 (0x00000002u)
/** Channel number 3 for transmit interrupt generation */
#define CSL_MCSI_INTS_REG_CHAN_NO_IT_TX_NO3 (0x00000003u)
/** Channel number 4 for transmit interrupt generation */
#define CSL_MCSI_INTS_REG_CHAN_NO_IT_TX_NO4 (0x00000004u)
/** Channel number 5 for transmit interrupt generation */
#define CSL_MCSI_INTS_REG_CHAN_NO_IT_TX_NO5 (0x00000005u)
/** Channel number 6 for transmit interrupt generation */
#define CSL_MCSI_INTS_REG_CHAN_NO_IT_TX_NO6 (0x00000006u)
/** Channel number 7 for transmit interrupt generation */
#define CSL_MCSI_INTS_REG_CHAN_NO_IT_TX_NO7 (0x00000007u)
/** Channel number 8 for transmit interrupt generation */
#define CSL_MCSI_INTS_REG_CHAN_NO_IT_TX_NO8 (0x00000008u)
/** Channel number 9 for transmit interrupt generation */
#define CSL_MCSI_INTS_REG_CHAN_NO_IT_TX_NO9 (0x00000009u)
/** Channel number 10 for transmit interrupt generation */
#define CSL_MCSI_INTS_REG_CHAN_NO_IT_TX_NO10 (0x0000000Au)
/** Channel number 11 for transmit interrupt generation */
#define CSL_MCSI_INTS_REG_CHAN_NO_IT_TX_NO11 (0x0000000Bu)
/** Channel number 12 for transmit interrupt generation */
#define CSL_MCSI_INTS_REG_CHAN_NO_IT_TX_NO12 (0x0000000Cu)
/** Channel number 13 for transmit interrupt generation */
#define CSL_MCSI_INTS_REG_CHAN_NO_IT_TX_NO13 (0x0000000Du)
/** Channel number 14 for transmit interrupt generation */
#define CSL_MCSI_INTS_REG_CHAN_NO_IT_TX_NO14 (0x0000000Eu)
/** Channel number 15 for transmit interrupt generation */
#define CSL_MCSI_INTS_REG_CHAN_NO_IT_TX_NO15 (0x0000000Fu)

/** Channel for IT_RX mask */
#define CSL_MCSI_INTS_REG_CHAN_NO_IT_RX_MASK (0x0000000Fu)
/** Channel for IT_RX shift */
#define CSL_MCSI_INTS_REG_CHAN_NO_IT_RX_SHIFT (0x00000000u)
/** Channel for IT_RX reset value */                              
#define CSL_MCSI_INTS_REG_CHAN_NO_IT_RX_RESETVAL (0x00000000u)
/** Channel number 0 for receive interrupt generation */
#define CSL_MCSI_INTS_REG_CHAN_NO_IT_RX_NO0 (0x00000000u)
/** Channel number 1 for receive interrupt generation */
#define CSL_MCSI_INTS_REG_CHAN_NO_IT_RX_NO1 (0x00000001u)
/** Channel number 2 for receive interrupt generation */
#define CSL_MCSI_INTS_REG_CHAN_NO_IT_RX_NO2 (0x00000002u)
/** Channel number 3 for receive interrupt generation */
#define CSL_MCSI_INTS_REG_CHAN_NO_IT_RX_NO3 (0x00000003u)
/** Channel number 4 for receive interrupt generation */
#define CSL_MCSI_INTS_REG_CHAN_NO_IT_RX_NO4 (0x00000004u)
/** Channel number 5 for receive interrupt generation */
#define CSL_MCSI_INTS_REG_CHAN_NO_IT_RX_NO5 (0x00000005u)
/** Channel number 6 for receive interrupt generation */
#define CSL_MCSI_INTS_REG_CHAN_NO_IT_RX_NO6 (0x00000006u)
/** Channel number 7 for receive interrupt generation */
#define CSL_MCSI_INTS_REG_CHAN_NO_IT_RX_NO7 (0x00000007u)
/** Channel number 8 for receive interrupt generation */
#define CSL_MCSI_INTS_REG_CHAN_NO_IT_RX_NO8 (0x00000008u)
/** Channel number 9 for receive interrupt generation */
#define CSL_MCSI_INTS_REG_CHAN_NO_IT_RX_NO9 (0x00000009u)
/** Channel number 10 for receive interrupt generation */
#define CSL_MCSI_INTS_REG_CHAN_NO_IT_RX_NO10 (0x0000000Au)
/** Channel number 11 for receive interrupt generation */
#define CSL_MCSI_INTS_REG_CHAN_NO_IT_RX_NO11 (0x0000000Bu)
/** Channel number 12 for receive interrupt generation */
#define CSL_MCSI_INTS_REG_CHAN_NO_IT_RX_NO12 (0x0000000Cu)
/** Channel number 13 for receive interrupt generation */
#define CSL_MCSI_INTS_REG_CHAN_NO_IT_RX_NO13 (0x0000000Du)
/** Channel number 14 for receive interrupt generation */
#define CSL_MCSI_INTS_REG_CHAN_NO_IT_RX_NO14 (0x0000000Eu)
/** Channel number 15 for receive interrupt generation */
#define CSL_MCSI_INTS_REG_CHAN_NO_IT_RX_NO15 (0x0000000Fu)

/** Interrupt mask register reset value */
#define CSL_MCSI_INTS_REG_RESETVAL       (0x00000000u)

/** CHAN_USED_REG */

/** Channel selection bit field mask */
#define CSL_MCSI_CHAN_USED_REG_CHAN_MASK (0x00000001u)
/** Channel selection bit field shift */
#define CSL_MCSI_CHAN_USED_REG_CHAN_SHIFT (0x00000000u)
/** Channel selection bit field reset value */
#define CSL_MCSI_CHAN_USED_REG_CHAN_RESETVAL (0x00000000u)
/** Channel 0 */
#define CSL_MCSI_CHAN_USED_REG_CHAN_0    (0x00000001u)
/** Channel 1 */
#define CSL_MCSI_CHAN_USED_REG_CHAN_1    (0x00000002u)
/** Channel 2 */
#define CSL_MCSI_CHAN_USED_REG_CHAN_2    (0x00000004u)
/** Channel 3 */
#define CSL_MCSI_CHAN_USED_REG_CHAN_3    (0x00000008u)
/** Channel 4 */
#define CSL_MCSI_CHAN_USED_REG_CHAN_4    (0x00000010u)
/** Channel 5 */
#define CSL_MCSI_CHAN_USED_REG_CHAN_5    (0x00000020u)
/** Channel 6 */
#define CSL_MCSI_CHAN_USED_REG_CHAN_6    (0x00000040u)
/** Channel 7 */
#define CSL_MCSI_CHAN_USED_REG_CHAN_7    (0x00000080u)
/** Channel 8 */
#define CSL_MCSI_CHAN_USED_REG_CHAN_8    (0x00000100u)
/** Channel 9 */
#define CSL_MCSI_CHAN_USED_REG_CHAN_9    (0x00000200u)
/** Channel 10 */
#define CSL_MCSI_CHAN_USED_REG_CHAN_10   (0x00000400u)
/** Channel 11 */
#define CSL_MCSI_CHAN_USED_REG_CHAN_11   (0x00000800u)
/** Channel 12 */
#define CSL_MCSI_CHAN_USED_REG_CHAN_12   (0x00001000u)
/** Channel 13 */
#define CSL_MCSI_CHAN_USED_REG_CHAN_13   (0x00002000u)
/** Channel 14 */
#define CSL_MCSI_CHAN_USED_REG_CHAN_14   (0x00004000u)
/** Channel 15 */
#define CSL_MCSI_CHAN_USED_REG_CHAN_15   (0x00008000u)

/** Channel selection register reset value */
#define CSL_MCSI_CHAN_USED_REG_RESETVAL  (0x00000000u)

/** OVR_CLK_REG */

/** Reserved field mask */
#define CSL_MCSI_OVR_CLK_REG_RESVERED_MASK (0x0000FC00u)
/** Reserved field shift */
#define CSL_MCSI_OVR_CLK_REG_RESVERED_SHIFT (0x0000000Au)
/** Reserved field reset value */ 
#define CSL_MCSI_OVR_CLK_REG_RESVERED_RESETVAL (0x00000000u)

/** Overhead clock periods in frame duration field mask */
#define CSL_MCSI_OVR_CLK_REG_OVR_CLK_MASK (0x000003FFu)
/** Overhead clock periods in frame duration field shift */
#define CSL_MCSI_OVR_CLK_REG_OVR_CLK_SHIFT (0x00000000u)
/** Overhead clock periods in frame duration field reset value */
#define CSL_MCSI_OVR_CLK_REG_OVR_CLK_RESETVAL (0x00000000u)

/** Over sized frame dimension register reset value */
#define CSL_MCSI_OVR_CLK_REG_RESETVAL    (0x00000000u)

/** CLK_FREQ_REG */

/** Reserved field mask */
#define CSL_MCSI_CLK_FREQ_REG_RESVERED_MASK (0x0000F800u)
/** Reserved field shift */
#define CSL_MCSI_CLK_FREQ_REG_RESVERED_SHIFT (0x0000000Bu)
/** Reserved field reset value */
#define CSL_MCSI_CLK_FREQ_REG_RESVERED_RESETVAL (0x00000000u)

/** Clock frequency field mask */
#define CSL_MCSI_CLK_FREQ_REG_CLK_FREQ_MASK (0x000007FFu)
/** Clock frequency field shift */
#define CSL_MCSI_CLK_FREQ_REG_CLK_FREQ_SHIFT (0x00000000u)
/** Clock frequency field reset value */
#define CSL_MCSI_CLK_FREQ_REG_CLK_FREQ_RESETVAL (0x00000000u)

/** Clock frequency register reset value */
#define CSL_MCSI_CLK_FREQ_REG_RESETVAL   (0x00000000u)

/** STATUS_REG */

/** Reserved field mask */
#define CSL_MCSI_STATUS_REG_RESVERED_MASK (0x0000FF80u)
/** Reserved field shift */
#define CSL_MCSI_STATUS_REG_RESVERED_SHIFT (0x00000007u)
/** Reserved field reset value */
#define CSL_MCSI_STATUS_REG_RESVERED_RESETVAL (0x00000000u)

/** Status reserved bit field mask */
#define CSL_MCSI_STATUS_REG_RESVERED_STAT_MASK (0x00000040u)
/** Status reserved bit field shift */
#define CSL_MCSI_STATUS_REG_RESVERED_STAT_SHIFT (0x00000006u)
/** Status reserved bit field reset value */
#define CSL_MCSI_STATUS_REG_RESVERED_RESETVAL (0x00000000u)

/** Transmit underflow bit field mask */
#define CSL_MCSI_STATUS_REG_TX_UNDFLW_MASK (0x00000020u)
/** Transmit underflow bit field shift */
#define CSL_MCSI_STATUS_REG_TX_UNDFLW_SHIFT (0x00000005u)
/** Transmit underflow bit field reset value */
#define CSL_MCSI_STATUS_REG_TX_UNDFLW_RESETVAL (0x00000000u)
/** Token for no underflow  */
#define CSL_MCSI_STATUS_REG_TX_UNDFLW_NO_UNDFLW (0x00000000u)
/** Token for under flow */
#define CSL_MCSI_STATUS_REG_TX_UNDFLW_UNDFLW (0x00000001u)

/** Flag for transmit interrupt bit field mask */
#define CSL_MCSI_STATUS_REG_TX_RDY_MASK  (0x00000010u)
/** Flag for transmit interrupt bit field shift*/ 
#define CSL_MCSI_STATUS_REG_TX_RDY_SHIFT (0x00000004u)
/** Flag for transmit interrupt bit field reset value*/
#define CSL_MCSI_STATUS_REG_TX_RDY_RESETVAL (0x00000000u)
/** Token for no interrupt */
#define CSL_MCSI_STATUS_REG_TX_RDY_NO_INT (0x00000000u)
/** Token for interrupt */
#define CSL_MCSI_STATUS_REG_TX_RDY_INT   (0x00000001u)

/** Receive overflow bit field mask */
#define CSL_MCSI_STATUS_REG_RX_OVRFLW_MASK (0x00000008u)
/** Receive overflow bit field shift */
#define CSL_MCSI_STATUS_REG_RX_OVRFLW_SHIFT (0x00000003u)
/** Receive overflow bit field reset value */
#define CSL_MCSI_STATUS_REG_RX_OVRFLW_RESETVAL (0x00000000u)
/** Token for no overflow */
#define CSL_MCSI_STATUS_REG_RX_OVRFLW_NO_OVRFLW (0x00000000u)
/** Token for overflow */
#define CSL_MCSI_STATUS_REG_RX_OVRFLW_OVRFLW (0x00000001u)

/** Flag for receive interrupt bit filed mask */
#define CSL_MCSI_STATUS_REG_RX_RDY_MASK  (0x00000004u)
/** Flag for receive interrupt bit field shift */
#define CSL_MCSI_STATUS_REG_RX_RDY_SHIFT (0x00000002u)
/** Flag for receive interrupt bit field reset value */
#define CSL_MCSI_STATUS_REG_RX_RDY_RESETVAL (0x00000000u)
/** Token for no interrupt */
#define CSL_MCSI_STATUS_REG_RX_RDY_NO_INT (0x00000000u)
/** Token for interrupt */
#define CSL_MCSI_STATUS_REG_RX_RDY_INT   (0x00000001u)

/** Error type bit field mask */
#define CSL_MCSI_STATUS_REG_FRM_DUR_ERR_MASK (0x00000002u)
/** Error type bit field shift */
#define CSL_MCSI_STATUS_REG_FRM_DUR_ERR_SHIFT (0x00000001u)
/** Error type bit field reset value */
#define CSL_MCSI_STATUS_REG_FRM_DUR_ERR_RESETVAL (0x00000000u)
/** Error type short */
#define CSL_MCSI_STATUS_REG_FRM_DUR_ERR_SHORT (0x00000000u)
/** Error type long */
#define CSL_MCSI_STATUS_REG_FRM_DUR_ERR_LONG (0x00000001u)


/** Frame error bit field mask */
#define CSL_MCSI_STATUS_REG_FRM_ERR_MASK (0x00000001u)
/** Frame error bit field shift */
#define CSL_MCSI_STATUS_REG_FRM_ERR_SHIFT (0x00000000u)
/** Frame error bit field reset value */
#define CSL_MCSI_STATUS_REG_FRM_ERR_RESETVAL (0x00000000u)
/** Frame error correct */
#define CSL_MCSI_STATUS_REG_FRM_ERR_CORR (0x00000000u)
/** Frame error bad */
#define CSL_MCSI_STATUS_REG_FRM_ERR_BAD  (0x00000001u)

/** Interface status register reset value */
#define CSL_MCSI_STATUS_REG_RESETVAL     (0x00000000u)

/** TX_REG */

/** Transmit word bits' field mask */
#define CSL_MCSI_TX_REG_TX_MASK          (0x0000FFFFu)
/** Transmit word bits' field shift */
#define CSL_MCSI_TX_REG_TX_SHIFT         (0x00000000u)
/** Tranamit word bits' field reset value */
#define CSL_MCSI_TX_REG_TX_RESETVAL      (0x00000000u)

/** Transmit word register reset value */
#define CSL_MCSI_TX_REG_RESETVAL         (0x00000000u)

/** RX_REG */

/** Receive word bits' field mask */
#define CSL_MCSI_RX_REG_RX_MASK          (0x0000FFFFu)
/** Receive word bits' field shift */
#define CSL_MCSI_RX_REG_RX_SHIFT         (0x00000000u)
/** Receive word bits' field reset value */
#define CSL_MCSI_RX_REG_RX_RESETVAL      (0x00000000u)

/** Receive word register reset value */
#define CSL_MCSI_RX_REG_RESETVAL         (0x00000000u)

#ifdef __cplusplus
}
#endif

#endif  /* CSLR_MCSI_H_ */