cslr_mcsi.h

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/** ============================================================================
 *   @file  cslr_mcsi.h
 *
 *   @path  $(CSLPATH)\dsp\mcsi\inc
 *
 *   @desc  API header file for mcsi
 *
 */
 
/* =============================================================================
 *   Copyright (c) Texas Instruments Inc 2002, 2003, 2004
 *
 *   Use of this software is controlled by the terms and conditions found in the
 *   license agreement under which this software has been supplied.
 *  ============================================================================
 */

/*  @(#) PSP/CSL 3.00.01.00[5912] (2004-04-18)  */

/* =============================================================================
 *  Revision History
 *  ================
 *  05-Jul-2004 sp    Modifications done according to the new CSL architecture
 *  26-Apr-2004 Shiva File Created.
 *
 * =============================================================================
 */
 
#ifndef _CSLR_MCSI_H_
#define _CSLR_MCSI_H_

/***************5905PG1_0***************/

#include <cslr.h>
#include <tistdtypes.h>
#include <csl_types.h>

#ifdef __cplusplus
extern "C" {
#endif

/**
 * Register Overlay Structure
 */
typedef struct  {
    /** Activity control register */
    volatile Uint16 CNTL_REG;
    /** Main parameters register */
    volatile Uint16 MAIN_PARAMS_REG;
    /** Interrupt mask register */
    volatile Uint16 INTS_REG;
    /** Channel selection register */
    volatile Uint16 CHAN_USED_REG;
    /** Over sized frame dimension register */
    volatile Uint16 OVR_CLK_REG;
    /** Clock frequency register */
    volatile Uint16 CLK_FREQ_REG;
    /** Interface status register */
    volatile Uint16 STATUS_REG;
    const char RSVD0[25];
    /** Transmit word register */
    volatile Uint16 TX_REG[16];
    /** Receive word register */
    volatile Uint16 RX_REG[16];
} CSL_McsiRegs;

/** Overlay structure typedef definition */
typedef volatile ioport CSL_McsiRegs  * CSL_McsiRegsOvly;

/**
 * Register Id's
 */
typedef enum  {
    /** Activity control register offset */
    CSL_MCSI_CNTL_REG = 0x0000u,
    /** Main parameters register offset */
    CSL_MCSI_MAIN_PARAMS_REG = 0x0001u,
    /** Interrupt mask register offset */
    CSL_MCSI_INTS_REG = 0x0002u,
    /** Channel selection register offset */
    CSL_MCSI_CHAN_USED_REG = 0x0003u,
    /** Over sized frame dimension register offset */
    CSL_MCSI_OVR_CLK_REG = 0x0004u,
    /** Clock frequency register offset */
    CSL_MCSI_CLK_FREQ_REG = 0x0005u,
    /** Interface status register offset */
    CSL_MCSI_STATUS_REG = 0x0006u,
    /** Transmit word register offset */
    CSL_MCSI_TX_REG = 0x0020u,
    /** Receive word register offset */
    CSL_MCSI_RX_REG = 0x0030u
} CSL_McsiRegIds;

/**************************************************************************\
* Field Definition Macros
\**************************************************************************/

/** CNTL_REG */
/** Reserved bits' field mask */
#define CSL_MCSI_CNTL_REG_RESVERED_MASK  (0x0000FFF8u)
/** Reserved bits' field shift */
#define CSL_MCSI_CNTL_REG_RESVERED_SHIFT (0x00000003u)
/** Reserved bits' field reset value */
#define CSL_MCSI_CNTL_REG_RESVERED_RESETVAL (0x00000000u)

/** Reserved bit field 1 mask */
#define CSL_MCSI_CNTL_REG_RESVERED_1_MASK  (0x00000004u)
/** Reserved bit field 1 shift */
#define CSL_MCSI_CNTL_REG_RESVERED_1_SHIFT (0x00000002u)
/** Reserved bit field 1 reset value */
#define CSL_MCSI_CNTL_REG_RESVERED_RESETVAL (0x00000000u)

/** Software reset bit field mask */
#define CSL_MCSI_CNTL_REG_SFT_RST_MASK   (0x00000002u)
/** Software reset bit field shift */
#define CSL_MCSI_CNTL_REG_SFT_RST_SHIFT  (0x00000001u)
/** Software reset bit field reset value */
#define CSL_MCSI_CNTL_REG_SFT_RST_RESETVAL (0x00000000u)
/** Token to disable software reset */
#define CSL_MCSI_CNTL_REG_SFT_RST_DIS    (0x00000000u)
/** Token to enable software reset */
#define CSL_MCSI_CNTL_REG_SFT_RST_EN     (0x00000001u)

/** Clock enable bit field mask */
#define CSL_MCSI_CNTL_REG_CLK_EN_MASK    (0x00000001u)
/** Clock enable bit field shift */
#define CSL_MCSI_CNTL_REG_CLK_EN_SHIFT   (0x00000000u)
/** Clock enable reset value */
#define CSL_MCSI_CNTL_REG_CLK_EN_RESETVAL (0x00000000u)
/** Token to disable Clock */
#define CSL_MCSI_CNTL_REG_CLK_EN_DIS     (0x00000000u)
/** Token to enable Clock */
#define CSL_MCSI_CNTL_REG_CLK_EN_EN      (0x00000001u)

/** Activity control register reset value */
#define CSL_MCSI_CNTL_REG_RESETVAL       (0x00000000u)

/** MAIN_PARAMS_REG */

/** DMA enable bits' field mask */
#define CSL_MCSI_MAIN_PARAMS_REG_DMA_EN_MASK (0x0000C000u)
/** DMA enable bits' field shift */
#define CSL_MCSI_MAIN_PARAMS_REG_DMA_EN_SHIFT (0x0000000Eu)
/** DMA enable bits' field reset value */
#define CSL_MCSI_MAIN_PARAMS_REG_DMA_EN_RESETVAL (0x00000000u)
/** Token for Normal mode (no DMA) */
#define CSL_MCSI_MAIN_PARAMS_REG_DMA_EN_NODMA (0x00000000u)
/** Token for DMA transmit mode and normal receive mode */
#define CSL_MCSI_MAIN_PARAMS_REG_DMA_EN_RX (0x00000001u)
/** Token for Normal transmit mode and DMA receive mode */
#define CSL_MCSI_MAIN_PARAMS_REG_DMA_EN_TX (0x00000002u)
/** Token for DMA transmit and receive mode */
#define CSL_MCSI_MAIN_PARAMS_REG_DMA_EN_TX_RX (0x00000003u)

/** Reserved bits' field mask */
#define CSL_MCSI_MAIN_PARAMS_REG_RESVERED_MASK (0x00003800u)
/** Reserved bits' field shift */
#define CSL_MCSI_MAIN_PARAMS_REG_RESVERED_SHIFT (0x0000000Bu)
/** Reserved bits' field reset value */ 
#define CSL_MCSI_MAIN_PARAMS_REG_RESVERED_RESETVAL (0x00000000u)

/** Frame-synchronization pulse polarity mask */
#define CSL_MCSI_MAIN_PARAMS_REG_FSYNC_POL_MASK (0x00000400u)
/** Frame-synchronization pulse polarity shift */
#define CSL_MCSI_MAIN_PARAMS_REG_FSYNC_POL_SHIFT (0x0000000Au)
/** Frame-synchronization pulse polarity reset value */
#define CSL_MCSI_MAIN_PARAMS_REG_FSYNC_POL_RESETVAL (0x00000000u)
/** Frame-synchronization pulse polarity positive */
#define CSL_MCSI_MAIN_PARAMS_REG_FSYNC_POL_POS (0x00000000u)
/** Frame-synchronization pulse polarity negative */
#define CSL_MCSI_MAIN_PARAMS_REG_FSYNC_POL_NEG (0x00000001u)

/** Frame-synchronization pulse position mask */
#define CSL_MCSI_MAIN_PARAMS_REG_FSYNCH_MODE_MASK (0x00000200u)
/** Frame-synchronization pulse position shift */
#define CSL_MCSI_MAIN_PARAMS_REG_FSYNCH_MODE_SHIFT (0x00000009u)
/** Frame-synchronization pulse position reset value */
#define CSL_MCSI_MAIN_PARAMS_REG_FSYNCH_MODE_RESETVAL (0x00000000u)
/** Frame-synchronization pulse position normal */
#define CSL_MCSI_MAIN_PARAMS_REG_FSYNCH_MODE_NOR (0x00000000u)
/** Frame-synchronization pulse position alternate */
#define CSL_MCSI_MAIN_PARAMS_REG_FSYNCH_MODE_ALTR (0x00000001u)

/** Frame-synchronization pulse position mask */
#define CSL_MCSI_MAIN_PARAMS_REG_FSYNCH_SIZE_MASK (0x00000100u)
/** Frame-synchronization pulse position shift */
#define CSL_MCSI_MAIN_PARAMS_REG_FSYNCH_SIZE_SHIFT (0x00000008u)
/** Frame-synchronization pulse position reset value */
#define CSL_MCSI_MAIN_PARAMS_REG_FSYNCH_SIZE_RESETVAL (0x00000000u)
/** Frame-synchronization pulse position short */
#define CSL_MCSI_MAIN_PARAMS_REG_FSYNCH_SIZE_SHORT (0x00000000u)
/** Frame-synchronization pulse position long */
#define CSL_MCSI_MAIN_PARAMS_REG_FSYNCH_SIZE_LONG (0x00000001u)

/** Frame structure mask */
#define CSL_MCSI_MAIN_PARAMS_REG_FRM_STRUCT_MASK (0x00000080u)
/** Frame structure shift */
#define CSL_MCSI_MAIN_PARAMS_REG_FRM_STRUCT_SHIFT (0x00000007u)
/** Frame structure reset value */
#define CSL_MCSI_MAIN_PARAMS_REG_FRM_STRUCT_RESETVAL (0x00000000u)
/** Frame structure single */
#define CSL_MCSI_MAIN_PARAMS_REG_FRM_STRUCT_SINGLE (0x00000000u)
/** Multi Frame structure */
#define CSL_MCSI_MAIN_PARAMS_REG_FRM_STRUCT_MULTI (0x00000001u)

/** Interface transmission mode mask */
#define CSL_MCSI_MAIN_PARAMS_REG_MCSI_MODE_MASK (0x00000040u)
/** Interface transmission mode shift */
#define CSL_MCSI_MAIN_PARAMS_REG_MCSI_MODE_SHIFT (0x00000006u)
/** Interface transmission mode reset value */
#define CSL_MCSI_MAIN_PARAMS_REG_MCSI_MODE_RESETVAL (0x00000000u)
/** Interface transmission mode as slave */
#define CSL_MCSI_MAIN_PARAMS_REG_MCSI_MODE_SLA (0x00000000u)
/** Interface transmission mode as master */
#define CSL_MCSI_MAIN_PARAMS_REG_MCSI_MODE_MAS (0x00000001u)

/** Frame mode mask */
#define CSL_MCSI_MAIN_PARAMS_REG_FRM_MODE_MASK (0x00000020u)
/** Frame mode shift */
#define CSL_MCSI_MAIN_PARAMS_REG_FRM_MODE_SHIFT (0x00000005u)
/** Frame mode reset value */
#define CSL_MCSI_MAIN_PARAMS_REG_FRM_MODE_RESETVAL (0x00000000u)
/** Frame mode - Burst */
#define CSL_MCSI_MAIN_PARAMS_REG_FRM_MODE_BURST (0x00000000u)
/** Frame mode - Continuous */
#define CSL_MCSI_MAIN_PARAMS_REG_FRM_MODE_CONT (0x00000001u)

/** Clock edge selection mask */
#define CSL_MCSI_MAIN_PARAMS_REG_CLK_POL_MASK (0x00000010u)
/** Clock edge selection shift */
#define CSL_MCSI_MAIN_PARAMS_REG_CLK_POL_SHIFT (0x00000004u)
/** Clock edge selection reset value */
#define CSL_MCSI_MAIN_PARAMS_REG_CLK_POL_RESETVAL (0x00000000u)
/** Clock edge selection - positive */
#define CSL_MCSI_MAIN_PARAMS_REG_CLK_POL_POS (0x00000000u)
/** Clock edge selection - negative */
#define CSL_MCSI_MAIN_PARAMS_REG_CLK_POL_NEG (0x00000001u)

/** Word size bits' field mask */
#define CSL_MCSI_MAIN_PARAMS_REG_WORD_SIZE_MASK (0x0000000Fu)
/** Word size bits' field shift */
#define CSL_MCSI_MAIN_PARAMS_REG_WORD_SIZE_SHIFT (0x00000000u)
/** Word size bits' field reset value */
#define CSL_MCSI_MAIN_PARAMS_REG_WORD_SIZE_RESETVAL (0x00000000u)
/** Word size in bits number - 0 */
#define CSL_MCSI_MAIN_PARAMS_REG_WORD_SIZE_SIZE0 (0x00000000u)
/** Word size in bits number - 1 */ 
#define CSL_MCSI_MAIN_PARAMS_REG_WORD_SIZE_SIZE1 (0x00000040u)
/** Word size in bits number - 2 */
#define CSL_MCSI_MAIN_PARAMS_REG_WORD_SIZE_SIZE2 (0x00000040u)
/** Word size in bits number - 3 */
#define CSL_MCSI_MAIN_PARAMS_REG_WORD_SIZE_SIZE3 (0x00000040u)
/** Word size in bits number - 4 */
#define CSL_MCSI_MAIN_PARAMS_REG_WORD_SIZE_SIZE4 (0x00000040u)
/** Word size in bits number - 5 */
#define CSL_MCSI_MAIN_PARAMS_REG_WORD_SIZE_SIZE5 (0x00000041u)
/** Word size in bits number - 6 */
#define CSL_MCSI_MAIN_PARAMS_REG_WORD_SIZE_SIZE6 (0x00000048u)
/** Word size in bits number - 7 */
#define CSL_MCSI_MAIN_PARAMS_REG_WORD_SIZE_SIZE7 (0x00000049u)
/** Word size in bits number - 8 */
#define CSL_MCSI_MAIN_PARAMS_REG_WORD_SIZE_SIZE8 (0x000003E8u)
/** Word size in bits number - 9 */
#define CSL_MCSI_MAIN_PARAMS_REG_WORD_SIZE_SIZE9 (0x000003E9u)
/** Word size in bits number - 10 */
#define CSL_MCSI_MAIN_PARAMS_REG_WORD_SIZE_SIZE10 (0x000003F2u)
/** Word size in bits number - 11 */
#define CSL_MCSI_MAIN_PARAMS_REG_WORD_SIZE_SIZE11 (0x000003F3u)
/** Word size in bits number - 12 */
#define CSL_MCSI_MAIN_PARAMS_REG_WORD_SIZE_SIZE12 (0x0000044Cu)
/** Word size in bits number - 13 */
#define CSL_MCSI_MAIN_PARAMS_REG_WORD_SIZE_SIZE13 (0x0000044Du)
/** Word size in bits number - 14 */
#define CSL_MCSI_MAIN_PARAMS_REG_WORD_SIZE_SIZE14 (0x00000456u)
/** Word size in bits number - 15 */
#define CSL_MCSI_MAIN_PARAMS_REG_WORD_SIZE_SIZE15 (0x00000457u)

/** Main parameters register reset value */
#define CSL_MCSI_MAIN_PARAMS_REG_RESETVAL (0x00000000u)

/** INTS_REG */

/** Reserved field mask */
#define CSL_MCSI_INTS_REG_RESVERED_MASK  (0x0000F800u)
/** Reserved field shift */
#define CSL_MCSI_INTS_REG_RESVERED_SHIFT (0x0000000Bu)
/** Reserved field reset value */
#define CSL_MCSI_INTS_REG_RESVERED_RESETVAL (0x00000000u)

/** Mask of frame duration error interrupt, bit field mask */
#define CSL_MCSI_INTS_REG_MSK_IT_ERR_MASK (0x00000400u)
/** Mask of frame duration error interrupt, bit field shift */
#define CSL_MCSI_INTS_REG_MSK_IT_ERR_SHIFT (0x0000000Au)
/** Mask of frame duration error interrupt, bit field reset value */
#define CSL_MCSI_INTS_REG_MSK_IT_ERR_RESETVAL (0x00000000u)
/** Mask of frame duration error interrupt active */
#define CSL_MCSI_INTS_REG_MSK_IT_ERR_ACTV (0x00000000u)
/** Mask of frame duration error interrupt inactive */
#define CSL_MCSI_INTS_REG_MSK_IT_ERR_INACTV (0x00000001u)

/** Mask of transmit interrupt bit field mask */