cslr_gpio.h

dsp在音频处理中的运用

#ifndef _CSLR_GPIO_1_H_
#define _CSLR_GPIO_1_H_
/*********************************************************************
 * Copyright (C) 2003-2004 Texas Instruments Incorporated. 
 * All Rights Reserved 
 *********************************************************************/
 /** \file cslr_gpio_1.h
 * 
 * \brief This file contains the Register Desciptions for GPIO
 * 
 *********************************************************************/

#include <cslr.h>

#include <tistdtypes.h>

/**************************************************************************\
* Register Overlay Structure
\**************************************************************************/
typedef struct  {
    volatile Uint32 REVISION;
    volatile Uint8 RSVD0[12];
    volatile Uint32 SYSCONFIG;
    volatile Uint32 SYSSTATUS;
    volatile Uint32 IRQSTATUS1;
    volatile Uint32 IRQENABLE1;
    volatile Uint32 IRQSTATUS2;
    volatile Uint32 IRQENABLE2;
    volatile Uint32 WAKEUPENABLE;
    volatile Uint32 DATAIN;
    volatile Uint32 DATAOUT;
    volatile Uint32 DIRECTION;
    volatile Uint32 EDGE_CTRL1;
    volatile Uint32 EDGE_CTRL2;
    volatile Uint8 RSVD1[92];
    volatile Uint32 CLEAR_IRQENABLE1;
    volatile Uint8 RSVD2[4];
    volatile Uint32 CLEAR_IRQENABLE2;
    volatile Uint32 CLEAR_WAKEUPENA;
    volatile Uint8 RSVD3[4];
    volatile Uint32 CLEAR_DATAOUT;
    volatile Uint8 RSVD4[40];
    volatile Uint32 SET_IRQENABLE1;
    volatile Uint8 RSVD5[4];
    volatile Uint32 SET_IRQENABLE2;
    volatile Uint32 SET_WAKEUPENA;
    volatile Uint8 RSVD6[4];
    volatile Uint32 SET_DATAOUT;
} CSL_GpioRegs;

/**************************************************************************\
* Overlay structure typedef definition
\**************************************************************************/
typedef volatile CSL_GpioRegs  *CSL_GpioRegsOvly;

/**************************************************************************\
* Field Definition Macros
\**************************************************************************/

/* REVISION */

#define CSL_GPIO_REVISION_MAJOR_MASK     (0x000000F0u)
#define CSL_GPIO_REVISION_MAJOR_SHIFT    (0x00000004u)
#define CSL_GPIO_REVISION_MAJOR_RESETVAL (0x00000001u)

#define CSL_GPIO_REVISION_MINOR_MASK     (0x0000000Fu)
#define CSL_GPIO_REVISION_MINOR_SHIFT    (0x00000000u)
#define CSL_GPIO_REVISION_MINOR_RESETVAL (0x00000002u)

#define CSL_GPIO_REVISION_RESETVAL       (0x00000012u)

/* SYSCONFIG */

#define CSL_GPIO_SYSCONFIG_IDLEMODE_MASK (0x00000018u)
#define CSL_GPIO_SYSCONFIG_IDLEMODE_SHIFT (0x00000003u)
#define CSL_GPIO_SYSCONFIG_IDLEMODE_RESETVAL (0x00000000u)

#define CSL_GPIO_SYSCONFIG_ENAWAKEUP_MASK (0x00000004u)
#define CSL_GPIO_SYSCONFIG_ENAWAKEUP_SHIFT (0x00000002u)
#define CSL_GPIO_SYSCONFIG_ENAWAKEUP_RESETVAL (0x00000000u)

#define CSL_GPIO_SYSCONFIG_SOFTRESET_MASK (0x00000002u)
#define CSL_GPIO_SYSCONFIG_SOFTRESET_SHIFT (0x00000001u)
#define CSL_GPIO_SYSCONFIG_SOFTRESET_RESETVAL (0x00000000u)

#define CSL_GPIO_SYSCONFIG_AUTOIDLE_MASK (0x00000001u)
#define CSL_GPIO_SYSCONFIG_AUTOIDLE_SHIFT (0x00000000u)
#define CSL_GPIO_SYSCONFIG_AUTOIDLE_RESETVAL (0x00000000u)

#define CSL_GPIO_SYSCONFIG_RESETVAL      (0x00000000u)

/* SYSSTATUS */

#define CSL_GPIO_SYSSTATUS_RESETDONE_MASK (0x00000001u)
#define CSL_GPIO_SYSSTATUS_RESETDONE_SHIFT (0x00000000u)
#define CSL_GPIO_SYSSTATUS_RESETDONE_RESETVAL (0x00000000u)

#define CSL_GPIO_SYSSTATUS_RESETVAL      (0x00000000u)

/* IRQSTATUS1 */

#define CSL_GPIO_IRQSTATUS1_IRQSTS_MASK  (0x0000FFFFu)
#define CSL_GPIO_IRQSTATUS1_IRQSTS_SHIFT (0x00000000u)
#define CSL_GPIO_IRQSTATUS1_IRQSTS_RESETVAL (0x00000000u)

#define CSL_GPIO_IRQSTATUS1_RESETVAL     (0x00000000u)

/* IRQENABLE1 */

#define CSL_GPIO_IRQENABLE1_IRQEN_MASK   (0x0000FFFFu)
#define CSL_GPIO_IRQENABLE1_IRQEN_SHIFT  (0x00000000u)
#define CSL_GPIO_IRQENABLE1_IRQEN_RESETVAL (0x00000000u)

#define CSL_GPIO_IRQENABLE1_RESETVAL     (0x00000000u)

/* IRQSTATUS2 */

#define CSL_GPIO_IRQSTATUS2_IRQSTS_MASK  (0x0000FFFFu)
#define CSL_GPIO_IRQSTATUS2_IRQSTS_SHIFT (0x00000000u)
#define CSL_GPIO_IRQSTATUS2_IRQSTS_RESETVAL (0x00000000u)

#define CSL_GPIO_IRQSTATUS2_RESETVAL     (0x00000000u)

/* IRQENABLE2 */

#define CSL_GPIO_IRQENABLE2_IRQEN_MASK   (0x0000FFFFu)
#define CSL_GPIO_IRQENABLE2_IRQEN_SHIFT  (0x00000000u)
#define CSL_GPIO_IRQENABLE2_IRQEN_RESETVAL (0x00000000u)

#define CSL_GPIO_IRQENABLE2_RESETVAL     (0x00000000u)

/* WAKEUPENABLE */

#define CSL_GPIO_WAKEUPENABLE_WKUPEN_MASK (0x0000FFFFu)
#define CSL_GPIO_WAKEUPENABLE_WKUPEN_SHIFT (0x00000000u)
#define CSL_GPIO_WAKEUPENABLE_WKUPEN_RESETVAL (0x00000000u)

#define CSL_GPIO_WAKEUPENABLE_RESETVAL   (0x00000000u)

/* DATAIN */

#define CSL_GPIO_DATAIN_RXDATA_MASK      (0x0000FFFFu)
#define CSL_GPIO_DATAIN_RXDATA_SHIFT     (0x00000000u)
#define CSL_GPIO_DATAIN_RXDATA_RESETVAL  (0x00000000u)

#define CSL_GPIO_DATAIN_RESETVAL         (0x00000000u)

/* DATAOUT */

#define CSL_GPIO_DATAOUT_TXDATA_MASK     (0x0000FFFFu)
#define CSL_GPIO_DATAOUT_TXDATA_SHIFT    (0x00000000u)
#define CSL_GPIO_DATAOUT_TXDATA_RESETVAL (0x00000000u)

#define CSL_GPIO_DATAOUT_RESETVAL        (0x00000000u)

/* DIRECTION */

#define CSL_GPIO_DIRECTION_DIR_MASK      (0x0000FFFFu)
#define CSL_GPIO_DIRECTION_DIR_SHIFT     (0x00000000u)
#define CSL_GPIO_DIRECTION_DIR_RESETVAL  (0x0000FFFFu)

#define CSL_GPIO_DIRECTION_RESETVAL      (0x0000FFFFu)

/* EDGE_CTRL1 */

#define CSL_GPIO_EDGE_CTRL1_PIN8_MASK    (0x0000C000u)
#define CSL_GPIO_EDGE_CTRL1_PIN8_SHIFT   (0x0000000Eu)
#define CSL_GPIO_EDGE_CTRL1_PIN8_RESETVAL (0x00000000u)

#define CSL_GPIO_EDGE_CTRL1_PIN7_MASK    (0x00003000u)
#define CSL_GPIO_EDGE_CTRL1_PIN7_SHIFT   (0x0000000Cu)
#define CSL_GPIO_EDGE_CTRL1_PIN7_RESETVAL (0x00000000u)

#define CSL_GPIO_EDGE_CTRL1_PIN6_MASK    (0x00000C00u)
#define CSL_GPIO_EDGE_CTRL1_PIN6_SHIFT   (0x0000000Au)
#define CSL_GPIO_EDGE_CTRL1_PIN6_RESETVAL (0x00000000u)

#define CSL_GPIO_EDGE_CTRL1_PIN5_MASK    (0x00000300u)
#define CSL_GPIO_EDGE_CTRL1_PIN5_SHIFT   (0x00000008u)
#define CSL_GPIO_EDGE_CTRL1_PIN5_RESETVAL (0x00000000u)

#define CSL_GPIO_EDGE_CTRL1_PIN4_MASK    (0x000000C0u)
#define CSL_GPIO_EDGE_CTRL1_PIN4_SHIFT   (0x00000006u)
#define CSL_GPIO_EDGE_CTRL1_PIN4_RESETVAL (0x00000000u)

#define CSL_GPIO_EDGE_CTRL1_PIN3_MASK    (0x00000030u)
#define CSL_GPIO_EDGE_CTRL1_PIN3_SHIFT   (0x00000004u)
#define CSL_GPIO_EDGE_CTRL1_PIN3_RESETVAL (0x00000000u)

#define CSL_GPIO_EDGE_CTRL1_PIN2_MASK    (0x0000000Cu)
#define CSL_GPIO_EDGE_CTRL1_PIN2_SHIFT   (0x00000002u)
#define CSL_GPIO_EDGE_CTRL1_PIN2_RESETVAL (0x00000000u)

#define CSL_GPIO_EDGE_CTRL1_PIN1_MASK    (0x00000003u)
#define CSL_GPIO_EDGE_CTRL1_PIN1_SHIFT   (0x00000000u)
#define CSL_GPIO_EDGE_CTRL1_PIN1_RESETVAL (0x00000000u)

#define CSL_GPIO_EDGE_CTRL1_RESETVAL     (0x00000000u)

/* EDGE_CTRL2 */

#define CSL_GPIO_EDGE_CTRL2_PIN16_MASK   (0x0000C000u)
#define CSL_GPIO_EDGE_CTRL2_PIN16_SHIFT  (0x0000000Eu)
#define CSL_GPIO_EDGE_CTRL2_PIN16_RESETVAL (0x00000000u)

#define CSL_GPIO_EDGE_CTRL2_PIN15_MASK   (0x00003000u)
#define CSL_GPIO_EDGE_CTRL2_PIN15_SHIFT  (0x0000000Cu)
#define CSL_GPIO_EDGE_CTRL2_PIN15_RESETVAL (0x00000000u)

#define CSL_GPIO_EDGE_CTRL2_PIN14_MASK   (0x00000C00u)
#define CSL_GPIO_EDGE_CTRL2_PIN14_SHIFT  (0x0000000Au)
#define CSL_GPIO_EDGE_CTRL2_PIN14_RESETVAL (0x00000000u)

#define CSL_GPIO_EDGE_CTRL2_PIN13_MASK   (0x00000300u)
#define CSL_GPIO_EDGE_CTRL2_PIN13_SHIFT  (0x00000008u)
#define CSL_GPIO_EDGE_CTRL2_PIN13_RESETVAL (0x00000000u)

#define CSL_GPIO_EDGE_CTRL2_PIN12_MASK   (0x000000C0u)
#define CSL_GPIO_EDGE_CTRL2_PIN12_SHIFT  (0x00000006u)
#define CSL_GPIO_EDGE_CTRL2_PIN12_RESETVAL (0x00000000u)

#define CSL_GPIO_EDGE_CTRL2_PIN11_MASK   (0x00000030u)
#define CSL_GPIO_EDGE_CTRL2_PIN11_SHIFT  (0x00000004u)
#define CSL_GPIO_EDGE_CTRL2_PIN11_RESETVAL (0x00000000u)

#define CSL_GPIO_EDGE_CTRL2_PIN10_MASK   (0x0000000Cu)
#define CSL_GPIO_EDGE_CTRL2_PIN10_SHIFT  (0x00000002u)
#define CSL_GPIO_EDGE_CTRL2_PIN10_RESETVAL (0x00000000u)

#define CSL_GPIO_EDGE_CTRL2_PIN9_MASK    (0x00000003u)
#define CSL_GPIO_EDGE_CTRL2_PIN9_SHIFT   (0x00000000u)
#define CSL_GPIO_EDGE_CTRL2_PIN9_RESETVAL (0x00000000u)

#define CSL_GPIO_EDGE_CTRL2_RESETVAL     (0x00000000u)

/* CLEAR_IRQENABLE1 */

#define CSL_GPIO_CLEAR_IRQENABLE1_CLRIRQEN_MASK (0x0000FFFFu)
#define CSL_GPIO_CLEAR_IRQENABLE1_CLRIRQEN_SHIFT (0x00000000u)
#define CSL_GPIO_CLEAR_IRQENABLE1_CLRIRQEN_RESETVAL (0x00000000u)

#define CSL_GPIO_CLEAR_IRQENABLE1_RESETVAL (0x00000000u)

/* CLEAR_IRQENABLE2 */

#define CSL_GPIO_CLEAR_IRQENABLE2_CLRIRQEN_MASK (0x0000FFFFu)
#define CSL_GPIO_CLEAR_IRQENABLE2_CLRIRQEN_SHIFT (0x00000000u)
#define CSL_GPIO_CLEAR_IRQENABLE2_CLRIRQEN_RESETVAL (0x00000000u)

#define CSL_GPIO_CLEAR_IRQENABLE2_RESETVAL (0x00000000u)

/* CLEAR_WAKEUPENA */

#define CSL_GPIO_CLEAR_WAKEUPENA_CLRWKUPEN_MASK (0x0000FFFFu)
#define CSL_GPIO_CLEAR_WAKEUPENA_CLRWKUPEN_SHIFT (0x00000000u)
#define CSL_GPIO_CLEAR_WAKEUPENA_CLRWKUPEN_RESETVAL (0x00000000u)

#define CSL_GPIO_CLEAR_WAKEUPENA_RESETVAL (0x00000000u)

/* CLEAR_DATAOUT */

#define CSL_GPIO_CLEAR_DATAOUT_CLRVAL_MASK (0x0000FFFFu)
#define CSL_GPIO_CLEAR_DATAOUT_CLRVAL_SHIFT (0x00000000u)
#define CSL_GPIO_CLEAR_DATAOUT_CLRVAL_RESETVAL (0x00000000u)

#define CSL_GPIO_CLEAR_DATAOUT_RESETVAL  (0x00000000u)

/* SET_IRQENABLE1 */

#define CSL_GPIO_SET_IRQENABLE1_SETIRQEN_MASK (0x0000FFFFu)
#define CSL_GPIO_SET_IRQENABLE1_SETIRQEN_SHIFT (0x00000000u)
#define CSL_GPIO_SET_IRQENABLE1_SETIRQEN_RESETVAL (0x00000000u)

#define CSL_GPIO_SET_IRQENABLE1_RESETVAL (0x00000000u)

/* SET_IRQENABLE2 */

#define CSL_GPIO_SET_IRQENABLE2_IRQEN_MASK (0x0000FFFFu)
#define CSL_GPIO_SET_IRQENABLE2_IRQEN_SHIFT (0x00000000u)
#define CSL_GPIO_SET_IRQENABLE2_IRQEN_RESETVAL (0x00000000u)

#define CSL_GPIO_SET_IRQENABLE2_RESETVAL (0x00000000u)

/* SET_WAKEUPENA */

#define CSL_GPIO_SET_WAKEUPENA_WKUPENA_MASK (0x0000FFFFu)
#define CSL_GPIO_SET_WAKEUPENA_WKUPENA_SHIFT (0x00000000u)
#define CSL_GPIO_SET_WAKEUPENA_WKUPENA_RESETVAL (0x00000000u)

#define CSL_GPIO_SET_WAKEUPENA_RESETVAL  (0x00000000u)

/* SET_DATAOUT */

#define CSL_GPIO_SET_DATAOUT_TXDATA_MASK (0x0000FFFFu)
#define CSL_GPIO_SET_DATAOUT_TXDATA_SHIFT (0x00000000u)
#define CSL_GPIO_SET_DATAOUT_TXDATA_RESETVAL (0x00000000u)

#define CSL_GPIO_SET_DATAOUT_RESETVAL    (0x00000000u)

#endif