📄 cslr_emiff.h
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/*****************************************************\ * Copyright 2003, Texas Instruments Incorporated. * * All rights reserved. * * Restricted rights to use, duplicate or disclose * * this code are granted through contract. * * * * "@(#) PSP/CSL 3.0.0.0 (2003-09-30) *\*****************************************************/#ifndef _CSLR_EMIFF_001_H_#define _CSLR_EMIFF_001_H_#include <cslr.h>#include <tistdtypes.h>/**************************************************************************\* Register Overlay Structure\**************************************************************************/typedef struct { const Uint8 RSVD0[8]; Uint32 PR; const Uint8 RSVD1[20]; Uint32 CR; Uint32 MRSLEG; const Uint8 RSVD2[20]; Uint32 CR2; const Uint8 RSVD3[36]; Uint32 DWRTCR; Uint32 DWRTSR; const Uint8 RSVD4[4]; Uint32 MRS; Uint32 EMRS0; Uint32 EMRS1; const Uint8 RSVD5[4]; Uint32 OPR; Uint32 MCR; const Uint8 RSVD6[4]; Uint32 DAPTR1; Uint32 DAPTR2; Uint32 DAPTR3; Uint32 AAR; Uint32 ATR; const Uint8 RSVD7[28]; Uint32 DLRDSR; Uint32 DURDCR; Uint32 DURDSR; Uint32 EMRS2; Uint32 DLRDCR;} CSL_EmiffRegs;/**************************************************************************\* Overlay structure typedef definition\**************************************************************************/typedef volatile CSL_EmiffRegs * CSL_EmiffRegsOvly;/**************************************************************************\* Field Definition Macros\**************************************************************************/ /* CSL_EMIFF_PR */#define CSL_EMIFF_PR_OCPI_MASK (0x0000F000u)#define CSL_EMIFF_PR_OCPI_SHIFT (0x0000000Cu)#define CSL_EMIFF_PR_OCPI_RESETVAL (0x00000000u)#define CSL_EMIFF_PR_DMA_MASK (0x00000F00u)#define CSL_EMIFF_PR_DMA_SHIFT (0x00000008u)#define CSL_EMIFF_PR_DMA_RESETVAL (0x00000000u)#define CSL_EMIFF_PR_DSP_MASK (0x00000070u)#define CSL_EMIFF_PR_DSP_SHIFT (0x00000004u)#define CSL_EMIFF_PR_DSP_RESETVAL (0x00000000u)#define CSL_EMIFF_PR_ARM_MASK (0x00000007u)#define CSL_EMIFF_PR_ARM_SHIFT (0x00000000u)#define CSL_EMIFF_PR_ARM_RESETVAL (0x00000000u)#define CSL_EMIFF_PR_RESETVAL (0x00000000u) /* CSL_EMIFF_CR */#define CSL_EMIFF_CR_LGSDRTP_MASK (0x30000000u)#define CSL_EMIFF_CR_LGSDRTP_SHIFT (0x0000001Cu)#define CSL_EMIFF_CR_LGSDRTP_RESETVAL (0x00000000u)#define CSL_EMIFF_CR_CLK_MASK (0x08000000u)#define CSL_EMIFF_CR_CLK_SHIFT (0x0000001Bu)#define CSL_EMIFF_CR_CLK_RESETVAL (0x00000000u)#define CSL_EMIFF_CR_PWD_MASK (0x04000000u)#define CSL_EMIFF_CR_PWD_SHIFT (0x0000001Au)#define CSL_EMIFF_CR_PWD_RESETVAL (0x00000000u)#define CSL_EMIFF_CR_SDRFRQ_MASK (0x03000000u)#define CSL_EMIFF_CR_SDRFRQ_SHIFT (0x00000018u)#define CSL_EMIFF_CR_SDRFRQ_RESETVAL (0x00000000u)#define CSL_EMIFF_CR_ARCV_MASK (0x00FFFF00u)#define CSL_EMIFF_CR_ARCV_SHIFT (0x00000008u)#define CSL_EMIFF_CR_ARCV_RESETVAL (0x00006188u)#define CSL_EMIFF_CR_SDRTP_MASK (0x000000F0u)#define CSL_EMIFF_CR_SDRTP_SHIFT (0x00000004u)#define CSL_EMIFF_CR_SDRTP_RESETVAL (0x00000000u)#define CSL_EMIFF_CR_ARE_MASK (0x0000000Cu)#define CSL_EMIFF_CR_ARE_SHIFT (0x00000002u)#define CSL_EMIFF_CR_ARE_RESETVAL (0x00000000u)#define CSL_EMIFF_CR_SLRF_MASK (0x00000001u)#define CSL_EMIFF_CR_SLRF_SHIFT (0x00000000u)#define CSL_EMIFF_CR_SLRF_RESETVAL (0x00000000u)#define CSL_EMIFF_CR_RESETVAL (0x00618800u) /* CSL_EMIFF_MRSLEG */#define CSL_EMIFF_MRSLEG_WBST_MASK (0x00000200u)#define CSL_EMIFF_MRSLEG_WBST_SHIFT (0x00000009u)#define CSL_EMIFF_MRSLEG_WBST_RESETVAL \ (0x00000000u)#define CSL_EMIFF_MRSLEG_CASL_MASK (0x00000070u)#define CSL_EMIFF_MRSLEG_CASL_SHIFT (0x00000004u)#define CSL_EMIFF_MRSLEG_CASL_RESETVAL \ (0x00000003u)#define CSL_EMIFF_MRSLEG_SI_MASK (0x00000008u)#define CSL_EMIFF_MRSLEG_SI_SHIFT (0x00000003u)#define CSL_EMIFF_MRSLEG_SI_RESETVAL (0x00000000u)#define CSL_EMIFF_MRSLEG_PGBL_MASK (0x00000007u)#define CSL_EMIFF_MRSLEG_PGBL_SHIFT (0x00000000u)#define CSL_EMIFF_MRSLEG_PGBL_RESETVAL \ (0x00000007u)#define CSL_EMIFF_MRSLEG_RESETVAL (0x00000037u) /* CSL_EMIFF_CR2 */#define CSL_EMIFF_CR2_AUTOCLK_MASK (0x00000004u)#define CSL_EMIFF_CR2_AUTOCLK_SHIFT (0x00000002u)#define CSL_EMIFF_CR2_AUTOCLK_RESETVAL \ (0x00000000u)#define CSL_EMIFF_CR2_RFRST_MASK (0x00000002u)#define CSL_EMIFF_CR2_RFRST_SHIFT (0x00000001u)#define CSL_EMIFF_CR2_RFRST_RESETVAL (0x00000001u)#define CSL_EMIFF_CR2_RFSTDBY_MASK (0x00000001u)#define CSL_EMIFF_CR2_RFSTDBY_SHIFT (0x00000000u)#define CSL_EMIFF_CR2_RFSTDBY_RESETVAL \ (0x00000001u)#define CSL_EMIFF_CR2_RESETVAL (0x00000003u) /* CSL_EMIFF_DWRTCR */#define CSL_EMIFF_DWRTCR_WROFF_MASK (0x03F00000u)#define CSL_EMIFF_DWRTCR_WROFF_SHIFT (0x00000014u)#define CSL_EMIFF_DWRTCR_WROFF_RESETVAL \ (0x00000000u)#define CSL_EMIFF_DWRTCR_DLY_MASK (0x0000FF00u)#define CSL_EMIFF_DWRTCR_DLY_SHIFT (0x00000008u)#define CSL_EMIFF_DWRTCR_DLY_RESETVAL (0x00000000u)#define CSL_EMIFF_DWRTCR_LDDLL_MASK (0x00000008u)#define CSL_EMIFF_DWRTCR_LDDLL_SHIFT (0x00000003u)#define CSL_EMIFF_DWRTCR_LDDLL_RESETVAL \ (0x00000000u)#define CSL_EMIFF_DWRTCR_DLLPH_MASK (0x00000004u)#define CSL_EMIFF_DWRTCR_DLLPH_SHIFT (0x00000002u)#define CSL_EMIFF_DWRTCR_DLLPH_RESETVAL \ (0x00000000u)#define CSL_EMIFF_DWRTCR_ENADLL_MASK (0x00000002u)#define CSL_EMIFF_DWRTCR_ENADLL_SHIFT (0x00000001u)#define CSL_EMIFF_DWRTCR_ENADLL_RESETVAL \ (0x00000000u)#define CSL_EMIFF_DWRTCR_RESETVAL (0x00000000u) /* CSL_EMIFF_DWRTSR */#define CSL_EMIFF_DWRTSR_DLLCNT_MASK (0x0000FF00u)#define CSL_EMIFF_DWRTSR_DLLCNT_SHIFT (0x00000008u)#define CSL_EMIFF_DWRTSR_DLLCNT_RESETVAL \ (0x00000000u)#define CSL_EMIFF_DWRTSR_LOCK_MASK (0x00000004u)#define CSL_EMIFF_DWRTSR_LOCK_SHIFT (0x00000002u)#define CSL_EMIFF_DWRTSR_LOCK_RESETVAL \ (0x00000000u)#define CSL_EMIFF_DWRTSR_UDF_MASK (0x00000002u)#define CSL_EMIFF_DWRTSR_UDF_SHIFT (0x00000001u)#define CSL_EMIFF_DWRTSR_UDF_RESETVAL (0x00000000u)#define CSL_EMIFF_DWRTSR_OVF_MASK (0x00000001u)#define CSL_EMIFF_DWRTSR_OVF_SHIFT (0x00000000u)#define CSL_EMIFF_DWRTSR_OVF_RESETVAL (0x00000000u)#define CSL_EMIFF_DWRTSR_RESETVAL (0x00000000u) /* CSL_EMIFF_MRS */#define CSL_EMIFF_MRS_WBST_MASK (0x00000200u)#define CSL_EMIFF_MRS_WBST_SHIFT (0x00000009u)#define CSL_EMIFF_MRS_WBST_RESETVAL (0x00000000u)#define CSL_EMIFF_MRS_CASL_MASK (0x00000070u)#define CSL_EMIFF_MRS_CASL_SHIFT (0x00000004u)#define CSL_EMIFF_MRS_CASL_RESETVAL (0x00000003u)#define CSL_EMIFF_MRS_SI_MASK (0x00000008u)#define CSL_EMIFF_MRS_SI_SHIFT (0x00000003u)#define CSL_EMIFF_MRS_SI_RESETVAL (0x00000000u)#define CSL_EMIFF_MRS_PGBL_MASK (0x00000007u)#define CSL_EMIFF_MRS_PGBL_SHIFT (0x00000000u)#define CSL_EMIFF_MRS_PGBL_RESETVAL (0x00000007u)#define CSL_EMIFF_MRS_RESETVAL (0x00000037u)⌨️ 快捷键说明
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