cslr_pwl.h

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/** ============================================================================
 *   @file  cslr_pwl.h
 *
 *   @path  $(CSLPATH)\arm\pwl\src
 *
 *   @desc  Register layer header file for PWL CSL
 *
 */
 
/*  ============================================================================
 *   Copyright (c) Texas Instruments Inc 2002, 2003, 2004
 *
 *   Use of this software is controlled by the terms and conditions found in the
 *   license agreement under which this software has been supplied.
 *   ===========================================================================
 */
 
/*  @(#) PSP/CSL 3.00.01.00[5912] (2004-06-01)  */

/* =============================================================================
 *  Revision History
 *  ===============
 *  01-Jun-2004 Shiva File Created.
 *
 * =============================================================================
 */
 
#ifndef _CSLR_PWL_H_
#define _CSLR_PWL_H_

#ifdef __cplusplus
extern "C" {
#endif

#include <cslr.h>

/**
  * Register overlay structure
  */
typedef struct  {
    /** PWL level register */
    volatile Uint8 PWL_LEVEL;
    /** Reserved fields */
    const char RSVD0[3];
    /** PWL control register */
    volatile Uint8 PWL_CTRL;
} CSL_PwlRegs;

/**
  * Register Id's
  */
typedef enum  {
   /** PWL level register offset */
   CSL_PWL_PWL_LEVEL = 0x0000u,
   /** PWL control register offset */
   CSL_PWL_PWL_CTRL = 0x0004u
} CSL_PwlRegIds;

/**
  * Overlay structure typedef definition
  */
typedef volatile CSL_PwlRegs  * CSL_PwlRegsOvly;

/**
  * Field Definition Macros
  */

/** PWL_LEVEL */
/** PWL level mask */
#define CSL_PWL_PWL_LEVEL_PWL_LEVEL_MASK (0x000000FFu)
/** PWL level shift */
#define CSL_PWL_PWL_LEVEL_PWL_LEVEL_SHIFT (0x00000000u)
/** PWL level reset value */
#define CSL_PWL_PWL_LEVEL_PWL_LEVEL_RESETVAL (0x00000000u)
/** PWL level register reset value */
#define CSL_PWL_PWL_LEVEL_RESETVAL       (0x00000000u)

/** PWL_CTRL */
/** PWL clock enable mask */
#define CSL_PWL_PWL_CTRL_CLK_ENABLE_MASK (0x00000001u)
/** PWL clock enable shift */
#define CSL_PWL_PWL_CTRL_CLK_ENABLE_SHIFT (0x00000000u)
/** PWL clock enable reset value */
#define CSL_PWL_PWL_CTRL_CLK_ENABLE_RESETVAL (0x00000000u)
/** PWL disable clock enable */
#define CSL_PWL_PWL_CTRL_CLK_ENABLE_DIS  (0x00000000u)
/** PWL enable clock enable */
#define CSL_PWL_PWL_CTRL_CLK_ENABLE_EN   (0x00000001u)
/** PWL control register reset value */
#define CSL_PWL_PWL_CTRL_RESETVAL        (0x00000000u)

#ifdef __cplusplus
}
#endif

#endif  /* CSLR_PWL_H_ */