cslr_vlynq.h

dsp在音频处理中的运用

/** ============================================================================
 *   @file  cslr_vlynq.h
 *
 *   @path  $(CSLPATH)\arm\vlynq\src
 *
 *   @desc  API header file for VLYNQ CSL
 *
 */
 
/*  ============================================================================
 *   Copyright (c) Texas Instruments Inc 2002, 2003, 2004
 *
 *   Use of this software is controlled by the terms and conditions found in the
 *   license agreement under which this software has been supplied.
 *   ===========================================================================
 */
 
/*  @(#) PSP/CSL 3.00.01.00[5912] (2004-07-05)  */

/* =============================================================================
 *  Revision History
 *  ===============
 *  29-Jul-2004 sd File taken from TI code base.
 * =============================================================================
 */
/* ---- File: <cslr_vlynq.h> ---- */ 
/* -*- C++ -*-  */
/* FILE: "/dsp/trinity_sim/sw/arm9_inc/cslr_vlynq.h"  */
/* LAST MODIFICATION: "Thu, 04 Mar 2004 21:07:50  (a0875069)" */
/* (C) 2004 by Ramakrishnan S <[e-mail]>  */
 
#ifndef _CSLR_VLYNQ_H_ 
#define _CSLR_VLYNQ_H_ 
 
#include <cslr.h> 
#include <tistdtypes.h> 

/** Register Overlay Structure */ 
typedef struct  { 
    volatile Uint32 REVID; 
    volatile Uint32 CTRL; 
    volatile Uint32 STAT; 
    Uint32          RSVD0; 
    volatile Uint32 INTSTATCLR; 
    volatile Uint32 INTPENDSET; 
    volatile Uint32 INTPTR; 
    volatile Uint32 XAM; 
    volatile Uint32 RAMS1; 
    volatile Uint32 RAMO1; 
    volatile Uint32 RAMS2; 
    volatile Uint32 RAMO2; 
    volatile Uint32 RAMS3; 
    volatile Uint32 RAMO3; 
    volatile Uint32 RAMS4; 
    volatile Uint32 RAMO4; 
    volatile Uint32 CHIPVER; 
    const char RSVD1[60]; 
    volatile Uint32 RREVID; 
    volatile Uint32 RCTRL; 
    volatile Uint32 RSTAT; 
    Uint32          RSVD2; 
    volatile Uint32 RINTSTATCLR; 
    volatile Uint32 RINTPENDSET; 
    volatile Uint32 RINTPTR; 
    volatile Uint32 RXAM; 
    volatile Uint32 RRAMS1; 
    volatile Uint32 RRAMO1; 
    volatile Uint32 RRAMS2; 
    volatile Uint32 RRAMO2; 
    volatile Uint32 RRAMS3; 
    volatile Uint32 RRAMO3; 
    volatile Uint32 RRAMS4; 
    volatile Uint32 RRAMO4; 
    volatile Uint32 RCHIPVER; 
    const char RSVD3[60]; 
    volatile Uint32 CONFIG; 
    volatile Uint32 ADDR_FAULT; 
    volatile Uint32 BUSY; 
    volatile Uint32 DMAREQ_EN; 
} CSL_VlynqRegs; 

/** Overlay structure typedef definition */ 
typedef volatile CSL_VlynqRegs *   CSL_VlynqRegsOvly; 
 
/** Register Id's */ 
typedef enum  { 
   CSL_VLYNQ_REVID = 0x0000u, 
   CSL_VLYNQ_CTRL = 0x0004u, 
   CSL_VLYNQ_STAT = 0x0008u, 
   CSL_VLYNQ_INTSTATCLR = 0x0010u, 
   CSL_VLYNQ_INTPENDSET = 0x0014u, 
   CSL_VLYNQ_INTPTR = 0x0018u, 
   CSL_VLYNQ_XAM = 0x001cu, 
   CSL_VLYNQ_RAMS1 = 0x0020u, 
   CSL_VLYNQ_RAMO1 = 0x0024u, 
   CSL_VLYNQ_RAMS2 = 0x0028u, 
   CSL_VLYNQ_RAMO2 = 0x002cu, 
   CSL_VLYNQ_RAMS3 = 0x0030u, 
   CSL_VLYNQ_RAMO3 = 0x0034u, 
   CSL_VLYNQ_RAMS4 = 0x0038u, 
   CSL_VLYNQ_RAMO4 = 0x003cu, 
   CSL_VLYNQ_CHIPVER = 0x0040u, 
   CSL_VLYNQ_RREVID = 0x0080u, 
   CSL_VLYNQ_RCTRL = 0x0084u, 
   CSL_VLYNQ_RSTAT = 0x0088u, 
   CSL_VLYNQ_RINTSTATCLR = 0x0090u, 
   CSL_VLYNQ_RINTPENDSET = 0x0094u, 
   CSL_VLYNQ_RINTPTR = 0x0098u, 
   CSL_VLYNQ_RXAM = 0x009cu, 
   CSL_VLYNQ_RRAMS1 = 0x00a0u, 
   CSL_VLYNQ_RRAMO1 = 0x00a4u, 
   CSL_VLYNQ_RRAMS2 = 0x00a8u, 
   CSL_VLYNQ_RRAMO2 = 0x00acu, 
   CSL_VLYNQ_RRAMS3 = 0x00b0u, 
   CSL_VLYNQ_RRAMO3 = 0x00b4u, 
   CSL_VLYNQ_RRAMS4 = 0x00b8u, 
   CSL_VLYNQ_RRAMO4 = 0x00bcu, 
   CSL_VLYNQ_RCHIPVER = 0x00c0u, 
   CSL_VLYNQ_CONFIG = 0x0100u, 
   CSL_VLYNQ_ADDR_FAULT = 0x0104u, 
   CSL_VLYNQ_BUSY = 0x0108u, 
   CSL_VLYNQ_DMAREQ_EN = 0x010cu 
} CSL_VlynqRegIds; 
 
/** Field Definition Macros */ 
 
/* REVID */ 
 
#define CSL_VLYNQ_REVID_ID_MASK          (0xFFFF0000u) 
#define CSL_VLYNQ_REVID_ID_SHIFT         (0x00000010u) 
#define CSL_VLYNQ_REVID_ID_RESETVAL      (0x00000001u) 
 
#define CSL_VLYNQ_REVID_REVMAJ_MASK      (0x0000FF00u) 
#define CSL_VLYNQ_REVID_REVMAJ_SHIFT     (0x00000008u) 
#define CSL_VLYNQ_REVID_REVMAJ_RESETVAL  (0x00000002u) 
 
#define CSL_VLYNQ_REVID_REVMIN_MASK      (0x000000FFu) 
#define CSL_VLYNQ_REVID_REVMIN_SHIFT     (0x00000000u) 
#define CSL_VLYNQ_REVID_REVMIN_RESETVAL  (0x00000005u) 
 
#define CSL_VLYNQ_REVID_RESETVAL         (0x00010205u) 
 
/* CTRL */ 
 
#define CSL_VLYNQ_CTRL_CLKDIV_MASK       (0x00070000u) 
#define CSL_VLYNQ_CTRL_CLKDIV_SHIFT      (0x00000010u) 
#define CSL_VLYNQ_CTRL_CLKDIV_RESETVAL   (0x00000000u) 
#define CSL_VLYNQ_CTRL_CLKDIV_ONE        (0x00000000u) 
#define CSL_VLYNQ_CTRL_CLKDIV_TWO        (0x00000001u) 
#define CSL_VLYNQ_CTRL_CLKDIV_THREE      (0x00000002u) 
#define CSL_VLYNQ_CTRL_CLKDIV_FOUR       (0x00000003u) 
#define CSL_VLYNQ_CTRL_CLKDIV_FIVE       (0x00000004u) 
#define CSL_VLYNQ_CTRL_CLKDIV_SIX        (0x00000005u) 
#define CSL_VLYNQ_CTRL_CLKDIV_SEVEN      (0x00000006u) 
#define CSL_VLYNQ_CTRL_CLKDIV_EIGHT      (0x00000007u) 
 
#define CSL_VLYNQ_CTRL_CLKDIR_MASK       (0x00008000u) 
#define CSL_VLYNQ_CTRL_CLKDIR_SHIFT      (0x0000000Fu) 
#define CSL_VLYNQ_CTRL_CLKDIR_RESETVAL   (0x00000000u) 
#define CSL_VLYNQ_CTRL_CLKDIR_INPUT      (0x00000000u) 
#define CSL_VLYNQ_CTRL_CLKDIR_OUTPUT     (0x00000001u) 
 
#define CSL_VLYNQ_CTRL_INTLOCAL_MASK     (0x00004000u) 
#define CSL_VLYNQ_CTRL_INTLOCAL_SHIFT    (0x0000000Eu) 
#define CSL_VLYNQ_CTRL_INTLOCAL_RESETVAL (0x00000000u) 
#define CSL_VLYNQ_CTRL_INTLOCAL_REMOTE   (0x00000000u) 
#define CSL_VLYNQ_CTRL_INTLOCAL_LOCAL    (0x00000001u) 
 
#define CSL_VLYNQ_CTRL_INTENABLE_MASK    (0x00002000u) 
#define CSL_VLYNQ_CTRL_INTENABLE_SHIFT   (0x0000000Du) 
#define CSL_VLYNQ_CTRL_INTENABLE_RESETVAL (0x00000000u) 
#define CSL_VLYNQ_CTRL_INTENABLE_DISABLE (0x00000000u) 
#define CSL_VLYNQ_CTRL_INTENABLE_ENABLE  (0x00000001u) 
 
#define CSL_VLYNQ_CTRL_INTVEC_MASK       (0x00001F00u) 
#define CSL_VLYNQ_CTRL_INTVEC_SHIFT      (0x00000008u) 
#define CSL_VLYNQ_CTRL_INTVEC_RESETVAL   (0x00000000u) 
 
#define CSL_VLYNQ_CTRL_INT2CFG_MASK      (0x00000080u) 
#define CSL_VLYNQ_CTRL_INT2CFG_SHIFT     (0x00000007u) 
#define CSL_VLYNQ_CTRL_INT2CFG_RESETVAL  (0x00000000u) 
#define CSL_VLYNQ_CTRL_INT2CFG_DISABLE   (0x00000000u) 
#define CSL_VLYNQ_CTRL_INT2CFG_ENABLE    (0x00000001u) 
 
#define CSL_VLYNQ_CTRL_ILOOP_MASK        (0x00000002u) 
#define CSL_VLYNQ_CTRL_ILOOP_SHIFT       (0x00000001u) 
#define CSL_VLYNQ_CTRL_ILOOP_RESETVAL    (0x00000000u) 
#define CSL_VLYNQ_CTRL_ILOOP_DISABLE     (0x00000000u) 
#define CSL_VLYNQ_CTRL_ILOOP_ENABLE      (0x00000001u) 
 
#define CSL_VLYNQ_CTRL_RESETVAL          (0x03000000u) 
 
/* STAT */ 
 
#define CSL_VLYNQ_STAT_SWIDTH_MASK    (0x07000000u) 
#define CSL_VLYNQ_STAT_SWIDTH_SHIFT   (0x00000018u) 
#define CSL_VLYNQ_STAT_SWIDTH_RESETVAL (0x00000000u) 

#define CSL_VLYNQ_STAT_MODESUP_MASK    (0x00E0000u) 
#define CSL_VLYNQ_STAT_MODESUP_SHIFT   (0x00000015u) 
#define CSL_VLYNQ_STAT_MODESUP_RESETVAL (0x00000000u) 
 
#define CSL_VLYNQ_STAT_IFLOW_MASK        (0x00000400u) 
#define CSL_VLYNQ_STAT_IFLOW_SHIFT       (0x0000000Au) 
#define CSL_VLYNQ_STAT_IFLOW_RESETVAL    (0x00000000u) 
 
#define CSL_VLYNQ_STAT_OFLOW_MASK        (0x00000200u) 
#define CSL_VLYNQ_STAT_OFLOW_SHIFT       (0x00000009u) 
#define CSL_VLYNQ_STAT_OFLOW_RESETVAL    (0x00000000u) 
 
#define CSL_VLYNQ_STAT_RERROR_MASK       (0x00000100u) 
#define CSL_VLYNQ_STAT_RERROR_SHIFT      (0x00000008u) 
#define CSL_VLYNQ_STAT_RERROR_RESETVAL   (0x00000000u) 
 
#define CSL_VLYNQ_STAT_LERROR_MASK       (0x00000080u) 
#define CSL_VLYNQ_STAT_LERROR_SHIFT      (0x00000007u) 
#define CSL_VLYNQ_STAT_LERROR_RESETVAL   (0x00000000u) 
 
#define CSL_VLYNQ_STAT_NFEMPTY3_MASK     (0x00000040u) 
#define CSL_VLYNQ_STAT_NFEMPTY3_SHIFT    (0x00000006u) 
#define CSL_VLYNQ_STAT_NFEMPTY3_RESETVAL (0x00000000u) 
 
#define CSL_VLYNQ_STAT_NFEMPTY2_MASK     (0x00000020u) 
#define CSL_VLYNQ_STAT_NFEMPTY2_SHIFT    (0x00000005u) 
#define CSL_VLYNQ_STAT_NFEMPTY2_RESETVAL (0x00000000u) 
 
#define CSL_VLYNQ_STAT_NFEMPTY1_MASK     (0x00000010u) 
#define CSL_VLYNQ_STAT_NFEMPTY1_SHIFT    (0x00000004u) 
#define CSL_VLYNQ_STAT_NFEMPTY1_RESETVAL (0x00000000u) 
 
#define CSL_VLYNQ_STAT_NFEMPTY0_MASK     (0x00000008u) 
#define CSL_VLYNQ_STAT_NFEMPTY0_SHIFT    (0x00000003u) 
#define CSL_VLYNQ_STAT_NFEMPTY0_RESETVAL (0x00000000u) 
 
#define CSL_VLYNQ_STAT_SPEND_MASK        (0x00000004u) 
#define CSL_VLYNQ_STAT_SPEND_SHIFT       (0x00000002u) 
#define CSL_VLYNQ_STAT_SPEND_RESETVAL    (0x00000000u) 
 
#define CSL_VLYNQ_STAT_MPEND_MASK        (0x00000002u) 
#define CSL_VLYNQ_STAT_MPEND_SHIFT       (0x00000001u) 
#define CSL_VLYNQ_STAT_MPEND_RESETVAL    (0x00000000u) 
 
#define CSL_VLYNQ_STAT_LINK_MASK         (0x00000001u) 
#define CSL_VLYNQ_STAT_LINK_SHIFT        (0x00000000u) 
#define CSL_VLYNQ_STAT_LINK_RESETVAL     (0x00000000u) 
 
#define CSL_VLYNQ_STAT_RESETVAL          (0x00000000u) 
 
/* INTSTATCLR */ 
 
#define CSL_VLYNQ_INTSTATCLR_INTCLR_MASK (0xFFFFFFFFu) 
#define CSL_VLYNQ_INTSTATCLR_INTCLR_SHIFT (0x00000000u) 
#define CSL_VLYNQ_INTSTATCLR_INTCLR_RESETVAL (0x00000000u) 
 
#define CSL_VLYNQ_INTSTATCLR_RESETVAL    (0x00000000u) 
 
/* INTPENDSET */ 
 
#define CSL_VLYNQ_INTPENDSET_INTSET_MASK (0xFFFFFFFFu) 
#define CSL_VLYNQ_INTPENDSET_INTSET_SHIFT (0x00000000u) 
#define CSL_VLYNQ_INTPENDSET_INTSET_RESETVAL (0x00000000u) 
 
#define CSL_VLYNQ_INTPENDSET_RESETVAL    (0x00000000u) 
 
/* INTPTR */ 
 
#define CSL_VLYNQ_INTPTR_INTPTR_MASK     (0xFFFFFFFCu) 
#define CSL_VLYNQ_INTPTR_INTPTR_SHIFT    (0x00000002u) 
#define CSL_VLYNQ_INTPTR_INTPTR_RESETVAL (0x00000000u) 
 
#define CSL_VLYNQ_INTPTR_RESETVAL        (0x00000000u) 
 
/* XAM */ 
 
#define CSL_VLYNQ_XAM_TXADRMAP_MASK      (0xFFFFFFFCu) 
#define CSL_VLYNQ_XAM_TXADRMAP_SHIFT     (0x00000002u) 
#define CSL_VLYNQ_XAM_TXADRMAP_RESETVAL  (0x00000000u) 
 
#define CSL_VLYNQ_XAM_RESETVAL           (0x00000000u) 
 
/* RAMS1 */ 
 
#define CSL_VLYNQ_RAMS1_RXADRSIZE1_MASK  (0xFFFFFFFCu) 
#define CSL_VLYNQ_RAMS1_RXADRSIZE1_SHIFT (0x00000002u) 
#define CSL_VLYNQ_RAMS1_RXADRSIZE1_RESETVAL (0x00000000u) 
 
#define CSL_VLYNQ_RAMS1_RESETVAL         (0x00000000u) 
 
/* RAMO1 */ 
 
#define CSL_VLYNQ_RAMO1_RXADROFFSET1_MASK (0xFFFFFFFCu) 
#define CSL_VLYNQ_RAMO1_RXADROFFSET1_SHIFT (0x00000002u) 
#define CSL_VLYNQ_RAMO1_RXADROFFSET1_RESETVAL (0x00000000u) 
 
#define CSL_VLYNQ_RAMO1_RESETVAL         (0x00000000u) 
 
/* RAMS2 */ 
 
#define CSL_VLYNQ_RAMS2_RXADRSIZE2_MASK  (0xFFFFFFFCu) 
#define CSL_VLYNQ_RAMS2_RXADRSIZE2_SHIFT (0x00000002u) 
#define CSL_VLYNQ_RAMS2_RXADRSIZE2_RESETVAL (0x00000000u) 
 
#define CSL_VLYNQ_RAMS2_RESETVAL         (0x00000000u) 
 
/* RAMO2 */ 
 
#define CSL_VLYNQ_RAMO2_RXADROFFSET2_MASK (0xFFFFFFFCu) 
#define CSL_VLYNQ_RAMO2_RXADROFFSET2_SHIFT (0x00000002u) 
#define CSL_VLYNQ_RAMO2_RXADROFFSET2_RESETVAL (0x00000000u) 
 
#define CSL_VLYNQ_RAMO2_RESETVAL         (0x00000000u) 
 
/* RAMS3 */ 
 
#define CSL_VLYNQ_RAMS3_RXADRSIZE3_MASK  (0xFFFFFFFCu) 
#define CSL_VLYNQ_RAMS3_RXADRSIZE3_SHIFT (0x00000002u) 
#define CSL_VLYNQ_RAMS3_RXADRSIZE3_RESETVAL (0x00000000u) 
 
#define CSL_VLYNQ_RAMS3_RESETVAL         (0x00000000u)