📄 cslr_irda.h

📁 dsp在音频处理中的运用
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#define CSL_IRDA_LCR_PARITY_TYPE1_MASK   (0x00000010u)#define CSL_IRDA_LCR_PARITY_TYPE1_SHIFT  (0x00000004u)#define CSL_IRDA_LCR_PARITY_TYPE1_RESETVAL (0x00000000u)#define CSL_IRDA_LCR_PARITY_EN_MASK      (0x00000008u)#define CSL_IRDA_LCR_PARITY_EN_SHIFT     (0x00000003u)#define CSL_IRDA_LCR_PARITY_EN_RESETVAL  (0x00000000u)#define CSL_IRDA_LCR_NB_STOP_MASK        (0x00000004u)#define CSL_IRDA_LCR_NB_STOP_SHIFT       (0x00000002u)#define CSL_IRDA_LCR_NB_STOP_RESETVAL    (0x00000000u)#define CSL_IRDA_LCR_NB_STOP_01          (0x00000000u)#define CSL_IRDA_LCR_NB_STOP_1_5         (0x00000001u)#define CSL_IRDA_LCR_NB_STOP_02          (0x00000001u)#define CSL_IRDA_LCR_CHAR_LENGTH_MASK    (0x00000003u)#define CSL_IRDA_LCR_CHAR_LENGTH_SHIFT   (0x00000000u)#define CSL_IRDA_LCR_CHAR_LENGTH_RESETVAL (0x00000000u)#define CSL_IRDA_LCR_CHAR_LENGTH_05      (0x00000000u)#define CSL_IRDA_LCR_CHAR_LENGTH_06      (0x00000001u)#define CSL_IRDA_LCR_CHAR_LENGTH_07      (0x00000002u)#define CSL_IRDA_LCR_CHAR_LENGTH_08      (0x00000003u)#define CSL_IRDA_LCR_RESETVAL            (0x00000000u)/* MCR_ADDR1 */#define CSL_IRDA_MCR_ADDR1_MCR_ADDR1_MASK (0x000000FFu)#define CSL_IRDA_MCR_ADDR1_MCR_ADDR1_SHIFT (0x00000000u)#define CSL_IRDA_MCR_ADDR1_MCR_ADDR1_RESETVAL (0x00000000u)#define CSL_IRDA_MCR_ADDR1_RESETVAL      (0x00000000u)/* MCR */#define CSL_IRDA_MCR_TCR_TLR_MASK        (0x00000040u)#define CSL_IRDA_MCR_TCR_TLR_SHIFT       (0x00000006u)#define CSL_IRDA_MCR_TCR_TLR_RESETVAL    (0x00000000u)#define CSL_IRDA_MCR_TCR_TLR_DISABLE     (0x00000000u)#define CSL_IRDA_MCR_TCR_TLR_ENABLE      (0x00000001u)#define CSL_IRDA_MCR_XON_EN_MASK         (0x00000020u)#define CSL_IRDA_MCR_XON_EN_SHIFT        (0x00000005u)#define CSL_IRDA_MCR_XON_EN_RESETVAL     (0x00000000u)#define CSL_IRDA_MCR_XON_EN_DISABLE      (0x00000000u)#define CSL_IRDA_MCR_XON_EN_ENABLE       (0x00000001u)#define CSL_IRDA_MCR_LOOPBACK_EN_MASK    (0x00000010u)#define CSL_IRDA_MCR_LOOPBACK_EN_SHIFT   (0x00000004u)#define CSL_IRDA_MCR_LOOPBACK_EN_RESETVAL (0x00000000u)#define CSL_IRDA_MCR_LOOPBACK_EN_DISABLE (0x00000000u)#define CSL_IRDA_MCR_LOOPBACK_EN_ENABLE  (0x00000001u)#define CSL_IRDA_MCR_CD_STS_CH_MASK      (0x00000008u)#define CSL_IRDA_MCR_CD_STS_CH_SHIFT     (0x00000003u)#define CSL_IRDA_MCR_CD_STS_CH_RESETVAL  (0x00000000u)#define CSL_IRDA_MCR_CD_STS_CH_HIGH      (0x00000000u)#define CSL_IRDA_MCR_CD_STS_CH_LOW       (0x00000001u)#define CSL_IRDA_MCR_RI_STS_CH_MASK      (0x00000004u)#define CSL_IRDA_MCR_RI_STS_CH_SHIFT     (0x00000002u)#define CSL_IRDA_MCR_RI_STS_CH_RESETVAL  (0x00000000u)#define CSL_IRDA_MCR_RI_STS_CH_HIGH      (0x00000000u)#define CSL_IRDA_MCR_RI_STS_CH_LOW       (0x00000001u)#define CSL_IRDA_MCR_RTS_MASK            (0x00000002u)#define CSL_IRDA_MCR_RTS_SHIFT           (0x00000001u)#define CSL_IRDA_MCR_RTS_RESETVAL        (0x00000000u)#define CSL_IRDA_MCR_RTS_DISABLE         (0x00000000u)#define CSL_IRDA_MCR_RTS_ENABLE          (0x00000001u)#define CSL_IRDA_MCR_DTR_MASK            (0x00000001u)#define CSL_IRDA_MCR_DTR_SHIFT           (0x00000000u)#define CSL_IRDA_MCR_DTR_RESETVAL        (0x00000000u)#define CSL_IRDA_MCR_DTR_DISABLE         (0x00000000u)#define CSL_IRDA_MCR_DTR_ENABLE          (0x00000001u)#define CSL_IRDA_MCR_RESETVAL            (0x00000000u)/* ADDR1 */#define CSL_IRDA_ADDR1_ADDR_MASK         (0x000000FFu)#define CSL_IRDA_ADDR1_ADDR_SHIFT        (0x00000000u)#define CSL_IRDA_ADDR1_ADDR_RESETVAL     (0x00000000u)#define CSL_IRDA_ADDR1_RESETVAL          (0x00000000u)/* LSR_ADDR2 */#define CSL_IRDA_LSR_ADDR2_LSR_ADDR2_MASK (0x000000FFu)#define CSL_IRDA_LSR_ADDR2_LSR_ADDR2_SHIFT (0x00000000u)#define CSL_IRDA_LSR_ADDR2_LSR_ADDR2_RESETVAL (0x00000000u)#define CSL_IRDA_LSR_ADDR2_RESETVAL      (0x00000000u)/* LSR */#define CSL_IRDA_LSR_THR_EMPTY_MASK      (0x00000080u)#define CSL_IRDA_LSR_THR_EMPTY_SHIFT     (0x00000007u)#define CSL_IRDA_LSR_THR_EMPTY_RESETVAL  (0x00000001u)#define CSL_IRDA_LSR_STS_FIFO_FULL_MASK  (0x00000040u)#define CSL_IRDA_LSR_STS_FIFO_FULL_SHIFT (0x00000006u)#define CSL_IRDA_LSR_STS_FIFO_FULL_RESETVAL (0x00000000u)#define CSL_IRDA_LSR_RX_LAST_BYTE_MASK   (0x00000020u)#define CSL_IRDA_LSR_RX_LAST_BYTE_SHIFT  (0x00000005u)#define CSL_IRDA_LSR_RX_LAST_BYTE_RESETVAL (0x00000000u)#define CSL_IRDA_LSR_FRAME_TOO_LONG_MASK (0x00000010u)#define CSL_IRDA_LSR_FRAME_TOO_LONG_SHIFT (0x00000004u)#define CSL_IRDA_LSR_FRAME_TOO_LONG_RESETVAL (0x00000000u)#define CSL_IRDA_LSR_ABORT_MASK          (0x00000008u)#define CSL_IRDA_LSR_ABORT_SHIFT         (0x00000003u)#define CSL_IRDA_LSR_ABORT_RESETVAL      (0x00000000u)#define CSL_IRDA_LSR_CRC_MASK            (0x00000004u)#define CSL_IRDA_LSR_CRC_SHIFT           (0x00000002u)#define CSL_IRDA_LSR_CRC_RESETVAL        (0x00000000u)#define CSL_IRDA_LSR_STS_FIFO_E_MASK     (0x00000002u)#define CSL_IRDA_LSR_STS_FIFO_E_SHIFT    (0x00000001u)#define CSL_IRDA_LSR_STS_FIFO_E_RESETVAL (0x00000001u)#define CSL_IRDA_LSR_RX_FIFO_E_MASK      (0x00000001u)#define CSL_IRDA_LSR_RX_FIFO_E_SHIFT     (0x00000000u)#define CSL_IRDA_LSR_RX_FIFO_E_RESETVAL  (0x00000001u)#define CSL_IRDA_LSR_RESETVAL            (0x00000083u)/* ADDR2 */#define CSL_IRDA_ADDR2_ADDR_MASK         (0x000000FFu)#define CSL_IRDA_ADDR2_ADDR_SHIFT        (0x00000000u)#define CSL_IRDA_ADDR2_ADDR_RESETVAL     (0x00000000u)#define CSL_IRDA_ADDR2_RESETVAL          (0x00000000u)/* SPR_TLR */#define CSL_IRDA_SPR_TLR_SPR_TLR_MASK    (0x000000FFu)#define CSL_IRDA_SPR_TLR_SPR_TLR_SHIFT   (0x00000000u)#define CSL_IRDA_SPR_TLR_SPR_TLR_RESETVAL (0x00000000u)#define CSL_IRDA_SPR_TLR_RESETVAL        (0x00000000u)/* SPR */#define CSL_IRDA_SPR_SPR_WORD_MASK       (0x000000FFu)#define CSL_IRDA_SPR_SPR_WORD_SHIFT      (0x00000000u)#define CSL_IRDA_SPR_SPR_WORD_RESETVAL   (0x00000000u)#define CSL_IRDA_SPR_RESETVAL            (0x00000000u)/* TLR */#define CSL_IRDA_TLR_RX_FIFO_TRIG_DMA_MASK (0x000000F0u)#define CSL_IRDA_TLR_RX_FIFO_TRIG_DMA_SHIFT (0x00000004u)#define CSL_IRDA_TLR_RX_FIFO_TRIG_DMA_RESETVAL (0x00000000u)#define CSL_IRDA_TLR_TX_FIFO_TRIG_DMA_MASK (0x0000000Fu)#define CSL_IRDA_TLR_TX_FIFO_TRIG_DMA_SHIFT (0x00000000u)#define CSL_IRDA_TLR_TX_FIFO_TRIG_DMA_RESETVAL (0x00000000u)#define CSL_IRDA_TLR_RESETVAL            (0x00000000u)/* MDR1 */#define CSL_IRDA_MDR1_FRAME_END_MODE_MASK (0x00000080u)#define CSL_IRDA_MDR1_FRAME_END_MODE_SHIFT (0x00000007u)#define CSL_IRDA_MDR1_FRAME_END_MODE_RESETVAL (0x00000000u)#define CSL_IRDA_MDR1_FRAME_END_MODE_FRM_LEN (0x00000000u)#define CSL_IRDA_MDR1_FRAME_END_MODE_EOT (0x00000001u)#define CSL_IRDA_MDR1_SIP_MODE_MASK      (0x00000040u)#define CSL_IRDA_MDR1_SIP_MODE_SHIFT     (0x00000006u)#define CSL_IRDA_MDR1_SIP_MODE_RESETVAL  (0x00000000u)#define CSL_IRDA_MDR1_SIP_MODE_MANUAL    (0x00000000u)#define CSL_IRDA_MDR1_SIP_MODE_AUTOMATIC (0x00000001u)#define CSL_IRDA_MDR1_SCT_MASK           (0x00000020u)#define CSL_IRDA_MDR1_SCT_SHIFT          (0x00000005u)#define CSL_IRDA_MDR1_SCT_RESETVAL       (0x00000000u)#define CSL_IRDA_MDR1_SCT_DISABLE        (0x00000000u)#define CSL_IRDA_MDR1_SCT_ENABLE         (0x00000001u)#define CSL_IRDA_MDR1_SET_TXIR_MASK      (0x00000010u)#define CSL_IRDA_MDR1_SET_TXIR_SHIFT     (0x00000004u)#define CSL_IRDA_MDR1_SET_TXIR_RESETVAL  (0x00000000u)#define CSL_IRDA_MDR1_SET_TXIR_NONE      (0x00000000u)#define CSL_IRDA_MDR1_SET_TXIR_HIGH      (0x00000001u)#define CSL_IRDA_MDR1_IR_SLEEP_MASK      (0x00000008u)#define CSL_IRDA_MDR1_IR_SLEEP_SHIFT     (0x00000003u)#define CSL_IRDA_MDR1_IR_SLEEP_RESETVAL  (0x00000000u)#define CSL_IRDA_MDR1_IR_SLEEP_DISABLE   (0x00000000u)#define CSL_IRDA_MDR1_IR_SLEEP_ENABLE    (0x00000001u)#define CSL_IRDA_MDR1_MODE_SELECT_MASK   (0x00000007u)#define CSL_IRDA_MDR1_MODE_SELECT_SHIFT  (0x00000000u)#define CSL_IRDA_MDR1_MODE_SELECT_RESETVAL (0x00000007u)#define CSL_IRDA_MDR1_MODE_SELECT_16X    (0x00000000u)#define CSL_IRDA_MDR1_MODE_SELECT_SIR    (0x00000001u)#define CSL_IRDA_MDR1_MODE_SELECT_16XAUTOBAUD (0x00000002u)#define CSL_IRDA_MDR1_MODE_SELECT_13X    (0x00000003u)#define CSL_IRDA_MDR1_MODE_SELECT_MIR    (0x00000004u)#define CSL_IRDA_MDR1_MODE_SELECT_FIR    (0x00000005u)#define CSL_IRDA_MDR1_MODE_SELECT_DISABLE (0x00000007u)#define CSL_IRDA_MDR1_RESETVAL           (0x00000007u)/* MDR2 */#define CSL_IRDA_MDR2_STS_FIFO_TRIG_MASK (0x00000006u)#define CSL_IRDA_MDR2_STS_FIFO_TRIG_SHIFT (0x00000001u)#define CSL_IRDA_MDR2_STS_FIFO_TRIG_RESETVAL (0x00000000u)#define CSL_IRDA_MDR2_STS_FIFO_TRIG_1    (0x00000000u)#define CSL_IRDA_MDR2_STS_FIFO_TRIG_4    (0x00000001u)#define CSL_IRDA_MDR2_STS_FIFO_TRIG_7    (0x00000002u)#define CSL_IRDA_MDR2_STS_FIFO_TRIG_8    (0x00000003u)#define CSL_IRDA_MDR2_IRTX_UNDERRUN_MASK (0x00000001u)#define CSL_IRDA_MDR2_IRTX_UNDERRUN_SHIFT (0x00000000u)#define CSL_IRDA_MDR2_IRTX_UNDERRUN_RESETVAL (0x00000000u)#define CSL_IRDA_MDR2_RESETVAL           (0x00000000u)/* SFLSR_TXFLL */#define CSL_IRDA_SFLSR_TXFLL_SFLSR_TXFLL_MASK (0x000000FFu)#define CSL_IRDA_SFLSR_TXFLL_SFLSR_TXFLL_SHIFT (0x00000000u)#define CSL_IRDA_SFLSR_TXFLL_SFLSR_TXFLL_RESETVAL (0x00000000u)#define CSL_IRDA_SFLSR_TXFLL_RESETVAL    (0x00000000u)/* TXFLL */#define CSL_IRDA_TXFLL_TXFLL_MASK        (0x000000FFu)#define CSL_IRDA_TXFLL_TXFLL_SHIFT       (0x00000000u)#define CSL_IRDA_TXFLL_TXFLL_RESETVAL    (0x00000000u)#define CSL_IRDA_TXFLL_RESETVAL          (0x00000000u)/* SFLSR */#define CSL_IRDA_SFLSR_OE_ERROR_MASK     (0x00000010u)#define CSL_IRDA_SFLSR_OE_ERROR_SHIFT    (0x00000004u)#define CSL_IRDA_SFLSR_OE_ERROR_RESETVAL (0x00000000u)#define CSL_IRDA_SFLSR_FRAME_TOO_LONG_ERROR_MASK (0x00000008u)#define CSL_IRDA_SFLSR_FRAME_TOO_LONG_ERROR_SHIFT (0x00000003u)#define CSL_IRDA_SFLSR_FRAME_TOO_LONG_ERROR_RESETVAL (0x00000000u)#define CSL_IRDA_SFLSR_ABORT_DETECT_MASK (0x00000004u)#define CSL_IRDA_SFLSR_ABORT_DETECT_SHIFT (0x00000002u)#define CSL_IRDA_SFLSR_ABORT_DETECT_RESETVAL (0x00000000u)#define CSL_IRDA_SFLSR_CRC_ERROR_MASK    (0x00000002u)#define CSL_IRDA_SFLSR_CRC_ERROR_SHIFT   (0x00000001u)#define CSL_IRDA_SFLSR_CRC_ERROR_RESETVAL (0x00000000u)#define CSL_IRDA_SFLSR_RESETVAL          (0x00000000u)/* RESUME_TXFLH */#define CSL_IRDA_RESUME_TXFLH_RESUME_TXFLH_MASK (0x000000FFu)#define CSL_IRDA_RESUME_TXFLH_RESUME_TXFLH_SHIFT (0x00000000u)#define CSL_IRDA_RESUME_TXFLH_RESUME_TXFLH_RESETVAL (0x00000000u)#define CSL_IRDA_RESUME_TXFLH_RESETVAL   (0x00000000u)/* RESUME */#define CSL_IRDA_RESUME_RESUME_MASK      (0x000000FFu)#define CSL_IRDA_RESUME_RESUME_SHIFT     (0x00000000u)#define CSL_IRDA_RESUME_RESUME_RESETVAL  (0x00000000u)
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#dsp #音频处理 #中的运用
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