📄 cslr_irda.h

📁 dsp在音频处理中的运用
💻 H
📖 第 1 页 / 共 3 页
字号:
12 3 下一页
#ifndef _CSLR_IRDA_001_H_#define _CSLR_IRDA_001_H_#include <cslr.h>#include <tistdtypes.h>/**************************************************************************\* Register Overlay Structure\**************************************************************************/typedef struct  {    volatile Uint8 RHR_THR_DLL;    const char RSVD0[3];    volatile Uint8 IER_DLH;    const char RSVD1[3];    volatile Uint8 IIR_FCR_EFR;    const char RSVD2[3];    volatile Uint8 LCR;    const char RSVD3[3];    volatile Uint8 MCR_ADDR1;    const char RSVD4[3];    volatile Uint8 LSR_ADDR2;    const char RSVD5[7];    volatile Uint8 SPR_TLR;    const char RSVD6[3];    volatile Uint8 MDR1;    const char RSVD7[3];    volatile Uint8 MDR2;    const char RSVD8[3];    volatile Uint8 SFLSR_TXFLL;    const char RSVD9[3];    volatile Uint8 RESUME_TXFLH;    const char RSVD10[3];    volatile Uint8 SFREGL_RXFLL;    const char RSVD11[3];    volatile Uint8 SFREGH_RXFLH;    const char RSVD12[3];    volatile Uint8 BLR;    const char RSVD13[3];    volatile Uint8 ACREG;    const char RSVD14[3];    volatile Uint8 SCR;    const char RSVD15[3];    volatile Uint8 SSR;    const char RSVD16[3];    volatile Uint8 EBLR;    const char RSVD17[7];    volatile Uint8 MVR;    const char RSVD18[3];    volatile Uint8 SYSC;    const char RSVD19[3];    volatile Uint8 SYSS;    const char RSVD20[3];    volatile Uint8 WER;} CSL_IrdaRegs;/**************************************************************************\* Overlay structure typedef definition\**************************************************************************/typedef volatile CSL_IrdaRegs  * CSL_IrdaRegsOvly;/**************************************************************************\* Field Definition Macros\**************************************************************************//* RHR_THR_DLL */#define CSL_IRDA_RHR_THR_DLL_RHR_THR_DLL_MASK (0x000000FFu)#define CSL_IRDA_RHR_THR_DLL_RHR_THR_DLL_SHIFT (0x00000000u)#define CSL_IRDA_RHR_THR_DLL_RHR_THR_DLL_RESETVAL (0x00000000u)#define CSL_IRDA_RHR_THR_DLL_RESETVAL    (0x00000000u)/* RHR */#define CSL_IRDA_RHR_RHR_MASK            (0x000000FFu)#define CSL_IRDA_RHR_RHR_SHIFT           (0x00000000u)#define CSL_IRDA_RHR_RHR_RESETVAL        (0x00000000u)#define CSL_IRDA_RHR_RESETVAL            (0x00000000u)/* THR */#define CSL_IRDA_THR_THR_MASK            (0x000000FFu)#define CSL_IRDA_THR_THR_SHIFT           (0x00000000u)#define CSL_IRDA_THR_THR_RESETVAL        (0x00000000u)#define CSL_IRDA_THR_RESETVAL            (0x00000000u)/* DLL */#define CSL_IRDA_DLL_CLOCK_LSB_MASK      (0x000000FFu)#define CSL_IRDA_DLL_CLOCK_LSB_SHIFT     (0x00000000u)#define CSL_IRDA_DLL_CLOCK_LSB_RESETVAL  (0x00000000u)#define CSL_IRDA_DLL_RESETVAL            (0x00000000u)/* IER_DLH */#define CSL_IRDA_IER_DLH_IER_DLH_MASK    (0x000000FFu)#define CSL_IRDA_IER_DLH_IER_DLH_SHIFT   (0x00000000u)#define CSL_IRDA_IER_DLH_IER_DLH_RESETVAL (0x00000000u)#define CSL_IRDA_IER_DLH_RESETVAL        (0x00000000u)/* IER */#define CSL_IRDA_IER_EOF_IT_MASK         (0x00000080u)#define CSL_IRDA_IER_EOF_IT_SHIFT        (0x00000007u)#define CSL_IRDA_IER_EOF_IT_RESETVAL     (0x00000000u)#define CSL_IRDA_IER_LINE_STS_IT_MASK    (0x00000040u)#define CSL_IRDA_IER_LINE_STS_IT_SHIFT   (0x00000006u)#define CSL_IRDA_IER_LINE_STS_IT_RESETVAL (0x00000000u)#define CSL_IRDA_IER_TX_STATUS_IT_MASK   (0x00000020u)#define CSL_IRDA_IER_TX_STATUS_IT_SHIFT  (0x00000005u)#define CSL_IRDA_IER_TX_STATUS_IT_RESETVAL (0x00000000u)#define CSL_IRDA_IER_STS_FIFO_TRIG_IT_MASK (0x00000010u)#define CSL_IRDA_IER_STS_FIFO_TRIG_IT_SHIFT (0x00000004u)#define CSL_IRDA_IER_STS_FIFO_TRIG_IT_RESETVAL (0x00000000u)#define CSL_IRDA_IER_RX_OVERRUN_IT_MASK  (0x00000008u)#define CSL_IRDA_IER_RX_OVERRUN_IT_SHIFT (0x00000003u)#define CSL_IRDA_IER_RX_OVERRUN_IT_RESETVAL (0x00000000u)#define CSL_IRDA_IER_LAST_RX_BYTE_IT_MASK (0x00000004u)#define CSL_IRDA_IER_LAST_RX_BYTE_IT_SHIFT (0x00000002u)#define CSL_IRDA_IER_LAST_RX_BYTE_IT_RESETVAL (0x00000000u)#define CSL_IRDA_IER_THR_IT_MASK         (0x00000002u)#define CSL_IRDA_IER_THR_IT_SHIFT        (0x00000001u)#define CSL_IRDA_IER_THR_IT_RESETVAL     (0x00000000u)#define CSL_IRDA_IER_RHR_IT_MASK         (0x00000001u)#define CSL_IRDA_IER_RHR_IT_SHIFT        (0x00000000u)#define CSL_IRDA_IER_RHR_IT_RESETVAL     (0x00000000u)#define CSL_IRDA_IER_RESETVAL            (0x00000000u)/* DLH */#define CSL_IRDA_DLH_CLOCK_MSB_MASK      (0x0000003Fu)#define CSL_IRDA_DLH_CLOCK_MSB_SHIFT     (0x00000000u)#define CSL_IRDA_DLH_CLOCK_MSB_RESETVAL  (0x00000000u)#define CSL_IRDA_DLH_RESETVAL            (0x00000000u)/* IIR_FCR_EFR */#define CSL_IRDA_IIR_FCR_EFR_IIR_FCR_EFR_MASK (0x000000FFu)#define CSL_IRDA_IIR_FCR_EFR_IIR_FCR_EFR_SHIFT (0x00000000u)#define CSL_IRDA_IIR_FCR_EFR_IIR_FCR_EFR_RESETVAL (0x00000000u)#define CSL_IRDA_IIR_FCR_EFR_RESETVAL    (0x00000000u)/* IIR */#define CSL_IRDA_IIR_EOF_IT_MASK         (0x00000080u)#define CSL_IRDA_IIR_EOF_IT_SHIFT        (0x00000007u)#define CSL_IRDA_IIR_EOF_IT_RESETVAL     (0x00000000u)#define CSL_IRDA_IIR_LINE_STS_IT_MASK    (0x00000040u)#define CSL_IRDA_IIR_LINE_STS_IT_SHIFT   (0x00000006u)#define CSL_IRDA_IIR_LINE_STS_IT_RESETVAL (0x00000000u)#define CSL_IRDA_IIR_TX_STATUS_IT_MASK   (0x00000020u)#define CSL_IRDA_IIR_TX_STATUS_IT_SHIFT  (0x00000005u)#define CSL_IRDA_IIR_TX_STATUS_IT_RESETVAL (0x00000000u)#define CSL_IRDA_IIR_STS_FIFO_IT_MASK    (0x00000010u)#define CSL_IRDA_IIR_STS_FIFO_IT_SHIFT   (0x00000004u)#define CSL_IRDA_IIR_STS_FIFO_IT_RESETVAL (0x00000000u)#define CSL_IRDA_IIR_RX_OE_IT_MASK       (0x00000008u)#define CSL_IRDA_IIR_RX_OE_IT_SHIFT      (0x00000003u)#define CSL_IRDA_IIR_RX_OE_IT_RESETVAL   (0x00000000u)#define CSL_IRDA_IIR_RX_FIFO_LAST_BYTE_IT_MASK (0x00000004u)#define CSL_IRDA_IIR_RX_FIFO_LAST_BYTE_IT_SHIFT (0x00000002u)#define CSL_IRDA_IIR_RX_FIFO_LAST_BYTE_IT_RESETVAL (0x00000000u)#define CSL_IRDA_IIR_THR_IT_MASK         (0x00000002u)#define CSL_IRDA_IIR_THR_IT_SHIFT        (0x00000001u)#define CSL_IRDA_IIR_THR_IT_RESETVAL     (0x00000000u)#define CSL_IRDA_IIR_RHR_IT_MASK         (0x00000001u)#define CSL_IRDA_IIR_RHR_IT_SHIFT        (0x00000000u)#define CSL_IRDA_IIR_RHR_IT_RESETVAL     (0x00000000u)#define CSL_IRDA_IIR_RESETVAL            (0x00000000u)/* EFR */#define CSL_IRDA_EFR_AUTO_CTS_EN_MASK    (0x00000080u)#define CSL_IRDA_EFR_AUTO_CTS_EN_SHIFT   (0x00000007u)#define CSL_IRDA_EFR_AUTO_CTS_EN_RESETVAL (0x00000000u)#define CSL_IRDA_EFR_AUTO_CTS_EN_DISABLE (0x00000000u)#define CSL_IRDA_EFR_AUTO_CTS_EN_ENABLE  (0x00000001u)#define CSL_IRDA_EFR_AUTO_RTS_EN_MASK    (0x00000040u)#define CSL_IRDA_EFR_AUTO_RTS_EN_SHIFT   (0x00000006u)#define CSL_IRDA_EFR_AUTO_RTS_EN_RESETVAL (0x00000000u)#define CSL_IRDA_EFR_AUTO_RTS_EN_DISABLE (0x00000000u)#define CSL_IRDA_EFR_AUTO_RTS_EN_ENABLE  (0x00000001u)#define CSL_IRDA_EFR_SPECIAL_CHAR_DETECT_MASK (0x00000020u)#define CSL_IRDA_EFR_SPECIAL_CHAR_DETECT_SHIFT (0x00000005u)#define CSL_IRDA_EFR_SPECIAL_CHAR_DETECT_RESETVAL (0x00000000u)#define CSL_IRDA_EFR_SPECIAL_CHAR_DETECT_DISABLE (0x00000000u)#define CSL_IRDA_EFR_SPECIAL_CHAR_DETECT_ENABLE (0x00000001u)#define CSL_IRDA_EFR_ENHANCED_EN_MASK    (0x00000010u)#define CSL_IRDA_EFR_ENHANCED_EN_SHIFT   (0x00000004u)#define CSL_IRDA_EFR_ENHANCED_EN_RESETVAL (0x00000000u)#define CSL_IRDA_EFR_ENHANCED_EN_DISABLE (0x00000000u)#define CSL_IRDA_EFR_ENHANCED_EN_ENABLE  (0x00000001u)#define CSL_IRDA_EFR_SW_FLOW_CONTROL_MASK (0x0000000Fu)#define CSL_IRDA_EFR_SW_FLOW_CONTROL_SHIFT (0x00000000u)#define CSL_IRDA_EFR_SW_FLOW_CONTROL_RESETVAL (0x00000000u)#define CSL_IRDA_EFR_RESETVAL            (0x00000000u)/* FCR */#define CSL_IRDA_FCR_RX_FIFO_TRIG_MASK   (0x000000C0u)#define CSL_IRDA_FCR_RX_FIFO_TRIG_SHIFT  (0x00000006u)#define CSL_IRDA_FCR_RX_FIFO_TRIG_RESETVAL (0x00000000u)#define CSL_IRDA_FCR_TX_FIFO_TRIG_MASK   (0x00000030u)#define CSL_IRDA_FCR_TX_FIFO_TRIG_SHIFT  (0x00000004u)#define CSL_IRDA_FCR_TX_FIFO_TRIG_RESETVAL (0x00000000u)#define CSL_IRDA_FCR_DMA_MODE_MASK       (0x00000008u)#define CSL_IRDA_FCR_DMA_MODE_SHIFT      (0x00000003u)#define CSL_IRDA_FCR_DMA_MODE_RESETVAL   (0x00000000u)#define CSL_IRDA_FCR_TX_FIFO_CLEAR_MASK  (0x00000004u)#define CSL_IRDA_FCR_TX_FIFO_CLEAR_SHIFT (0x00000002u)#define CSL_IRDA_FCR_TX_FIFO_CLEAR_RESETVAL (0x00000000u)#define CSL_IRDA_FCR_TX_FIFO_CLEAR_DISABLE (0x00000000u)#define CSL_IRDA_FCR_TX_FIFO_CLEAR_ENABLE (0x00000001u)#define CSL_IRDA_FCR_RX_FIFO_CLEAR_MASK  (0x00000002u)#define CSL_IRDA_FCR_RX_FIFO_CLEAR_SHIFT (0x00000001u)#define CSL_IRDA_FCR_RX_FIFO_CLEAR_RESETVAL (0x00000000u)#define CSL_IRDA_FCR_RX_FIFO_CLEAR_DISABLE (0x00000000u)#define CSL_IRDA_FCR_RX_FIFO_CLEAR_ENABLE (0x00000001u)#define CSL_IRDA_FCR_FIFO_EN_MASK        (0x00000001u)#define CSL_IRDA_FCR_FIFO_EN_SHIFT       (0x00000000u)#define CSL_IRDA_FCR_FIFO_EN_RESETVAL    (0x00000000u)#define CSL_IRDA_FCR_FIFO_EN_DISABLE     (0x00000000u)#define CSL_IRDA_FCR_FIFO_EN_ENABLE      (0x00000001u)#define CSL_IRDA_FCR_RESETVAL            (0x00000000u)/* LCR */#define CSL_IRDA_LCR_DIV_EN_MASK         (0x00000080u)#define CSL_IRDA_LCR_DIV_EN_SHIFT        (0x00000007u)#define CSL_IRDA_LCR_DIV_EN_RESETVAL     (0x00000000u)#define CSL_IRDA_LCR_DIV_EN_DISABLE      (0x00000000u)#define CSL_IRDA_LCR_DIV_EN_ENABLE       (0x00000001u)#define CSL_IRDA_LCR_BREAK_EN_MASK       (0x00000040u)#define CSL_IRDA_LCR_BREAK_EN_SHIFT      (0x00000006u)#define CSL_IRDA_LCR_BREAK_EN_RESETVAL   (0x00000000u)#define CSL_IRDA_LCR_BREAK_EN_DISABLE    (0x00000000u)#define CSL_IRDA_LCR_BREAK_EN_ENABLE     (0x00000001u)#define CSL_IRDA_LCR_PARITY_TYPE2_MASK   (0x00000020u)#define CSL_IRDA_LCR_PARITY_TYPE2_SHIFT  (0x00000005u)#define CSL_IRDA_LCR_PARITY_TYPE2_RESETVAL (0x00000000u)
12 3 下一页
💿 文件大小 2456 K
👤 上传用户 princessmeng
📂 所属分类 VC书籍
🏷️ 相关标签

#dsp #音频处理 #中的运用
⌨️ 快捷键说明

复制代码 Ctrl + C
搜索代码 Ctrl + F
全屏模式 F11
切换主题 Ctrl + Shift + D
显示快捷键 ?
增大字号 Ctrl + =
减小字号 Ctrl + -