csl_clkrstaux.h

dsp在音频处理中的运用

			_arm_idlect2 |= CSL_FMKT(CLKRST_ARM_IDLECT2_DMACK_REQ, ACTIVE_ONREQ);
		}

     /* To Enable/Disable the Clock Supplied to MPU Timer */
		if (ckEnable & (1 << i++)) {
			_arm_idlect2 |= CSL_FMKT(CLKRST_ARM_IDLECT2_EN_TIMCK, ACTIVE);
		}

     /* To Enable/Disable the Clock Supplied to MPUI */
		if (ckEnable & (1 << i++)) {
			_arm_idlect2 |= CSL_FMKT(CLKRST_ARM_IDLECT2_EN_APICK, ACTIVE);
		}

     /* To Skip the DPLL Bit in the ckEnable Variable */
      i++;

     /* To Skip the IF Bit in the ckEnable Variable */
      i++;

     /* To Enable/Disable the Clock Supplied to LCD Controller */
		if (ckEnable & (1 << i++)) {
			_arm_idlect2 |= CSL_FMKT(CLKRST_ARM_IDLECT2_EN_LCDCK, ACTIVE);
		}

     /* To Enable/Disable the Clock Supplied to External Peripherals */
		if (ckEnable & (1 << i++)) {
			_arm_idlect2 |= CSL_FMKT(CLKRST_ARM_IDLECT2_EN_PERCK, ACTIVE);
		}

     /* To Enable/Disable the Clock Supplied to OS Timer */
		if (ckEnable & (1 << i++)) {
			_arm_idlect2 |= CSL_FMKT(CLKRST_ARM_IDLECT2_EN_XORPCK, ACTIVE);
		}

     /* To Enable/Disable the Clock Supplied to Watch Dog Timer */
		if (ckEnable & (1 << i++)) {
			_arm_idlect2 |= CSL_FMKT(CLKRST_ARM_IDLECT2_EN_WDTCK, ACTIVE);
		}

     /* To Enable/Disable the Clock Supplied to OCPI */
		if (ckEnable & (1 << i++)) {
			_arm_idlect3 |= CSL_FMKT(CLKRST_ARM_IDLECT3_EN_OCPI_CK, ACTIVE);
		}

     /* To Enable/Disable the Clock Supplied to TC1 */
		if (ckEnable & (1 << i++)) {
			_arm_idlect3 |= CSL_FMKT(CLKRST_ARM_IDLECT3_EN_TC1_CK, ACTIVE);
		}

     /* To Enable/Disable the Clock Supplied to TC2 */
		if (ckEnable & (1 << i++)) {
			_arm_idlect3 |= CSL_FMKT(CLKRST_ARM_IDLECT3_EN_TC2_CK, ACTIVE);
		}

     /* To Enable/Disable the Clock Supplied to DSP */
		if (ckEnable & (1 << i++)) {
			_arm_ckctl = CSL_FMKT(CLKRST_ARM_CKCTL_EN_DSPCK, ACTIVE);
		}

     /* To Enable/Disable the Clock Supplied to GPIO */
		if (ckEnable & (1 << i++)) {
			_arm_idlect2 |= CSL_FMKT(CLKRST_ARM_IDLECT2_EN_GPIOCK, ACTIVE);
		}


	if (CSL_CLKRST_CMD_CLK_ENABLE == cmd) {
		hClkrst->regs->ARM_IDLECT2 |= _arm_idlect2;
		hClkrst->regs->ARM_IDLECT3 |= _arm_idlect3;
		hClkrst->regs->ARM_CKCTL |= _arm_ckctl;
	} else if (CSL_CLKRST_CMD_CLK_DISABLE == cmd) {
		hClkrst->regs->ARM_IDLECT2 &= ~_arm_idlect2;
		hClkrst->regs->ARM_IDLECT3 &= ~_arm_idlect3;
		hClkrst->regs->ARM_CKCTL &= ~_arm_ckctl;
	}

}


static inline 
void CSL_clkrstReset(
		CSL_ClkrstHandle        hClkrst,
		CSL_ClkrstHwControlCmd  cmd,
		Uint16                  resetSrc
		)
{

	Uint32 i=0;
	Uint32 _arm_rstct1=0;
    Uint32 _rstct_=0;


     switch(cmd) 
    {
      case CSL_CLKRST_CMD_RESET_IN: 
        /* To Do a MPU Reset */  
        i=0;
		if (resetSrc & (1 << i)) {
            _rstct_= CSL_CLKRST_ARM_RSTCT1_ARM_RST_MPU_RESET;
			CSL_FINSR(_arm_rstct1, i, i, _rstct_);
		}

        /* To Do a DSP Reset */  
        i++;
		if (resetSrc & (1 << i)) {
            _rstct_= CSL_CLKRST_ARM_RSTCT1_DSP_EN_MGS3_RESET;
			CSL_FINSR(_arm_rstct1, i, i, _rstct_);
		}

        /* To Do a DSP EMIF Reset */  
        i++;
		if (resetSrc & (1 << i)) {
            _rstct_= CSL_CLKRST_ARM_RSTCT1_DSP_RST_EMIF_API_RESET;
			CSL_FINSR(_arm_rstct1, i, i, _rstct_);
		}

        /* To Do a Global System (OMAP 3.2) Reset */  
        i++;
		if (resetSrc & (1 << i)) {
            _rstct_= CSL_CLKRST_ARM_RSTCT1_SW_RST_OMAP3_RESET;
			CSL_FINSR(_arm_rstct1, i, i, _rstct_);
		}

        /* To Do a MPU Peripheral Reset */  
	    if (resetSrc & (1 << 4)) {
            _rstct_= CSL_CLKRST_ARM_RSTCT2_PER_EN_PER_RESET;
 		    CSL_FINS(hClkrst->regs->ARM_RSTCT2, CLKRST_ARM_RSTCT2_PER_EN, _rstct_);
	    }
        break;

      case CSL_CLKRST_CMD_RESET_OUT:
        /* To Enable a MPU Clock Domain */  
        i=0;
		if (resetSrc & (1 << i)) {
            _rstct_= CSL_CLKRST_ARM_RSTCT1_ARM_RST_MPU_ENABLED;
			CSL_FINSR(_arm_rstct1, i, i, _rstct_);
		}

        /* To Enable the DSP */  
        i++;
		if (resetSrc & (1 << i)) {
            _rstct_= CSL_CLKRST_ARM_RSTCT1_DSP_EN_MGS3_ENABLED;
			CSL_FINSR(_arm_rstct1, i, i, _rstct_);
		}

        /* To Enable the DSP EMIF  */  
        i++;
		if (resetSrc & (1 << i)) {
            _rstct_= CSL_CLKRST_ARM_RSTCT1_DSP_RST_EMIF_API_ENABLED;
			CSL_FINSR(_arm_rstct1, i, i, _rstct_);
		}

        /* To Enable Global System (OMAP 3.2) */  
        i++;
		if (resetSrc & (1 << i)) {
            _rstct_= CSL_CLKRST_ARM_RSTCT1_SW_RST_OMAP3_ENABLED;
			CSL_FINSR(_arm_rstct1, i, i, _rstct_);
		}

        /* To Enable MPU Peripherals */  
	    if (resetSrc & (1 << 4)) {
            _rstct_= CSL_CLKRST_ARM_RSTCT2_PER_EN_PER_ENABLED;
 		    CSL_FINS(hClkrst->regs->ARM_RSTCT2, CLKRST_ARM_RSTCT2_PER_EN, _rstct_);
	    }
        break;
              
    }



}

static inline 
void CSL_clkrstGetClkIdleEntry(
		CSL_ClkrstHandle        hClkrst,
		Uint16                  *ckIdleEntry
		)
{

	Uint32 i=0;
	Uint32 _arm_idlect1;
	Uint32 _arm_idlect3;


	_arm_idlect1 = hClkrst->regs->ARM_IDLECT1;
	_arm_idlect3 = hClkrst->regs->ARM_IDLECT3;
	*ckIdleEntry = 0, i=0 ;  

    /* To Get the Idle Entry of the Clock Supplied to External Clock */
	if (_arm_idlect1 & CSL_FMKT(CLKRST_ARM_IDLECT1_IDLCLKOUT_ARM, IDLE_STOP)) {
        *ckIdleEntry |= (1 << i);        
		}

   /* To Skip the DMA Bit in the ckIdleEntry Variable */
    i++;

    /* To Get the Idle Entry of the MPU Timer Clock */
    i++;
	if (_arm_idlect1 & CSL_FMKT(CLKRST_ARM_IDLECT1_IDLTIM_ARM, IDLE_STOP)) {
        *ckIdleEntry |= (1 << i);        
		}

    /* To Get the Idle Entry of the MPUI Clock */
    i++;
	if (_arm_idlect1 & CSL_FMKT(CLKRST_ARM_IDLECT1_IDLAPI_ARM, IDLE_STOP)) {
        *ckIdleEntry |= (1 << i);        
		}

    /* To Get the Idle Entry of the DPLL */
    i++;
	if (_arm_idlect1 & CSL_FMKT(CLKRST_ARM_IDLECT1_IDLDPLL_ARM, IDLE_STOP)) {
        *ckIdleEntry |= (1 << i);        
		}

    /* To Get the Idle Entry of the Clocks supplied to TIPB Bridge, DMA controller and TC */
    i++;
	if (_arm_idlect1 & CSL_FMKT(CLKRST_ARM_IDLECT1_IDLIF_ARM, IDLE_STOP)) {
        *ckIdleEntry |= (1 << i);        
		}

    /* To Get the Idle Entry of the Clocks supplied to LCD Controller */
    i++;
	if (_arm_idlect1 & CSL_FMKT(CLKRST_ARM_IDLECT1_IDLLCD_ARM, IDLE_STOP)) {
        *ckIdleEntry |= (1 << i);        
		}

    /* To Get the Idle Entry of the Arm External Peripheral Clock */
    i++;
	if (_arm_idlect1 & CSL_FMKT(CLKRST_ARM_IDLECT1_IDLPER_ARM, IDLE_STOP)) {
        *ckIdleEntry |= (1 << i);        
		}

    /* To Get the Idle Entry of the OS Timer and External Reference Perepheral Clock */
    i++;
	if (_arm_idlect1 & CSL_FMKT(CLKRST_ARM_IDLECT1_IDLXORP_ARM, IDLE_STOP)) {
        *ckIdleEntry |= (1 << i);        
		}

    /* To Get the Idle Entry of the WDT Clock */
    i++;
	if (_arm_idlect1 & CSL_FMKT(CLKRST_ARM_IDLECT1_IDLWDT_ARM, IDLE_STOP)) {
        *ckIdleEntry |= (1 << i);        
		}

    /* To Get the Idle Entry of the OCPI Clock */
    i++;
	if (_arm_idlect3 & CSL_FMKT(CLKRST_ARM_IDLECT3_IDLOCPI_ARM, IDLE_STOP)) {
        *ckIdleEntry |= (1 << i);        
		}

    /* To Get the Idle Entry of the TC1 Clock */
    i++;
	if (_arm_idlect3 & CSL_FMKT(CLKRST_ARM_IDLECT3_IDLTC1_ARM, IDLE_STOP)) {
        *ckIdleEntry |= (1 << i);        
		}

    /* To Get the Idle Entry of the TC2 Clock */
    i++;
	if (_arm_idlect3 & CSL_FMKT(CLKRST_ARM_IDLECT3_IDLTC2_ARM, IDLE_STOP)) {
        *ckIdleEntry |= (1 << i);        
		}

   /* Skip the DSP Bit in the ckIdleEntry Variable */
    i++;
    
    /* To Get the Idle Entry of the GPIO Clock */
    i++;
	if ( hClkrst->regs->ARM_IDLECT2 & CSL_FMKT(CLKRST_ARM_IDLECT2_EN_GPIOCK, ACTIVE)) {
        *ckIdleEntry |= (1 << i);        
		}



}

static inline 
void CSL_clkrstGetClkSource(
		CSL_ClkrstHandle        hClkrst,
		CSL_ClkrstClkSrc        *clkSource
		)
{

	*clkSource = (CSL_ClkrstClkSrc)(hClkrst->regs->ARM_CKCTL &
		                        CSL_CLKRST_ARM_CKCTL_ARM_TIMXO_MASK);

}

static inline 
void CSL_clkrstGetMpuInthCkSource(
		CSL_ClkrstHandle        hClkrst,
		CSL_ClkrstMpuInthCk     *mpuInthCkSrc
		)
{

	*mpuInthCkSrc = (CSL_ClkrstMpuInthCk)CSL_FEXT(hClkrst->regs->ARM_CKCTL, CLKRST_ARM_CKCTL_ARM_INTHCK_SEL);

}

static inline 
void CSL_clkrstGetClkScheme(
		CSL_ClkrstHandle               hClkrst,
		CSL_ClkrstHwSetupClkClkScheme  *clkPtr
		)
{

	Uint32 _arm_ckctl;

	_arm_ckctl = hClkrst->regs->ARM_CKCTL;
	clkPtr->clkDiv.dspDiv = CSL_FEXT(_arm_ckctl, CLKRST_ARM_CKCTL_DSPDIV);
	clkPtr->clkDiv.mpuDiv = CSL_FEXT(_arm_ckctl, CLKRST_ARM_CKCTL_ARMDIV);
	clkPtr->clkDiv.perDiv = CSL_FEXT(_arm_ckctl, CLKRST_ARM_CKCTL_PERDIV);
	clkPtr->clkDiv.lcdDiv = CSL_FEXT(_arm_ckctl, CLKRST_ARM_CKCTL_LCDDIV);
	clkPtr->clkDiv.tcDiv = CSL_FEXT(_arm_ckctl, CLKRST_ARM_CKCTL_TCDIV);
	clkPtr->clkDiv.dspmmuDiv = CSL_FEXT(_arm_ckctl, CLKRST_ARM_CKCTL_DSPMMUDIV);

	clkPtr->clkScheme = (CSL_ClkrstClkScheme)CSL_FEXT(hClkrst->regs->ARM_SYSST, CLKRST_ARM_SYSST_CLOCK_SELECT);

}

static inline 
void CSL_clkrstGetCkout(
		CSL_ClkrstHandle               hClkrst,
		CSL_ClkrstHwSetupClkCkout      *ckoutPtr
		)
{

	Uint32 _arm_ckout1;

	_arm_ckout1 = hClkrst->regs->ARM_CKOUT1;
	ckoutPtr->mpuDomain = (CSL_ClkrstCkoutType)CSL_FEXT(_arm_ckout1, CLKRST_ARM_CKOUT1_ACLKOUT);
	ckoutPtr->dspDomain = (CSL_ClkrstCkoutType)CSL_FEXT(_arm_ckout1, CLKRST_ARM_CKOUT1_DCLKOUT);
	ckoutPtr->tcDomain = (CSL_ClkrstCkoutType)CSL_FEXT(_arm_ckout1, CLKRST_ARM_CKOUT1_TCLKOUT);

}

static inline 
void CSL_clkrstGetPwrctl(
		CSL_ClkrstHandle               hClkrst,
		CSL_ClkrstHwSetupPwrctl        *pwrctlPtr
		)
{
	Uint32 _arm_ewupct;

	_arm_ewupct = hClkrst->regs->ARM_EWUPCT;
	pwrctlPtr->resPwr = (CSL_ClkrstRespwrTcIdlEntry)CSL_FEXT(_arm_ewupct, CLKRST_ARM_EWUPCT_REPWR_EN);
	pwrctlPtr->delayRespwrActiveToClkStart = CSL_FEXT(_arm_ewupct, CLKRST_ARM_EWUPCT_EXTPW);

}

static inline 
void CSL_clkrstGetWkupMode(
		CSL_ClkrstHandle               hClkrst,
		CSL_ClkrstWkupChipNwkup        *wkupModePtr
		)
{

	*wkupModePtr = (CSL_ClkrstWkupChipNwkup)CSL_FEXT(hClkrst->regs->ARM_IDLECT1, CLKRST_ARM_IDLECT1_WKUP_MODE);

}

#ifdef __cplusplus
}
#endif


#endif