csl_clkrstaux.h

dsp在音频处理中的运用

/* Updated by Ravindra Upadhyaya on 02-02-2005 */ 

#ifndef _CSL_CLKRSTAUX_H_
#define _CSL_CLKRSTAUX_H_

#include <csl_clkrst.h>

#ifdef __cplusplus
extern "C" {
#endif

static inline 
void CSL_clkrstClkIdleEntry(
		CSL_ClkrstHandle        hClkrst,
		Uint16                  ckIdleEntry
		)
{

	Uint32 i=0;
	Uint32 _arm_idlect1 = hClkrst->regs->ARM_IDLECT1 &
			          ~( CSL_FMKT(CLKRST_ARM_IDLECT1_IDLCLKOUT_ARM, IDLE_STOP) |
			             CSL_FMKT(CLKRST_ARM_IDLECT1_IDLTIM_ARM, IDLE_STOP) |
				         CSL_FMKT(CLKRST_ARM_IDLECT1_IDLAPI_ARM, IDLE_STOP) |
				         CSL_FMKT(CLKRST_ARM_IDLECT1_IDLDPLL_ARM, IDLE_STOP) |
				         CSL_FMKT(CLKRST_ARM_IDLECT1_IDLIF_ARM, IDLE_STOP) |
				         CSL_FMKT(CLKRST_ARM_IDLECT1_IDLLCD_ARM, IDLE_STOP) |
				         CSL_FMKT(CLKRST_ARM_IDLECT1_IDLPER_ARM, IDLE_STOP) |
				         CSL_FMKT(CLKRST_ARM_IDLECT1_IDLXORP_ARM, IDLE_STOP) |
				         CSL_FMKT(CLKRST_ARM_IDLECT1_IDLWDT_ARM, IDLE_STOP));
	Uint32 _arm_idlect2 = hClkrst->regs->ARM_IDLECT2 &
                      ~( CSL_FMKT(CLKRST_ARM_IDLECT2_EN_CKOUT_ARM, ACTIVE)|
				         CSL_FMKT(CLKRST_ARM_IDLECT2_EN_GPIOCK, ACTIVE)|
				         CSL_FMKT(CLKRST_ARM_IDLECT2_DMACK_REQ, ACTIVE_ONREQ)|
				         CSL_FMKT(CLKRST_ARM_IDLECT2_EN_TIMCK, ACTIVE)|
				         CSL_FMKT(CLKRST_ARM_IDLECT2_EN_APICK, ACTIVE)|
				         CSL_FMKT(CLKRST_ARM_IDLECT2_EN_LCDCK, ACTIVE)|
				         CSL_FMKT(CLKRST_ARM_IDLECT2_EN_PERCK, ACTIVE)|
				         CSL_FMKT(CLKRST_ARM_IDLECT2_EN_XORPCK, ACTIVE)|
				         CSL_FMKT(CLKRST_ARM_IDLECT2_EN_WDTCK, ACTIVE));
	Uint32 _arm_idlect3 = hClkrst->regs->ARM_IDLECT3 &
			          ~( CSL_FMKT(CLKRST_ARM_IDLECT3_IDLOCPI_ARM, IDLE_STOP) |
                         CSL_FMKT(CLKRST_ARM_IDLECT3_EN_OCPI_CK, ACTIVE) |
				         CSL_FMKT(CLKRST_ARM_IDLECT3_IDLTC1_ARM, IDLE_STOP) |
                         CSL_FMKT(CLKRST_ARM_IDLECT3_EN_TC1_CK, ACTIVE) |
				         CSL_FMKT(CLKRST_ARM_IDLECT3_IDLTC2_ARM, IDLE_STOP) |
                         CSL_FMKT(CLKRST_ARM_IDLECT3_EN_TC2_CK, ACTIVE));


    /* To Idle the Clock Supplied to External Clock */
	if (ckIdleEntry & (1 << i++)) {
		_arm_idlect1 |= CSL_FMKT(CLKRST_ARM_IDLECT1_IDLCLKOUT_ARM, IDLE_STOP);
		_arm_idlect2 |= CSL_FMKT(CLKRST_ARM_IDLECT2_EN_CKOUT_ARM, ACTIVE);
		}

   /* To Skip the DMA Bit in the ckIdleEntry Variable */
    i++;

    /* To Idle the MPU Timer Clock */
	if (ckIdleEntry & (1 << i++)) {
		_arm_idlect1 |= CSL_FMKT(CLKRST_ARM_IDLECT1_IDLTIM_ARM, IDLE_STOP);
		_arm_idlect2 |= CSL_FMKT(CLKRST_ARM_IDLECT2_EN_TIMCK, ACTIVE);
		}

    /* To Idle the MPUI Clock */
	if (ckIdleEntry & (1 << i++)) {
		_arm_idlect1 |= CSL_FMKT(CLKRST_ARM_IDLECT1_IDLAPI_ARM, IDLE_STOP);
		_arm_idlect2 |= CSL_FMKT(CLKRST_ARM_IDLECT2_EN_APICK, ACTIVE);
		}

    /* To Idle the DPLL */
	if (ckIdleEntry & (1 << i++)) {
		_arm_idlect1 |= CSL_FMKT(CLKRST_ARM_IDLECT1_IDLDPLL_ARM, IDLE_STOP);
		}

    /* To Idle the Clocks supplied to TIPB Bridge, DMA controller and TC */
	if (ckIdleEntry & (1 << i++)) {
		_arm_idlect1 |= CSL_FMKT(CLKRST_ARM_IDLECT1_IDLIF_ARM, IDLE_STOP);
		_arm_idlect2 |= CSL_FMKT(CLKRST_ARM_IDLECT2_DMACK_REQ, ACTIVE_ONREQ);
		}

    /* To Idle the Clocks supplied to LCD controller */
	if (ckIdleEntry & (1 << i++)) {
		_arm_idlect1 |= CSL_FMKT(CLKRST_ARM_IDLECT1_IDLLCD_ARM, IDLE_STOP);
		_arm_idlect2 |= CSL_FMKT(CLKRST_ARM_IDLECT2_EN_LCDCK, ACTIVE);
		}

    /* To Idle the Arm External Peripheral Clock */
	if (ckIdleEntry & (1 << i++)) {
		_arm_idlect1 |= CSL_FMKT(CLKRST_ARM_IDLECT1_IDLPER_ARM, IDLE_STOP);
		_arm_idlect2 |= CSL_FMKT(CLKRST_ARM_IDLECT2_EN_PERCK, ACTIVE);
		}

    /* To Idle the OS Timer and External Reference Perepheral Clock */
	if (ckIdleEntry & (1 << i++)) {
		_arm_idlect1 |= CSL_FMKT(CLKRST_ARM_IDLECT1_IDLXORP_ARM, IDLE_STOP);
		_arm_idlect2 |= CSL_FMKT(CLKRST_ARM_IDLECT2_EN_XORPCK, ACTIVE);
		}

    /* To Idle the WDT Clock */
	if (ckIdleEntry & (1 << i++)) {
		_arm_idlect1 |= CSL_FMKT(CLKRST_ARM_IDLECT1_IDLWDT_ARM, IDLE_STOP);
		_arm_idlect2 |= CSL_FMKT(CLKRST_ARM_IDLECT2_EN_APICK, ACTIVE);
		}

    /* To Idle the OCPI Clock */
	if (ckIdleEntry & (1 << i++)) {
		_arm_idlect3 |= CSL_FMKT(CLKRST_ARM_IDLECT3_IDLOCPI_ARM, IDLE_STOP);
		_arm_idlect3 |= CSL_FMKT(CLKRST_ARM_IDLECT3_EN_OCPI_CK, ACTIVE);
		}

    /* To Idle the TC1 Clock */
	if (ckIdleEntry & (1 << i++)) {
		_arm_idlect3 |= CSL_FMKT(CLKRST_ARM_IDLECT3_IDLTC1_ARM, IDLE_STOP);
		_arm_idlect3 |= CSL_FMKT(CLKRST_ARM_IDLECT3_EN_TC1_CK, ACTIVE);
		}

    /* To Idle the TC2 Clock */
	if (ckIdleEntry & (1 << i++)) {
		_arm_idlect3 |= CSL_FMKT(CLKRST_ARM_IDLECT3_IDLTC2_ARM, IDLE_STOP);
		_arm_idlect3 |= CSL_FMKT(CLKRST_ARM_IDLECT3_EN_TC2_CK, ACTIVE);
		}

   /* Skip the DSP Bit in the ckIdleEntry Variable */
     i++;

    /* To Enable the GPIO Clock and thereby its IDLE Configuration */
	if (ckIdleEntry & (1 << i++)) {
		_arm_idlect2 |= CSL_FMKT(CLKRST_ARM_IDLECT2_EN_GPIOCK, ACTIVE);
		}
	hClkrst->regs->ARM_IDLECT1 = _arm_idlect1;
	hClkrst->regs->ARM_IDLECT2 = _arm_idlect2;
	hClkrst->regs->ARM_IDLECT3 = _arm_idlect3;

}

static inline 
void CSL_clkrstMpuInthCkSource(
		CSL_ClkrstHandle        hClkrst,
		CSL_ClkrstMpuInthCk     mpuInthCkSrc
		)
{

	CSL_FINS(hClkrst->regs->ARM_CKCTL, CLKRST_ARM_CKCTL_ARM_INTHCK_SEL, mpuInthCkSrc);

}


static inline 
void CSL_clkrstClkSource(
		CSL_ClkrstHandle        hClkrst,
		CSL_ClkrstClkSrc        clkSource
		)
{

	CSL_FINS(hClkrst->regs->ARM_CKCTL, CLKRST_ARM_CKCTL_ARM_TIMXO, CSL_FEXT(clkSource, CLKRST_ARM_CKCTL_ARM_TIMXO));

}

static inline 
void CSL_clkrstClkScheme(
		CSL_ClkrstHandle               hClkrst,
		CSL_ClkrstHwSetupClkClkScheme  *clkPtr
		)
{

	Uint32 _arm_ckctl;

	hClkrst->regs->ARM_SYSST = CSL_FMK(CLKRST_ARM_SYSST_CLOCK_SELECT, clkPtr->clkScheme);

	_arm_ckctl = hClkrst->regs->ARM_CKCTL;
	CSL_FINS(_arm_ckctl, CLKRST_ARM_CKCTL_DSPDIV, clkPtr->clkDiv.dspDiv);
	CSL_FINS(_arm_ckctl, CLKRST_ARM_CKCTL_ARMDIV, clkPtr->clkDiv.mpuDiv);
	CSL_FINS(_arm_ckctl, CLKRST_ARM_CKCTL_PERDIV, clkPtr->clkDiv.perDiv);
	CSL_FINS(_arm_ckctl, CLKRST_ARM_CKCTL_LCDDIV, clkPtr->clkDiv.lcdDiv);
	CSL_FINS(_arm_ckctl, CLKRST_ARM_CKCTL_TCDIV, clkPtr->clkDiv.tcDiv);
	CSL_FINS(_arm_ckctl, CLKRST_ARM_CKCTL_DSPMMUDIV, clkPtr->clkDiv.dspmmuDiv);
	hClkrst->regs->ARM_CKCTL = _arm_ckctl;

}

static inline 
void CSL_clkrstCkout(
		CSL_ClkrstHandle               hClkrst,
		CSL_ClkrstHwSetupClkCkout      *ckoutPtr
		)
{

	Uint32 _arm_ckout1;

	_arm_ckout1 = hClkrst->regs->ARM_CKOUT1;
	CSL_FINS(_arm_ckout1, CLKRST_ARM_CKOUT1_ACLKOUT, ckoutPtr->mpuDomain);
	CSL_FINS(_arm_ckout1, CLKRST_ARM_CKOUT1_DCLKOUT, ckoutPtr->dspDomain);
	CSL_FINS(_arm_ckout1, CLKRST_ARM_CKOUT1_TCLKOUT, ckoutPtr->tcDomain);
	hClkrst->regs->ARM_CKOUT1 = _arm_ckout1;

}

static inline 
void CSL_clkrstPwrctl(
		CSL_ClkrstHandle               hClkrst,
		CSL_ClkrstHwSetupPwrctl        *pwrctlPtr
		)
{
	Uint32 _arm_ewupct;

	_arm_ewupct = hClkrst->regs->ARM_EWUPCT;
	CSL_FINS(_arm_ewupct, CLKRST_ARM_EWUPCT_REPWR_EN, pwrctlPtr->resPwr);
	CSL_FINS(_arm_ewupct, CLKRST_ARM_EWUPCT_EXTPW, pwrctlPtr->delayRespwrActiveToClkStart);
	hClkrst->regs->ARM_EWUPCT = _arm_ewupct;

}

static inline 
void CSL_clkrstWkupMode(
		CSL_ClkrstHandle               hClkrst,
		CSL_ClkrstWkupChipNwkup        wkupMode
		)
{

	CSL_FINS(hClkrst->regs->ARM_IDLECT1, CLKRST_ARM_IDLECT1_WKUP_MODE, wkupMode);

}

static inline 
void CSL_clkrstGetCkEn(
		CSL_ClkrstHandle        hClkrst,
		Uint16                  *ckEnable
		)
{

	Uint32 i=0;
	Uint32 _arm_idlect2 = 0;
	Uint32 _arm_idlect3 = 0;

	_arm_idlect2 = hClkrst->regs->ARM_IDLECT2;
	_arm_idlect3 = hClkrst->regs->ARM_IDLECT3;
	*ckEnable = 0;

     /* To get the status of the Clock Generated from DPLL1 Clock Output */
		if (_arm_idlect2 & CSL_FMKT(CLKRST_ARM_IDLECT2_EN_CKOUT_ARM, ACTIVE)) 
        {
			*ckEnable |= (1 << i);
		}

     /* To get the status of the Clock Supplied to System DMA Controller */
      i++;
		if (_arm_idlect2 & CSL_FMKT(CLKRST_ARM_IDLECT2_DMACK_REQ, ACTIVE_ONREQ))
        {
			*ckEnable |= (1 << i);
		}

     /* To get the status of the Clock Supplied to MPU Timer */
      i++;
		if (_arm_idlect2 & CSL_FMKT(CLKRST_ARM_IDLECT2_EN_TIMCK, ACTIVE)) {
			*ckEnable |= (1 << i);
		}

     /* To get the status of the Clock Supplied to MPUI */
      i++;
		if (_arm_idlect2 & CSL_FMKT(CLKRST_ARM_IDLECT2_EN_APICK, ACTIVE)) {
			*ckEnable |= (1 << i);
		}

     /* To Skip the DPLL Bit in the ckEnable Variable */
      i++;

     /* To Skip the IF Bit in the ckEnable Variable */
      i++;

     /* To get the status of the Clock Supplied to LCD Controller */
      i++;
		if (_arm_idlect2 & CSL_FMKT(CLKRST_ARM_IDLECT2_EN_LCDCK, ACTIVE)) {
			*ckEnable |= (1 << i);
		}

     /* To get the status of the Clock Supplied to External Peripherals */
      i++;
		if (_arm_idlect2 & CSL_FMKT(CLKRST_ARM_IDLECT2_EN_PERCK, ACTIVE)) {
			*ckEnable |= (1 << i);
		}

     /* To get the status of the Clock Supplied to OS Timer */
      i++;
		if (_arm_idlect2 & CSL_FMKT(CLKRST_ARM_IDLECT2_EN_XORPCK, ACTIVE)) {
			*ckEnable |= (1 << i);
		}

     /* To get the status of the Clock Supplied to Watch Dog Timer */
      i++;
		if (_arm_idlect2 & CSL_FMKT(CLKRST_ARM_IDLECT2_EN_WDTCK, ACTIVE)) {
			*ckEnable |= (1 << i);
		}

     /* To get the status of the Clock Supplied to OCPI */
      i++;
		if (_arm_idlect3 & CSL_FMKT(CLKRST_ARM_IDLECT3_EN_OCPI_CK, ACTIVE)) {
			*ckEnable |= (1 << i);
		}

     /* To get the status of the Clock Supplied to TC1 */
      i++;
		if (_arm_idlect3 & CSL_FMKT(CLKRST_ARM_IDLECT3_EN_TC1_CK, ACTIVE)) {
			*ckEnable |= (1 << i);
		}

     /* To get the status of the Clock Supplied to TC2 */
      i++;
		if (_arm_idlect3 & CSL_FMKT(CLKRST_ARM_IDLECT3_EN_TC2_CK, ACTIVE)) {
			*ckEnable |= (1 << i);
		}

     /* To get the status of the Clock Supplied to DSP */
      i++;
		if (hClkrst->regs->ARM_CKCTL & CSL_FMKT(CLKRST_ARM_CKCTL_EN_DSPCK, ACTIVE)) {
			*ckEnable |= (1 << i);
		}

     /* To get the status of the Clock Supplied to GPIO */
      i++;
		if (_arm_idlect2 & CSL_FMKT(CLKRST_ARM_IDLECT2_EN_GPIOCK, ACTIVE)) {
			*ckEnable |= (1 << i);
		}


}

static inline 
void CSL_clkrstGetResetStatus(
		CSL_ClkrstHandle        hClkrst,
		CSL_ClkrstStatus        *status
		)
{

	Uint32 _arm_sysst;

	_arm_sysst = hClkrst->regs->ARM_SYSST;

	hClkrst->regs->ARM_SYSST = (_arm_sysst & CSL_CLKRST_ARM_SYSST_CLOCK_SELECT_MASK);

	status->status    = _arm_sysst & 0x3F;
	status->dspStatus = (CSL_ClkrstDspStatus)CSL_FEXT(_arm_sysst, CLKRST_ARM_SYSST_IDLE_DSP);

}

static inline 
void CSL_clkrstCkEn(
		CSL_ClkrstHandle        hClkrst,
		CSL_ClkrstHwControlCmd  cmd,
		Uint16                  ckEnable
		)
{

	Uint32 i=0;
	Uint32 _arm_idlect2 = 0;
	Uint32 _arm_idlect3 = 0;
	Uint32 _arm_ckctl = 0;


     /* To Enable/Disable Clock Generated from DPLL1 Clock Output */
		if (ckEnable & (1 << i++)) 
        {
			_arm_idlect2 |= CSL_FMKT(CLKRST_ARM_IDLECT2_EN_CKOUT_ARM, ACTIVE);
		}

     /* To Enable/Disable the Clock Supplied to System DMA Controller */
		if (ckEnable & (1 << i++)) 
        {