📄 5912.h
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#define USB_DATA_DMA *( VUint16* )0xFFFB4048
#define USB_TXDMA0 *( VUint16* )0xFFFB4050
#define USB_TXDMA1 *( VUint16* )0xFFFB4054
#define USB_TXDMA2 *( VUint16* )0xFFFB4058
#define USB_RXDMA0 *( VUint16* )0xFFFB4060
#define USB_RXDMA1 *( VUint16* )0xFFFB4064
#define USB_RXDMA2 *( VUint16* )0xFFFB4068
#define USB_EP0 *( VUint16* )0xFFFB4080
#define USB_EP_RX_BASE ( VUint32* ) 0xFFFB4084
#define USB_EP1_RX *( VUint16* )0xFFFB4084
#define USB_EP2_RX *( VUint16* )0xFFFB4088
#define USB_EP3_RX *( VUint16* )0xFFFB408C
#define USB_EP4_RX *( VUint16* )0xFFFB4090
#define USB_EP5_RX *( VUint16* )0xFFFB4094
#define USB_EP6_RX *( VUint16* )0xFFFB4098
#define USB_EP7_RX *( VUint16* )0xFFFB409C
#define USB_EP8_RX *( VUint16* )0xFFFB40A0
#define USB_EP9_RX *( VUint16* )0xFFFB40A4
#define USB_EP10_RX *( VUint16* )0xFFFB40A8
#define USB_EP11_RX *( VUint16* )0xFFFB40AC
#define USB_EP12_RX *( VUint16* )0xFFFB40B0
#define USB_EP13_RX *( VUint16* )0xFFFB40B4
#define USB_EP14_RX *( VUint16* )0xFFFB40B8
#define USB_EP15_RX *( VUint16* )0xFFFB40BC
#define USB_EP_TX_BASE ( VUint32* ) 0xFFFB40C4
#define USB_EP1_TX *( VUint16* )0xFFFB40C4
#define USB_EP2_TX *( VUint16* )0xFFFB40C8
#define USB_EP3_TX *( VUint16* )0xFFFB40CC
#define USB_EP4_TX *( VUint16* )0xFFFB40D0
#define USB_EP5_TX *( VUint16* )0xFFFB40D4
#define USB_EP6_TX *( VUint16* )0xFFFB40D8
#define USB_EP7_TX *( VUint16* )0xFFFB40DC
#define USB_EP8_TX *( VUint16* )0xFFFB40E0
#define USB_EP9_TX *( VUint16* )0xFFFB40E4
#define USB_EP10_TX *( VUint16* )0xFFFB40E8
#define USB_EP11_TX *( VUint16* )0xFFFB40EC
#define USB_EP12_TX *( VUint16* )0xFFFB40F0
#define USB_EP13_TX *( VUint16* )0xFFFB40F4
#define USB_EP14_TX *( VUint16* )0xFFFB40F8
#define USB_EP15_TX *( VUint16* )0xFFFB40FC
#define USB_EP_SIZE 15
/* Register Parameters for USB EP_NUM ( USB_EP_NUM_ ) */
#define USB_EP_NUM_SETUP_SEL 0x0040
#define USB_EP_NUM_EP_SEL 0x0020
#define USB_EP_NUM_EP_DIR 0x0010
/* Register Parameters for USB CTRL ( USB_CTRL_ ) */
#define USB_CTRL_CLR_HALT 0x0080
#define USB_CTRL_SET_HALT 0x0040
#define USB_CTRL_SET_FIFO_EN 0x0004
#define USB_CTRL_CLR_EP 0x0002
#define USB_CTRL_RESET_EP 0x0001
/* Register Parameters for USB STAT ( USB_STAT_ ) */
#define USB_STAT_FLG_EP_HALTED 0x0040 // Non-Isochronous
#define USB_STAT_FLG_STALL 0x0020
#define USB_STAT_FLG_NAK 0x0010
#define USB_STAT_FLG_ACK 0x0008
#define USB_STAT_FLG_FIFO_EN 0x0004
#define USB_STAT_FLG_NON_ISO_FIFO_EMPTY 0x0002
#define USB_STAT_FLG_NON_ISO_FIFO_FULL 0x0001
/* Register Parameters for USB SYSCON2 ( USB_SYSCON2_ ) */
#define USB_SYSCON2_RMT_WKP 0x0040 // Remote Wakeup
#define USB_SYSCON2_STALL_CMD 0x0020 // Stall Command
#define USB_SYSCON2_DEV_CFG 0x0008 // Device Config
#define USB_SYSCON2_CLR_CFG 0x0004 // Clear Config
/* Register Parameters for USB IRQ_SRC ( USB_DEVSTAT_ ) */
#define USB_DEVSTAT_R_WK_OK 0x0040
#define USB_DEVSTAT_USB_RESET 0x0020
#define USB_DEVSTAT_SUS 0x0010
#define USB_DEVSTAT_CFG 0x0008
#define USB_DEVSTAT_ADD 0x0004
#define USB_DEVSTAT_DEF 0x0002
#define USB_DEVSTAT_ATT 0x0001
/* Register Parameters for USB IRQ_SRC ( USB_IRQ_SRC_ ) */
#define USB_IRQ_SRC_TXN_DONE 0x0400
#define USB_IRQ_SRC_RXN_CNT 0x0200
#define USB_IRQ_SRC_RXN_EOT 0x0100
#define USB_IRQ_SRC_SOF 0x0080
#define USB_IRQ_SRC_EPN_RX 0x0020
#define USB_IRQ_SRC_EPN_TX 0x0010
#define USB_IRQ_SRC_DS_CHG 0x0008
#define USB_IRQ_SRC_SETUP 0x0004
#define USB_IRQ_SRC_EP0_RX 0x0002
#define USB_IRQ_SRC_EP0_TX 0x0001
/* ------------------------------------------------------------------------ *
* Control Registers for: USB On-The-Go Module ( OTG_ ) *
* ------------------------------------------------------------------------ */
#define OTG_REV *( VUint32* )0xFFFB0400
#define OTG_SYSCON_1 *( VUint32* )0xFFFB0404
#define OTG_SYSCON_2 *( VUint32* )0xFFFB0408
#define OTG_CTRL *( VUint32* )0xFFFB040C
#define OTG_IRQ_EN *( VUint32* )0xFFFB0410
#define OTG_IRQ_SRC *( VUint32* )0xFFFB0414
#define OTG_OUTCTRL *( VUint32* )0xFFFB0418
#define OTG_TEST *( VUint32* )0xFFFB0420
#define OTG_VC *( VUint32* )0xFFFB04FC
/* ------------------------------------------------------------------------ *
* Control Registers for: DSP MCBSP1 ( DSP_MCBSP1_ ) *
* ------------------------------------------------------------------------ */
#define DSP_MCBSP1_DRR2 *( VUint16* )0xE1011800
#define DSP_MCBSP1_DRR1 *( VUint16* )0xE1011802
#define DSP_MCBSP1_DXR2 *( VUint16* )0xE1011804
#define DSP_MCBSP1_DXR1 *( VUint16* )0xE1011806
#define DSP_MCBSP1_SPCR2 *( VUint16* )0xE1011808
#define DSP_MCBSP1_SPCR1 *( VUint16* )0xE101180A
#define DSP_MCBSP1_RCR2 *( VUint16* )0xE101180C
#define DSP_MCBSP1_RCR1 *( VUint16* )0xE101180E
#define DSP_MCBSP1_XCR2 *( VUint16* )0xE1011810
#define DSP_MCBSP1_XCR1 *( VUint16* )0xE1011812
#define DSP_MCBSP1_SRGR2 *( VUint16* )0xE1011814
#define DSP_MCBSP1_SRGR1 *( VUint16* )0xE1011816
#define DSP_MCBSP1_MCR2 *( VUint16* )0xE1011818
#define DSP_MCBSP1_MCR1 *( VUint16* )0xE101181A
#define DSP_MCBSP1_RCERA *( VUint16* )0xE101181C
#define DSP_MCBSP1_RCERB *( VUint16* )0xE101181E
#define DSP_MCBSP1_XCERA *( VUint16* )0xE1011820
#define DSP_MCBSP1_XCERB *( VUint16* )0xE1011822
#define DSP_MCBSP1_PCR0 *( VUint16* )0xE1011824
#define DSP_MCBSP1_RCERC *( VUint16* )0xE1011826
#define DSP_MCBSP1_RCERD *( VUint16* )0xE1011828
#define DSP_MCBSP1_XCERC *( VUint16* )0xE101182A
#define DSP_MCBSP1_XCERD *( VUint16* )0xE101182C
#define DSP_MCBSP1_RCERE *( VUint16* )0xE101182E
#define DSP_MCBSP1_RCERF *( VUint16* )0xE1011830
#define DSP_MCBSP1_XCERE *( VUint16* )0xE1011832
#define DSP_MCBSP1_XCERF *( VUint16* )0xE1011834
#define DSP_MCBSP1_RCERG *( VUint16* )0xE1011836
#define DSP_MCBSP1_RCERH *( VUint16* )0xE1011838
#define DSP_MCBSP1_XCERG *( VUint16* )0xE101183A
#define DSP_MCBSP1_XCERH *( VUint16* )0xE101183C
/* ------------------------------------------------------------------------ *
* Control Registers for: DSP MCBSP2 ( DSP_MCBSP2_ ) *
* ------------------------------------------------------------------------ */
#define ARM_MCBSP2_DRR2 *( VUint16* )0xFFFB1000
#define ARM_MCBSP2_DRR1 *( VUint16* )0xFFFB1002
#define ARM_MCBSP2_DXR2 *( VUint16* )0xFFFB1004
#define ARM_MCBSP2_DXR1 *( VUint16* )0xFFFB1006
#define ARM_MCBSP2_SPCR2 *( VUint16* )0xFFFB1008
#define ARM_MCBSP2_SPCR1 *( VUint16* )0xFFFB100A
#define ARM_MCBSP2_RCR2 *( VUint16* )0xFFFB100C
#define ARM_MCBSP2_RCR1 *( VUint16* )0xFFFB100E
#define ARM_MCBSP2_XCR2 *( VUint16* )0xFFFB1010
#define ARM_MCBSP2_XCR1 *( VUint16* )0xFFFB1012
#define ARM_MCBSP2_SRGR2 *( VUint16* )0xFFFB1014
#define ARM_MCBSP2_SRGR1 *( VUint16* )0xFFFB1016
#define ARM_MCBSP2_MCR2 *( VUint16* )0xFFFB1018
#define ARM_MCBSP2_MCR1 *( VUint16* )0xFFFB101A
#define ARM_MCBSP2_RCERA *( VUint16* )0xFFFB101C
#define ARM_MCBSP2_RCERB *( VUint16* )0xFFFB101E
#define ARM_MCBSP2_XCERA *( VUint16* )0xFFFB1020
#define ARM_MCBSP2_XCERB *( VUint16* )0xFFFB1022
#define ARM_MCBSP2_PCR0 *( VUint16* )0xFFFB1024
#define ARM_MCBSP2_RCERC *( VUint16* )0xFFFB1026
#define ARM_MCBSP2_RCERD *( VUint16* )0xFFFB1028
#define ARM_MCBSP2_XCERC *( VUint16* )0xFFFB102A
#define ARM_MCBSP2_XCERD *( VUint16* )0xFFFB102C
#define ARM_MCBSP2_RCERE *( VUint16* )0xFFFB102E
#define ARM_MCBSP2_RCERF *( VUint16* )0xFFFB1030
#define ARM_MCBSP2_XCERE *( VUint16* )0xFFFB1032
#define ARM_MCBSP2_XCERF *( VUint16* )0xFFFB1034
#define ARM_MCBSP2_RCERG *( VUint16* )0xFFFB1036
#define ARM_MCBSP2_RCERH *( VUint16* )0xFFFB1038
#define ARM_MCBSP2_XCERG *( VUint16* )0xFFFB103A
#define ARM_MCBSP2_XCERH *( VUint16* )0xFFFB103C
/* ------------------------------------------------------------------------ *
* Control Registers for: DSP MCBSP3 ( DSP_MCBSP3_ ) *
* ------------------------------------------------------------------------ */
#define DSP_MCBSP3_DRR2 *( VUint16* )0xE1017000
#define DSP_MCBSP3_DRR1 *( VUint16* )0xE1017002
#define DSP_MCBSP3_DXR2 *( VUint16* )0xE1017004
#define DSP_MCBSP3_DXR1 *( VUint16* )0xE1017006
#define DSP_MCBSP3_SPCR2 *( VUint16* )0xE1017008
#define DSP_MCBSP3_SPCR1 *( VUint16* )0xE101700A
#define DSP_MCBSP3_RCR2 *( VUint16* )0xE101700C
#define DSP_MCBSP3_RCR1 *( VUint16* )0xE101700E
#define DSP_MCBSP3_XCR2 *( VUint16* )0xE1017010
#define DSP_MCBSP3_XCR1 *( VUint16* )0xE1017012
#define DSP_MCBSP3_SRGR2 *( VUint16* )0xE1017014
#define DSP_MCBSP3_SRGR1 *( VUint16* )0xE1017016
#define DSP_MCBSP3_MCR2 *( VUint16* )0xE1017018
#define DSP_MCBSP3_MCR1 *( VUint16* )0xE101701A
#define DSP_MCBSP3_RCERA *( VUint16* )0xE101701C
#define DSP_MCBSP3_RCERB *( VUint16* )0xE101701E
#define DSP_MCBSP3_XCERA *( VUint16* )0xE1017020
#define DSP_MCBSP3_XCERB *( VUint16* )0xE1017022
#define DSP_MCBSP3_PCR0 *( VUint16* )0xE1017024
#define DSP_MCBSP3_RCERC *( VUint16* )0xE1017026
#define DSP_MCBSP3_RCERD *( VUint16* )0xE1017028
#define DSP_MCBSP3_XCERC *( VUint16* )0xE101702A
#define DSP_MCBSP3_XCERD *( VUint16* )0xE101702C
#define DSP_MCBSP3_RCERE *( VUint16* )0xE101702E
#define DSP_MCBSP3_RCERF *( VUint16* )0xE1017030
#define DSP_MCBSP3_XCERE *( VUint16* )0xE1017032
#define DSP_MCBSP3_XCERF *( VUint16* )0xE1017034
#define DSP_MCBSP3_RCERG *( VUint16* )0xE1017036
#define DSP_MCBSP3_RCERH *( VUint16* )0xE1017038
#define DSP_MCBSP3_XCERG *( VUint16* )0xE101703A
#define DSP_MCBSP3_XCERH *( VUint16* )0xE101703C
/* Register Parameters for MCBSP PCR0 ( MCBSP_PCR0_ ) */
#define MCBSP_PCR0_IDLE_EN 0x4000
#define MCBSP_PCR0_XIOEN 0x2000
#define MCBSP_PCR0_RIOEN 0x1000
#define MCBSP_PCR0_FSXM 0x0800
#define MCBSP_PCR0_FSRM 0x0400
#define MCBSP_PCR0_CLKXM 0x0200
#define MCBSP_PCR0_CLKRM 0x0100
#define MCBSP_PCR0_SCLKME 0x0080
#define MCBSP_PCR0_CLKS_STAT 0x0040
#define MCBSP_PCR0_DX_STAT 0x0020
#define MCBSP_PCR0_DR_STAT 0x0010
#define MCBSP_PCR0_FSXP 0x0008
#define MCBSP_PCR0_FSRP 0x0004
#define MCBSP_PCR0_CLKXP 0x0002
#define MCBSP_PCR0_CLKRP 0x0001
/* Register Parameters for MCBSP RCR2 ( MCBSP_RCR2_ ) */
#define MCBSP_RCR2_RPHASE 0x8000
#define MCBSP_RCR2_RFIG 0x0004
/* Register Parameters for MCBSP XCR2 ( MCBSP_XCR2_ ) */
#define MCBSP_XCR2_XPHASE 0x8000
#define MCBSP_XCR2_XFIG 0x0004
/* Register Parameters for MCBSP SPCR1 ( MCBSP_SPCR1_ ) */
#define MCBSP_SPCR1_DLB 0x8000
#define MCBSP_SPCR1_DXENA 0x0020
#define MCBSP_SPCR1_ABIS 0x0010
#define MCBSP_SPCR1_RSYNCERR 0x0008
#define MCBSP_SPCR1_RFULL 0x0004
#define MCBSP_SPCR1_RRDY 0x0002
#define MCBSP_SPCR1_RRST 0x0001
#define MCBSP_SPCR1_RRST 0x0001
/* Register Parameters for MCBSP SPCR2 ( MCBSP_SPCR2_ ) */
#define MCBSP_SPCR2_FREE 0x0200
#define MCBSP_SPCR2_SOFT 0x0100
#define MCBSP_SPCR2_FRST 0x0080
#define MCBSP_SPCR2_GRST 0x0040
#define MCBSP_SPCR2_XSYNCERR 0x0008
#define MCBSP_SPCR2_XEMPTY 0x0004
#define MCBSP_SPCR2_XRDY 0x0002
#define MCBSP_SPCR2_XRST 0x0001
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