📄 5912.h
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* Control Registers for: UART2 TIPB Switch Registers ( UART2_ ) *
* ------------------------------------------------------------------------ */
#define UART2_BASE_ADDR ( VUint32* )0xFFFB0800
/* ------------------------------------------------------------------------ *
* Control Registers for: UART3 TIPB Switch Registers ( UART3_ ) *
* ------------------------------------------------------------------------ */
#define UART3_BASE_ADDR ( VUint32* )0xFFFB9800
/* ------------------------------------------------------------------------ *
* Control Registers for: UART Registers minus Base Address ( UART_ ) *
* These Registers are available with "LCR[bit 7] = 0" *
* ------------------------------------------------------------------------ */
#define UART_RHR 0x00 // Read only
#define UART_THR 0x00 // Write only
#define UART_IER 0x04 // To Access: EFR[4]=1
#define UART_IIR 0x08 // Read only
#define UART_FCR 0x08 // Write only - To Access: EFR[4]=1
#define UART_LCR 0x0C
#define UART_MCR 0x10 // To Access: EFR[4]=1
#define UART_LSR 0x14 // Read only
#define UART_MSR 0x18 // Read only
#define UART_TCR 0x18 // To Access: EFR[4]=1 & MCR[6]=1
#define UART_TLR 0x1C // To Access: EFR[4]=1 & MCR[6]=1
#define UART_SPR 0x1C
#define UART_MDR1 0x20
#define UART_MDR2 0x24
#define UART_SFLSR 0x28 // Read only
#define UART_TXFLL 0x28 // Write only
#define UART_RESUME 0x2C // Read only
#define UART_TXFLH 0x2C // Write only
#define UART_SFREGL 0x30 // Read only
#define UART_RXFLL 0x30 // Write only
#define UART_SFREGH 0x34 // Read only
#define UART_RXFLH 0x34 // Write only
#define UART_BLR 0x38
#define UART_ACREG 0x3C
#define UART_SCR 0x40
#define UART_SSR 0x44 // Read only
#define UART_EBLR 0x48
#define UART_MVR 0x50 // Read only
#define UART_SYSC 0x54
#define UART_SYSS 0x58
#define UART_WER 0x5C
/* ------------------------------------------------------------------------ *
* Control Registers for: UART Registers minus Base Address ( UART_ ) *
* These Registers are available with "LCR[bit 7] = 1" *
* ------------------------------------------------------------------------ */
#define UART_MODE_LCR_80 0x1000
#define UART_DLL UART_MODE_LCR_80 + 0x00
#define UART_DLH UART_MODE_LCR_80 + 0x04
#define UART_UASR UART_MODE_LCR_80 + 0x38
/* ------------------------------------------------------------------------ *
* Control Registers for: UART Registers minus Base Address ( UART_ ) *
* These Registers are available with "LCR = 0xBF" *
* ------------------------------------------------------------------------ */
#define UART_MODE_LCR_BF 0x2000
#define UART_EFR UART_MODE_LCR_BF + 0x08
#define UART_XON1 UART_MODE_LCR_BF + 0x10
#define UART_XON2 UART_MODE_LCR_BF + 0x14
#define UART_XOFF1 UART_MODE_LCR_BF + 0x18
#define UART_XOFF2 UART_MODE_LCR_BF + 0x1C
/* ------------------------------------------------------------------------ *
* Register Parameters for UART_MDR1 ( UART_MDR1_ ) *
* ------------------------------------------------------------------------ */
#define UART_MDR1_FRAME_END_MODE 0x80
#define UART_MDR1_SIP_MODE 0x40
#define UART_MDR1_SCT 0x20
#define UART_MDR1_SET_TXIR 0x10
#define UART_MDR1_IR_SLEEP 0x08
/* ------------------------------------------------------------------------ *
* Register Parameters for UART_MDR1_MODE_SELECT ( UART_MDR1_MODE_SELECT_ )*
* ------------------------------------------------------------------------ */
#define UART_MDR1_MODE_SELECT_16X_MODE 0
#define UART_MDR1_MODE_SELECT_SIR_MODE 1
#define UART_MDR1_MODE_SELECT_16X_AUTO 2
#define UART_MDR1_MODE_SELECT_13X_MODE 3
#define UART_MDR1_MODE_SELECT_MIR_MODE 4
#define UART_MDR1_MODE_SELECT_FIR_MODE 5
#define UART_MDR1_MODE_SELECT_DISABLE 7
/* ------------------------------------------------------------------------ *
* Register Parameters for UART_LSR ( UART_LSR_ ) *
* ------------------------------------------------------------------------ */
#define UART_LSR_RX_FIFO_STS 0x80
#define UART_LSR_TX_SR_E 0x40
#define UART_LSR_TX_FIFO_E 0x20
#define UART_LSR_RX_BI 0x10
#define UART_LSR_RX_FE 0x08
#define UART_LSR_RX_PE 0x04
#define UART_LSR_RX_OE 0x02
#define UART_LSR_RX_FIFO_E 0x01
/* ------------------------------------------------------------------------ *
* Register Parameters for UART_SYSC ( UART_SYSC_ ) *
* ------------------------------------------------------------------------ */
#define UART_SYSC_IDLEMODE_SMART_IDLE 0x10
#define UART_SYSC_IDLEMODE_NO_IDLE 0x08
#define UART_SYSC_IDLEMODE_FORCE_IDLE 0x00
#define UART_SYSC_ENAWAKEUP 0x04
#define UART_SYSC_SOFTRESET 0x02
#define UART_SYSC_AUTOIDLE 0x01
/* ------------------------------------------------------------------------ *
* Register Parameters for UART_SYSS ( UART_SYSS_ ) *
* ------------------------------------------------------------------------ */
#define UART_SYSS_RESETDONE 0x01
/* ------------------------------------------------------------------------ *
* Control Registers for: Interrupt Handler Level 1 ( INT1_ ) *
* ------------------------------------------------------------------------ */
#define INT1_ITR *( VUint32* ) 0xFFFECB00
#define INT1_MIR *( VUint32* ) 0xFFFECB04
#define INT1_SIR_IRQ_CODE *( VUint8* ) 0xFFFECB10
#define INT1_SIR_FIQ_CODE *( VUint8* ) 0xFFFECB14
#define INT1_CONTROL *( VUint8* ) 0xFFFECB18
#define INT1_SISR *( VUint32* ) 0xFFFECB9C
#define INT1_GMR *( VUint32* ) 0xFFFECBA0
#define INT1_ILR_BASE ( VUint32* ) 0xFFFECB1C // Priority Regs Base
#define INT1_SIZE 32
/* ------------------------------------------------------------------------ *
* Control Registers for: Interrupt Handler Level 2 ( INT2_ ) *
* ------------------------------------------------------------------------ */
#define INT2_ITR 0x00
#define INT2_MIR 0x04
#define INT2_SIR_IRQ_CODE *( Uint32* )0xFFFE0010
#define INT2_SIR_FIQ_CODE *( Uint32* )0xFFFE0014
#define INT2_CONTROL *( Uint32* )0xFFFE0018
#define INT2_SISR 0x9C
#define INT2_STATUS *( Uint32* )0xFFFE00A0
#define INT2_OCP_CFG *( Uint32* )0xFFFE00A4
#define INT2_INTH_REV *( Uint32* )0xFFFE00A8
#define INT2_ILR_BASE 0x1C // Priority Regs Base
#define INT2_SIZE 32
#define INT2_BANKS 4 // 4: 128 INTR
/* ------------------------------------------------------------------------ *
* Control Registers for: Inter-Integrated Circuit ( I2C_ ) *
* ------------------------------------------------------------------------ */
#define I2C_REV *( VUint16* )0xFFFB3800
#define I2C_IE *( VUint16* )0xFFFB3804
#define I2C_STAT *( VUint16* )0xFFFB3808
#define I2C_SYSS *( VUint16* )0xFFFB3810
#define I2C_BUF *( VUint16* )0xFFFB3814
#define I2C_CNT *( VUint16* )0xFFFB3818
#define I2C_DATA *( VUint16* )0xFFFB381C
#define I2C_SYSC *( VUint16* )0xFFFB3820
#define I2C_CON *( VUint16* )0xFFFB3824
#define I2C_OA *( VUint16* )0xFFFB3828
#define I2C_SA *( VUint16* )0xFFFB382C
#define I2C_PSC *( VUint16* )0xFFFB3830
#define I2C_SCLL *( VUint16* )0xFFFB3834
#define I2C_SCLH *( VUint16* )0xFFFB3838
#define I2C_SYSTEST *( VUint16* )0xFFFB383C
/* ------------------------------------------------------------------------ *
* Register Parameters for I2C_REV ( I2C_REV_ ) *
* ------------------------------------------------------------------------ */
#define I2C_REV_MASK 0x00FF // Bit Mask
/* ------------------------------------------------------------------------ *
* Register Parameters for I2C_IE ( I2C_IE_ ) *
* ------------------------------------------------------------------------ */
#define I2C_IE_GC_IE 0x0020 // General Call
#define I2C_IE_XRDY_IE 0x0010 // Trasmit Data Ready
#define I2C_IE_RRDY_IE 0x0008 // Receive Data Ready
#define I2C_IE_ARDY_IE 0x0004 // Register Access Ready
#define I2C_IE_NACK_IE 0x0002 // No Ack
#define I2C_IE_AL_IE 0x0001 // Arbitration Lost
/* ------------------------------------------------------------------------ *
* Register Parameters for I2C_STAT ( I2C_STAT_ ) *
* ------------------------------------------------------------------------ */
#define I2C_STAT_SBD 0x8000 // Single byte data
#define I2C_STAT_BB 0x1000 // Bus busy
#define I2C_STAT_ROVR 0x0800 // Receive overrun
#define I2C_STAT_XUDF 0x0400 // Transmit underflow
#define I2C_STAT_AAS 0x0200 // Address as slave
#define I2C_STAT_GC 0x0020 // General call
#define I2C_STAT_XRDY 0x0010 // Transmit data ready
#define I2C_STAT_RRDY 0x0008 // Receive data ready
#define I2C_STAT_ARDY 0x0004 // Register access ready
#define I2C_STAT_NACK 0x0002 // No acknowledgment
#define I2C_STAT_AL 0x0001 // Arbitration lost
/* ------------------------------------------------------------------------ *
* Register Parameters for I2C_SYSS ( I2C_SYSS_ ) *
* ------------------------------------------------------------------------ */
#define I2C_SYSS_RDONE 0x0001 // Reset Done
/* ------------------------------------------------------------------------ *
* Register Parameters for I2C_BUF ( I2C_BUF_ ) *
* ------------------------------------------------------------------------ */
#define I2C_BUF_RDMA_EN 0x8000 // Receive DMA enable
#define I2C_BUF_XDMA_EN 0x0080 // Transmit DMA enable
/* ------------------------------------------------------------------------ *
* Register Parameters for I2C_SYSC ( I2C_SYSC_ ) *
* ------------------------------------------------------------------------ */
#define I2C_SYSC_SRST 0x0002 // Soft Reset
/* ------------------------------------------------------------------------ *
* Register Parameters for I2C_CON ( I2C_CON_ ) *
* ------------------------------------------------------------------------ */
#define I2C_CON_I2C_EN 0x8000 // I2C module enable
#define I2C_CON_BE 0x4000 // Big endian mode
#define I2C_CON_STB 0x0800 // Start byte mode
#define I2C_CON_MST 0x0400 // Master/slave mode
#define I2C_CON_TRX 0x0200 // TX/RX mode
#define I2C_CON_TX 0x0200 // TX mode
#define I2C_CON_RX 0x0000 // RX mode
#define I2C_CON_XA 0x0100 // Expand address
#define I2C_CON_STP 0x0002 // Stop condition
#define I2C_CON_STT 0x0001 // Start condition
/* ------------------------------------------------------------------------ *
* Register Parameters for I2C_OA ( I2C_OA_ ) *
* ------------------------------------------------------------------------ */
#define I2C_OA_MASK 0x03FF // Bit Mask
/* ------------------------------------------------------------------------ *
* Register Parameters for I2C_SA ( I2C_SA_ ) *
* ------------------------------------------------------------------------ */
#define I2C_SA_MASK 0x03FF // Bit Mask
/* ------------------------------------------------------------------------ *
* Control Registers for: USB Function Module ( USB_ ) *
* ------------------------------------------------------------------------ */
#define USB_REV *( VUint16* )0xFFFB4000
#define USB_EP_NUM *( VUint16* )0xFFFB4004
#define USB_DATA_WORD *( VUint16* )0xFFFB4008
#define USB_DATA_BYTE *( VUint8* ) 0xFFFB4008
#define USB_CTRL *( VUint16* )0xFFFB400C
#define USB_STAT_FLG *( VUint16* )0xFFFB4010
#define USB_RXFSTAT *( VUint16* )0xFFFB4014
#define USB_SYSCON1 *( VUint16* )0xFFFB4018
#define USB_SYSCON2 *( VUint16* )0xFFFB401C
#define USB_DEVSTAT *( VUint16* )0xFFFB4020
#define USB_SOF *( VUint16* )0xFFFB4024
#define USB_IRQ_EN *( VUint16* )0xFFFB4028
#define USB_DMA_IRQ_EN *( VUint16* )0xFFFB402C
#define USB_IRQ_SRC *( VUint16* )0xFFFB4030
#define USB_EPN_STAT *( VUint16* )0xFFFB4034
#define USB_DMAN_STAT *( VUint16* )0xFFFB4038
#define USB_RXDMA_CFG *( VUint16* )0xFFFB4040
#define USB_TXDMA_CFG *( VUint16* )0xFFFB4044
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