📄 5912.h
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#define PMUX_FUNC_MUX_DSP_DMA_D *( VUint32* )0xFFFE10DC
#define PMUX_FUNC_MUX_ARM_DMA_A *( VUint32* )0xFFFE10EC
#define PMUX_FUNC_MUX_ARM_DMA_B *( VUint32* )0xFFFE10F0
#define PMUX_FUNC_MUX_ARM_DMA_C *( VUint32* )0xFFFE10F4
#define PMUX_FUNC_MUX_ARM_DMA_D *( VUint32* )0xFFFE10F8
#define PMUX_FUNC_MUX_ARM_DMA_E *( VUint32* )0xFFFE10FC
#define PMUX_FUNC_MUX_ARM_DMA_F *( VUint32* )0xFFFE1100
#define PMUX_FUNC_MUX_ARM_DMA_G *( VUint32* )0xFFFE1104
#define PMUX_MOD_CONF_CTRL_1 *( VUint32* )0xFFFE1110
#define PMUX_SECCTRL *( VUint32* )0xFFFE1120
#define PMUX_CONF_STATUS *( VUint32* )0xFFFE1130
#define PMUX_RESET_CONTROL *( VUint32* )0xFFFE1140
#define PMUX_CONF_1611_CTRL *( VUint32* )0xFFFE1150
/* ------------------------------------------------------------------------ *
* Control Registers for: Traffic Controller ( TC_ ) *
* ------------------------------------------------------------------------ */
/* OCP-T1/OCP-T2 Registers */
#define TC_OCPT1_PRIOR *( VUint32* )0xFFFECC00
#define TC_OCPT1_PTOR1 *( VUint32* )0xFFFECCA0
#define TC_OCPT1_PTOR2 *( VUint32* )0xFFFECCA4
#define TC_OCPT1_PTOR3 *( VUint32* )0xFFFECCA8
#define TC_OCPT1_ATOR *( VUint32* )0xFFFECCAC
#define TC_OCPT1_AADDR *( VUint32* )0xFFFECCB0
#define TC_OCPT1_ATYPER *( VUint32* )0xFFFECCB4
#define TC_OCPT_CONFIG_REG *( VUint32* )0xFFFECCB8
#define TC_OCPT2_PRIOR *( VUint32* )0xFFFECCD0
#define TC_OCPT2_PTOR1 *( VUint32* )0xFFFECCD4
#define TC_OCPT2_PTOR2 *( VUint32* )0xFFFECCD8
#define TC_OCPT2_PTOR3 *( VUint32* )0xFFFECCDC
#define TC_OCPT2_ATOR *( VUint32* )0xFFFECCE0
#define TC_OCPT2_AADDR *( VUint32* )0xFFFECCE4
#define TC_OCPT2_ATYPER *( VUint32* )0xFFFECCE8
/* EMIFS Registers */
#define TC_EMIFS_PRIOR *( VUint32* )0xFFFECC04
#define TC_EMIFS_CONFIG *( VUint32* )0xFFFECC0C
#define TC_EMIFS_CCS0 *( VUint32* )0xFFFECC10
#define TC_EMIFS_CCS1 *( VUint32* )0xFFFECC14
#define TC_EMIFS_CCS2 *( VUint32* )0xFFFECC18
#define TC_EMIFS_CCS3 *( VUint32* )0xFFFECC1C
#define TC_EMIFS_PTOR1 *( VUint32* )0xFFFECC28
#define TC_EMIFS_PTOR2 *( VUint32* )0xFFFECC2C
#define TC_EMIFS_PTOR3 *( VUint32* )0xFFFECC30
#define TC_EMIFS_DWS *( VUint32* )0xFFFECC40
#define TC_EMIFS_AADDR *( VUint32* )0xFFFECC44
#define TC_EMIFS_ATYPER *( VUint32* )0xFFFECC48
#define TC_EMIFS_ATOR *( VUint32* )0xFFFECC4C
#define TC_EMIFS_ACS0 *( VUint32* )0xFFFECC50
#define TC_EMIFS_ACS1 *( VUint32* )0xFFFECC54
#define TC_EMIFS_ACS2 *( VUint32* )0xFFFECC58
#define TC_EMIFS_ACS3 *( VUint32* )0xFFFECC5C
/* EMIFF Registers */
#define TC_EMIFF_PRIOR *( VUint32* )0xFFFECC08
#define TC_EMIFF_CONFIG *( VUint32* )0xFFFECC20
#define TC_EMIFF_MRS *( VUint32* )0xFFFECC24
#define TC_EMIFF_CONFIG2 *( VUint32* )0xFFFECC3C
#define TC_EMIFF_DLL_WRD_CTRL *( VUint32* )0xFFFECC64
#define TC_EMIFF_DLL_WRD_STAT *( VUint32* )0xFFFECC68
#define TC_EMIFF_MRS_NEW *( VUint32* )0xFFFECC70
#define TC_EMIFF_EMRS0 *( VUint32* )0xFFFECC74
#define TC_EMIFF_EMRS1 *( VUint32* )0xFFFECC78
#define TC_EMIFF_OP *( VUint32* )0xFFFECC80
#define TC_EMIFF_CMD *( VUint32* )0xFFFECC84
#define TC_EMIFF_PTOR1 *( VUint32* )0xFFFECC8C
#define TC_EMIFF_PTOR2 *( VUint32* )0xFFFECC90
#define TC_EMIFF_PTOR3 *( VUint32* )0xFFFECC94
#define TC_EMIFF_AADDR *( VUint32* )0xFFFECC98
#define TC_EMIFF_ATYPER *( VUint32* )0xFFFECC9C
#define TC_EMIFF_DLL_LRD_STAT *( VUint32* )0xFFFECCBC
#define TC_EMIFF_DLL_URD_CTRL *( VUint32* )0xFFFECCC0
#define TC_EMIFF_DLL_URD_STAT *( VUint32* )0xFFFECCC4
#define TC_EMIFF_EMRS2 *( VUint32* )0xFFFECCC8
#define TC_EMIFF_DLL_LRD_CTRL *( VUint32* )0xFFFECCCC
/* ------------------------------------------------------------------------ *
* Register Parameters for EMIFS_CCS ( TC_EMIFS_CCS_ ) *
* ------------------------------------------------------------------------ */
#define TC_EMIFS_CCS_PGWSTEN 0x80000000
#define TC_EMIFS_CCS_MAD 0x00400000
#define TC_EMIFS_CCS_BW 0x00100000
#define TC_EMIFS_CCS_RT 0x00000004
/* ------------------------------------------------------------------------ *
* Register Parameters for EMIFS_CONFIG ( TC_EMIFS_CONFIG_ ) *
* ------------------------------------------------------------------------ */
#define TC_EMIFS_CONFIG_FR 0x00000010
#define TC_EMIFS_CONFIG_PDE 0x00000008
#define TC_EMIFS_CONFIG_PWD_EN 0x00000004
#define TC_EMIFS_CONFIG_BM 0x00000002
#define TC_EMIFS_CONFIG_WP 0x00000001
/* ------------------------------------------------------------------------ *
* Register Parameters for EMIFF_CONFIG ( TC_EMIFF_CONFIG_ ) *
* ------------------------------------------------------------------------ */
#define TC_EMIFF_CONFIG_LG_SDRAM_0 0x00000000
#define TC_EMIFF_CONFIG_LG_SDRAM_1 0x10000000
#define TC_EMIFF_CONFIG_LG_SDRAM_2 0x20000000
#define TC_EMIFF_CONFIG_LG_SDRAM_3 0x30000000
#define TC_EMIFF_CONFIG_CLK 0x08000000
#define TC_EMIFF_CONFIG_PWD 0x04000000
#define TC_EMIFF_CONFIG_SDRAM_SDF0 0x00000000
#define TC_EMIFF_CONFIG_SDRAM_SDF1 0x01000000
#define TC_EMIFF_CONFIG_SDRAM_SDF2 0x02000000
#define TC_EMIFF_CONFIG_SDRAM_SDF3 0x03000000
#define TC_EMIFF_CONFIG_SLRF 0x00000001
/* ------------------------------------------------------------------------ *
* Register Parameters for EMIFF_OP ( TC_EMIFF_OP_ ) *
* ------------------------------------------------------------------------ */
#define TC_EMIFF_OP_MODE_LPLB 0x00000000
#define TC_EMIFF_OP_MODE_HPHB 0x00000004
#define TC_EMIFF_OP_MODE_POM0 0x00000008
#define TC_EMIFF_OP_SDRAM_TYPE_REG_SDR 0x00000000
#define TC_EMIFF_OP_SDRAM_TYPE_REG_DDR 0x00000001
#define TC_EMIFF_OP_SDRAM_TYPE_LOW_POW_SDR 0x00000002
#define TC_EMIFF_OP_SDRAM_TYPE_MOBILE_DDR 0x00000003
/* ------------------------------------------------------------------------ *
* Register Parameters for EMIFF_CMD ( TC_EMIFF_CMD_ ) *
* ------------------------------------------------------------------------ */
#define TC_EMIFF_CMD_NOP 0x00000000
#define TC_EMIFF_CMD_PRECHARGE 0x00000001
#define TC_EMIFF_CMD_AUTOREFRESH 0x00000002
#define TC_EMIFF_CMD_ENTER_DEEP_SLEEP 0x00000003
#define TC_EMIFF_CMD_EXIT_DEEP_SLEEP 0x00000004
#define TC_EMIFF_CMD_SET_CKE_HIGH 0x00000007
#define TC_EMIFF_CMD_SET_CKE_LOW 0x00000008
/* ------------------------------------------------------------------------ *
* Control Registers for: MPU Interface ( MPUI_ ) *
* ------------------------------------------------------------------------ */
#define MPUI_CTRL_REG *( VUint32* )0xFFFEC900
#define MPUI_DEBUG_ADDR *( VUint32* )0xFFFEC904
#define MPUI_DEBUG_DATA *( VUint32* )0xFFFEC908
#define MPUI_DEBUG_FLAG *( VUint32* )0xFFFEC90C
#define MPUI_STATUS_REG *( VUint32* )0xFFFEC910
#define MPUI_DSP_STATUS_REG *( VUint32* )0xFFFEC914
#define MPUI_DSP_BOOT_CONFIG *( VUint32* )0xFFFEC918
#define MPUI_DSP_MPUI_CONFIG *( VUint32* )0xFFFEC91C
/* ------------------------------------------------------------------------ *
* Control Registers for: Arm Watchdog Timer ( WDT_ ) *
* ------------------------------------------------------------------------ */
#define WDT_WIDR *( VUint32* )0xFFFEB000
#define WDT_WD_SYSCONFIG *( VUint32* )0xFFFEB010
#define WDT_WD_SYSSTATUS *( VUint32* )0xFFFEB014
#define WDT_WCLR *( VUint32* )0xFFFEB024
#define WDT_WCRR *( VUint32* )0xFFFEB028
#define WDT_WLDR *( VUint32* )0xFFFEB02C
#define WDT_WTGR *( VUint32* )0xFFFEB030
#define WDT_WWPS *( VUint32* )0xFFFEB034
#define WDT_WSPR *( VUint32* )0xFFFEB048
/* ------------------------------------------------------------------------ *
* Register Parameters for WDT_WWPS ( WDT_WWPS_ ) *
* ------------------------------------------------------------------------ */
#define WDT_WWPS_W_PEND_WSPR 0x00000010
#define WDT_WWPS_W_PEND_WTGR 0x00000008
#define WDT_WWPS_W_PEND_WLDR 0x00000004
#define WDT_WWPS_W_PEND_WCRR 0x00000002
#define WDT_WWPS_W_PEND_WCLR 0x00000001
/* ------------------------------------------------------------------------ *
* Control Registers for: Arm Watchdog Timer ( WDT_ ) *
* ------------------------------------------------------------------------ */
#define WDT_CNTL_TIMER *( VUint16* )0xFFFEC800
#define WDT_LOAD_TIM *( VUint16* )0xFFFEC804
#define WDT_READ_TIM *( VUint16* )0xFFFEC804
#define WDT_TIMER_MODE *( VUint16* )0xFFFEC808
/* ------------------------------------------------------------------------ *
* Control Registers for: DSP Watchdog Timer ( DSP_WDT_ ) *
* ------------------------------------------------------------------------ */
#define DSP_WDT_CNTL_TIMER *( VUint16* )0xE1006800
#define DSP_WDT_LOAD_TIM *( VUint16* )0xE1006804
#define DSP_WDT_READ_TIM *( VUint16* )0xE1006804
#define DSP_WDT_TIMER_MODE *( VUint16* )0xE1006808
/* ------------------------------------------------------------------------ *
* Control Registers for: Arm 32kHz Timer ( TIM32K_ ) *
* ------------------------------------------------------------------------ */
#define TIM32K_CR *( VUint32* )0xFFFB9008
#define TIM32K_TVR *( VUint32* )0xFFFB9000
#define TIM32K_TCR *( VUint32* )0xFFFB9004
/* ------------------------------------------------------------------------ *
* Control Registers for: Arm Timer1 ( TIMER1_ ) *
* ------------------------------------------------------------------------ */
#define TIMER1_CNTL_TIMER *( VUint32* )0xFFFEC500
#define TIMER1_LOAD_TIM *( VUint32* )0xFFFEC504
#define TIMER1_READ_TIM *( VUint32* )0xFFFEC508
/* ------------------------------------------------------------------------ *
* Control Registers for: Arm Timer2 ( TIMER2_ ) *
* ------------------------------------------------------------------------ */
#define TIMER2_CNTL_TIMER *( VUint32* )0xFFFEC600
#define TIMER2_LOAD_TIM *( VUint32* )0xFFFEC604
#define TIMER2_READ_TIM *( VUint32* )0xFFFEC608
/* ------------------------------------------------------------------------ *
* Control Registers for: Arm Timer3 ( TIMER3_ ) *
* ------------------------------------------------------------------------ */
#define TIMER3_CNTL_TIMER *( VUint32* )0xFFFEC700
#define TIMER3_LOAD_TIM *( VUint32* )0xFFFEC704
#define TIMER3_READ_TIM *( VUint32* )0xFFFEC708
/* ------------------------------------------------------------------------ *
* Control Registers for: ARM Public TIPB Registers ( PUBB_ ) *
* ------------------------------------------------------------------------ */
#define PUBB_TIPB_CNTL *( VUint16* )0xFFFED300
#define PUBB_TIPB_BUS_ALLOC *( VUint16* )0xFFFED304
#define PUBB_MPU_TIPB_CNTL *( VUint16* )0xFFFED308
#define PUBB_ENHANCED_TIPB_CNTL *( VUint16* )0xFFFED30C
#define PUBB_ADDRESS_DBG *( VUint16* )0xFFFED310
#define PUBB_DATA_DEBUG_LOW *( VUint16* )0xFFFED314
#define PUBB_DATA_DEBUG_HIGH *( VUint16* )0xFFFED318
#define PUBB_DEBUG_CNTR_SIG *( VUint16* )0xFFFED31C
/* ------------------------------------------------------------------------ *
* Control Registers for: ARM Private TIPB Registers ( PRIB_ ) *
* ------------------------------------------------------------------------ */
#define PRIB_TIPB_CNTL *( VUint16* )0xFFFECA00
#define PRIB_TIPB_BUS_ALLOC *( VUint16* )0xFFFECA04
#define PRIB_MPU_TIPB_CNTL *( VUint16* )0xFFFECA08
#define PRIB_ENHANCED_TIPB_CNTL *( VUint16* )0xFFFECA0C
#define PRIB_ADDRESS_DBG *( VUint16* )0xFFFECA10
#define PRIB_DATA_DEBUG_LOW *( VUint16* )0xFFFECA14
#define PRIB_DATA_DEBUG_HIGH *( VUint16* )0xFFFECA18
#define PRIB_DEBUG_CNTR_SIG *( VUint16* )0xFFFECA1C
/* ------------------------------------------------------------------------ *
* Control Registers for: UART1 TIPB Switch Registers ( UART1_ ) *
* ------------------------------------------------------------------------ */
#define UART1_BASE_ADDR ( VUint32* )0xFFFB0000
/* ------------------------------------------------------------------------ *
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