5912.h

dsp在音频处理中的运用

/*
 *  Copyright 2004 by Spectrum Digital Incorporated.
 *  All rights reserved. Property of Spectrum Digital Incorporated.
 */

/*
 *  ======== 5912.h ========
 *  Registers, Register Fields, and Memory Mapping for OSK5912
 */


/* ======================================================================== *
 *  Memory Mapping                                                          *
 * ======================================================================== */
/* ------------------------------------------------------------------------ *
 *  SDRAM Parameters                                                        *
 * ------------------------------------------------------------------------ */
#define OSK5912_SDRAM_BASE_ADDR     0x10000000
#define OSK5912_SDRAM_SIZE          0x02000000 // 64 Mbytes

/* ------------------------------------------------------------------------ *
 *  SRAM Parameters                                                         *
 * ------------------------------------------------------------------------ */
#define OSK5912_SRAM_BASE_ADDR      0x20000000
#define OSK5912_SRAM_SIZE           0x0003E800 // 250 Kbytes





/* ======================================================================== *
 *  Peripheral Registers                                                    *
 * ======================================================================== */
/* ------------------------------------------------------------------------ *
 *  Control Registers for: ARM CLOCK ( CLK_ )                               *
 * ------------------------------------------------------------------------ */
#define CLK_ARM_CKCTL               *( VUint32* )0xFFFECE00
#define CLK_ARM_IDLECT1             *( VUint32* )0xFFFECE04
#define CLK_ARM_IDLECT2             *( VUint32* )0xFFFECE08
#define CLK_ARM_EWUPCT              *( VUint32* )0xFFFECE0C
#define CLK_ARM_RSTCT1              *( VUint32* )0xFFFECE10
#define CLK_ARM_RSTCT2              *( VUint32* )0xFFFECE14
#define CLK_ARM_SYSST               *( VUint32* )0xFFFECE18
#define CLK_ARM_CKOUT1              *( VUint32* )0xFFFECE1C
#define CLK_ARM_CKOUT2              *( VUint32* )0xFFFECE20
#define CLK_ARM_IDLECT3             *( VUint32* )0xFFFECE24

/* ------------------------------------------------------------------------ *
 *  Register Parameters for ARM_CKCTL ( CLK_ARM_CKCTL_ )                    *
 * ------------------------------------------------------------------------ */
#define CLK_ARM_CKCTL_ARM_INTHCK_SEL        0x00004000
#define CLK_ARM_CKCTL_EN_DSPCK              0x00002000
#define CLK_ARM_CKCTL_ARM_TIMXO             0x00001000

/* ------------------------------------------------------------------------ *
 *  Register Parameters for ARM_IDLECT1 ( CLK_ARM_IDLECT1_ )                *
 * ------------------------------------------------------------------------ */
#define CLK_ARM_IDLECT1_IDL_CLKOUT_ARM      0x00001000
#define CLK_ARM_IDLECT1_WKUP_MODE           0x00000400
#define CLK_ARM_IDLECT1_IDLTIM_ARM          0x00000200
#define CLK_ARM_IDLECT1_IDLAPI_ARM          0x00000100
#define CLK_ARM_IDLECT1_IDLDPLL_ARM         0x00000080
#define CLK_ARM_IDLECT1_IDLIF_ARM           0x00000040
#define CLK_ARM_IDLECT1_IDLPER_ARM          0x00000004
#define CLK_ARM_IDLECT1_IDLXORP_ARM         0x00000002
#define CLK_ARM_IDLECT1_IDLWDT_ARM          0x00000001

/* ------------------------------------------------------------------------ *
 *  Register Parameters for ARM_IDLECT2 ( CLK_ARM_IDLECT2_ )                *
 *      Used for enabling Clks sent to various components & peripherals     *
 * ------------------------------------------------------------------------ */
#define CLK_ARM_IDLECT2_EN_CKOUT_ARM        0x00000800
#define CLK_ARM_IDLECT2_DMACK_REQ           0x00000100
#define CLK_ARM_IDLECT2_EN_TIMCK            0x00000080
#define CLK_ARM_IDLECT2_EN_APICK            0x00000040
#define CLK_ARM_IDLECT2_EN_LBCK             0x00000010
#define CLK_ARM_IDLECT2_EN_LCDCK            0x00000008
#define CLK_ARM_IDLECT2_EN_PERCK            0x00000004
#define CLK_ARM_IDLECT2_EN_XORPCK           0x00000002
#define CLK_ARM_IDLECT2_EN_WDTCK            0x00000001

/* ------------------------------------------------------------------------ *
 *  Register Parameters for ARM_RSTCT1 ( CLK_ARM_RSTCT1_ )                  *
 *      Used for Reseting the MPU/DSP                                       *
 * ------------------------------------------------------------------------ */
#define CLK_ARM_RSTCT1_SW_RST               0x00000008
#define CLK_ARM_RSTCT1_DSP_RST              0x00000004
#define CLK_ARM_RSTCT1_DSP_EN               0x00000002
#define CLK_ARM_RSTCT1_ARM_RST              0x00000001

/* ------------------------------------------------------------------------ *
 *  Register Parameters for ARM_RSTCT2 ( CLK_ARM_RSTCT2_ )                  *
 *      Used for Enabling Peripherals                                       *
 * ------------------------------------------------------------------------ */
#define CLK_ARM_RSTCT2_PER_EN               0x00000001

/* ------------------------------------------------------------------------ *
 *  Register Parameters for ARM_SYSST ( CLK_ARM_SYSST_ )                    *
 * ------------------------------------------------------------------------ */
#define CLK_ARM_SYSST_CLOCK_SELECT_FULL_SYNC    0x00000000
#define CLK_ARM_SYSST_CLOCK_SELECT_SYNC_SCAL    0x00001000
#define CLK_ARM_SYSST_CLOCK_SELECT_BYPASS_MODE  0x00002800
#define CLK_ARM_SYSST_CLOCK_SELECT_MIX_MODE_3   0x00003000
#define CLK_ARM_SYSST_CLOCK_SELECT_MIX_MODE_4   0x00003800
#define CLK_ARM_SYSST_IDLE_DSP              0x00000040
#define CLK_ARM_SYSST_POR                   0x00000020
#define CLK_ARM_SYSST_EXT_RST               0x00000010
#define CLK_ARM_SYSST_ARM_MCRST             0x00000008
#define CLK_ARM_SYSST_ARM_WDRST             0x00000004
#define CLK_ARM_SYSST_GLOB_SWRST            0x00000002
#define CLK_ARM_SYSST_DSP_WDRST             0x00000001

/* ------------------------------------------------------------------------ *
 *  Register Parameters for ARM_IDLECT3 ( CLK_ARM_IDLECT3_ )                *
 *      Used for enabling Clks sent to various components & peripherals     *
 * ------------------------------------------------------------------------ */
#define CLK_ARM_IDLECT3_IDLTC2_ARM          0x00000020
#define CLK_ARM_IDLECT3_EN_TC2_CK           0x00000010
#define CLK_ARM_IDLECT3_IDLTC1_ARM          0x00000008
#define CLK_ARM_IDLECT3_EN_TC1_CK           0x00000004
#define CLK_ARM_IDLECT3_IDLOCPI_ARM         0x00000002
#define CLK_ARM_IDLECT3_EN_OCPI_CK          0x00000001





/* ------------------------------------------------------------------------ *
 *  Control Registers for: DSP CLOCK ( CLK_ )                               *
 * ------------------------------------------------------------------------ */
#define CLK_DSP_CKCTL               *( VUint16* )0xE1008000
#define CLK_DSP_IDLECT1             *( VUint16* )0xE1008004
#define CLK_DSP_IDLECT2             *( VUint16* )0xE1008008
#define CLK_DSP_RSTCT2              *( VUint16* )0xE1008014
#define CLK_DSP_SYSST               *( VUint16* )0xE1008018

/* ------------------------------------------------------------------------ *
 *  Register Parameters for DSP_IDLECT1 ( CLK_DSP_IDLECT1_ )                *
 *      Idle Control on DSP                                                 *
 * ------------------------------------------------------------------------ */
#define CLK_DSP_IDLECT1_IDLTIM_DSP          0x0100
#define CLK_DSP_IDLECT1_IDLXORP_DSP         0x0002
#define CLK_DSP_IDLECT1_IDLWDT_DSP          0x0001

/* ------------------------------------------------------------------------ *
 *  Register Parameters for DSP_IDLECT2 ( CLK_DSP_IDLECT2_ )                *
 *      Idle Control on DSP                                                 *
 * ------------------------------------------------------------------------ */
#define CLK_DSP_IDLECT2_EN_TIMCK            0x0020
#define CLK_DSP_IDLECT2_EN_GPIOCK           0x0010
#define CLK_DSP_IDLECT2_EN_XORPCK           0x0002
#define CLK_DSP_IDLECT2_EN_WDTCK            0x0001

/* ------------------------------------------------------------------------ *
 *  Register Parameters for DSP_RSTCT2 ( CLK_DSP_RSTCT2_ )                  *
 *      Reset Control on DSP Peripherals                                    *
 * ------------------------------------------------------------------------ */
#define CLK_DSP_RSTCT2_WD_PER_EN             0x0002
#define CLK_DSP_RSTCT2_PER_EN                0x0001





/* ------------------------------------------------------------------------ *
 *  Control Register for: Digital Phase Lock Loop ( DPLL#_ )                *
 * ------------------------------------------------------------------------ */
#define DPLL1_CTL_REG               *( VUint32* )0xFFFECF00
#define DPLL2_CTL_REG               *( VUint32* )0xFFFED000

/* ------------------------------------------------------------------------ *
 *  Register Parameters for DPLL_CTL_REG ( DPLL_CTL_REG_ )                  *
 *      Reset Control on DSP Peripherals                                    *
 * ------------------------------------------------------------------------ */
#define DPLL1_CTL_REG_LS_DISABLE            0x8000
#define DPLL1_CTL_REG_IAI                   0x4000
#define DPLL1_CTL_REG_IOB                   0x2000
#define DPLL1_CTL_REG_TEST                  0x1000
#define DPLL1_CTL_REG_PLL_ENABLE            0x0010
#define DPLL1_CTL_REG_BREAKLN               0x0002
#define DPLL1_CTL_REG_LOCK                  0x0001





/* ------------------------------------------------------------------------ *
 *  Control Register for: ULPD power management ( ULPD_ )                   *
 * ------------------------------------------------------------------------ */
#define ULPD_COUNTER_32_LSB         *( VUint16* )0xFFFE0800
#define ULPD_COUNTER_32_MSB         *( VUint16* )0xFFFE0804
#define ULPD_COUNTER_HIGH_FREQ_LSB  *( VUint16* )0xFFFE0808
#define ULPD_COUNTER_HIGH_FREQ_MSB  *( VUint16* )0xFFFE080C
#define ULPD_GAUGING_CTRL           *( VUint16* )0xFFFE0810
#define ULPD_IT_STATUS              *( VUint16* )0xFFFE0814
#define ULPD_SETUP_ANALOG_CELL3_ULPD1   *( VUint16* )0xFFFE0824
#define ULPD_SETUP_ANALOG_CELL2_ULPD1   *( VUint16* )0xFFFE0828
#define ULPD_SETUP_ANALOG_CELL1_ULPD1   *( VUint16* )0xFFFE082C
#define ULPD_CLOCK_CTRL             *( VUint16* )0xFFFE0830
#define ULPD_SOFT_REQ               *( VUint16* )0xFFFE0834
#define ULPD_COUNTER_32_FIQ         *( VUint16* )0xFFFE0838
#define ULPD_STATUS_REQ             *( VUint16* )0xFFFE0840
#define ULPD_PLL_DIV                *( VUint16* )0xFFFE0844
#define ULPD_ULPD_PLL_CTRL_STATUS   *( VUint16* )0xFFFE084C
#define ULPD_POWER_CTRL             *( VUint16* )0xFFFE0850
#define ULPD_STATUS_REQ2            *( VUint16* )0xFFFE0854
#define ULPD_SLEEP_STATUS           *( VUint16* )0xFFFE0858
#define ULPD_SETUP_ANALOG_CELL4_ULPD1   *( VUint16* )0xFFFE085C
#define ULPD_SETUP_ANALOG_CELL5_ULPD1   *( VUint16* )0xFFFE0860
#define ULPD_SETUP_ANLOG_CELL6_ULPD1    *( VUint16* )0xFFFE0864
#define ULPD_SOFT_DISABLE_REQ       *( VUint16* )0xFFFE0868
#define ULPD_RESET_STATUS           *( VUint16* )0xFFFE086C
#define ULPD_REVISION_NUMBER        *( VUint16* )0xFFFE0870
#define ULPD_SDW_CLK_DIV_CTRL_SEL   *( VUint16* )0xFFFE0874
#define ULPD_COM_CLK_DIV_CTRL_SEL   *( VUint16* )0xFFFE0878
#define ULPD_CAM_CLK_CTRL           *( VUint16* )0xFFFE087C
#define ULPD_SOFT_REQ2              *( VUint16* )0xFFFE0880


/* ------------------------------------------------------------------------ *
 *  Control Registers for: OMAP1610 Configuration ( PMUX_ )                 *
 * ------------------------------------------------------------------------ */
#define PMUX_FUNC_MUX_CTRL_0        *( VUint32* )0xFFFE1000
#define PMUX_FUNC_MUX_CTRL_1        *( VUint32* )0xFFFE1004
#define PMUX_FUNC_MUX_CTRL_2        *( VUint32* )0xFFFE1008
#define PMUX_COMP_MODE_CTRL_0       *( VUint32* )0xFFFE100C
#define PMUX_FUNC_MUX_CTRL_3        *( VUint32* )0xFFFE1010
#define PMUX_FUNC_MUX_CTRL_4        *( VUint32* )0xFFFE1014
#define PMUX_FUNC_MUX_CTRL_5        *( VUint32* )0xFFFE1018
#define PMUX_FUNC_MUX_CTRL_6        *( VUint32* )0xFFFE101C
#define PMUX_FUNC_MUX_CTRL_7        *( VUint32* )0xFFFE1020
#define PMUX_FUNC_MUX_CTRL_8        *( VUint32* )0xFFFE1024
#define PMUX_FUNC_MUX_CTRL_9        *( VUint32* )0xFFFE1028
#define PMUX_FUNC_MUX_CTRL_A        *( VUint32* )0xFFFE102C
#define PMUX_FUNC_MUX_CTRL_B        *( VUint32* )0xFFFE1030
#define PMUX_FUNC_MUX_CTRL_C        *( VUint32* )0xFFFE1034
#define PMUX_FUNC_MUX_CTRL_D        *( VUint32* )0xFFFE1038
#define PMUX_PULL_DWN_CTRL_0        *( VUint32* )0xFFFE1040
#define PMUX_PULL_DWN_CTRL_1        *( VUint32* )0xFFFE1044
#define PMUX_PULL_DWN_CTRL_2        *( VUint32* )0xFFFE1048
#define PMUX_PULL_DWN_CTRL_3        *( VUint32* )0xFFFE104C
#define PMUX_GATE_INH_CTRL_0        *( VUint32* )0xFFFE1050
#define PMUX_CONF_REV               *( VUint32* )0xFFFE1058
#define PMUX_VOLTAGE_CTRL_0         *( VUint32* )0xFFFE1060
#define PMUX_USB_TRANSCEIVER_CTRL   *( VUint32* )0xFFFE1064
#define PMUX_LDO_PWRDN_CBTRK        *( VUint32* )0xFFFE1068
#define PMUX_TEST_DBG_CTRL_0        *( VUint32* )0xFFFE1070
#define PMUX_MOD_CONF_CTRL_0        *( VUint32* )0xFFFE1080
#define PMUX_FUNC_MUX_CTRL_E        *( VUint32* )0xFFFE1090
#define PMUX_FUNC_MUX_CTRL_F        *( VUint32* )0xFFFE1094
#define PMUX_FUNC_MUX_CTRL_10       *( VUint32* )0xFFFE1098
#define PMUX_FUNC_MUX_CTRL_11       *( VUint32* )0xFFFE109C
#define PMUX_FUNC_MUX_CTRL_12       *( VUint32* )0xFFFE10A0
#define PMUX_PULL_DWN_CTRL_4        *( VUint32* )0xFFFE10AC
#define PMUX_PU_PD_SEL_0            *( VUint32* )0xFFFE10B4
#define PMUX_PU_PD_SEL_1            *( VUint32* )0xFFFE10B8
#define PMUX_PU_PD_SEL_2            *( VUint32* )0xFFFE10BC
#define PMUX_PU_PD_SEL_3            *( VUint32* )0xFFFE10C0
#define PMUX_PU_PD_SEL_4            *( VUint32* )0xFFFE10C4
#define PMUX_FUNC_MUX_DSP_DMA_A     *( VUint32* )0xFFFE10D0
#define PMUX_FUNC_MUX_DSP_DMA_B     *( VUint32* )0xFFFE10D4
#define PMUX_FUNC_MUX_DSP_DMA_C     *( VUint32* )0xFFFE10D8