osk5912init.c

dsp在音频处理中的运用

/*#include <csl_clkrst.h>
#include <csl.h>
#include <csl_types.h>
#include <cslr.h>
#include <soc.h>
#include <tistdtypes.h>*/

#include <soc.h>

#include <csl_wdt.h>
#include <csl_dpll.h>
#include <csl_clkrst.h>
#include <Osk5912.h>
#include  <stdio.h>

/*#define WDT_WIDR                    *( VUint32* )0xFFFEB000
#define WDT_WD_SYSCONFIG            *( VUint32* )0xFFFEB010
#define WDT_WD_SYSSTATUS            *( VUint32* )0xFFFEB014
#define WDT_WCLR                    *( VUint32* )0xFFFEB024
#define WDT_WCRR                    *( VUint32* )0xFFFEB028
#define WDT_WLDR                    *( VUint32* )0xFFFEB02C
#define WDT_WTGR                    *( VUint32* )0xFFFEB030*/
//#define WDT_WWPS                    *( Uint32* )0xFFFEB034
//#define WDT_WSPR                    *( Uint32* )0xFFFEB048

#define WDT_WWPS_W_PEND_WSPR                0x00000010
#define WDT_WWPS_W_PEND_WTGR                0x00000008
#define WDT_WWPS_W_PEND_WLDR                0x00000004
#define WDT_WWPS_W_PEND_WCRR                0x00000002
#define WDT_WWPS_W_PEND_WCLR                0x00000001
/*#define CSL_CLKRST_HWSETUP_CLK_CLKSCHEME_DEFAULTS { \
	   CSL_CLKRST_CLKSCHEME_FULLSYNC,           \
	   {                                        \
		   0,                               \
		   0,                               \
		   0,                               \
		   0,                               \
		   0,                               \
		   0                                \
	   }                                        \
         }*/
CSL_DpllObj     dpllObj;
CSL_ClkrstObj     clkrstObj;
CSL_DpllHwSetup dpllsetup1 = CSL_DPLL_HWSETUP_DEFAULTS;
void  disable_watchdog();
void  setDpll(Uint16 freq);
void  clkrst_init();

void osk5912_init()
{  PMUX_VOLTAGE_CTRL_0 = 0x0FCD;
   /*PMUX_COMP_MODE_CTRL_0 = 0;
   PMUX_FUNC_MUX_CTRL_D&= 0xFFFFFFF8;
   PMUX_MOD_CONF_CTRL_1&=0xE7FFFFFF;
   PMUX_COMP_MODE_CTRL_0 = 0x0000EAEF;*/
   disable_watchdog();
   setDpll(192);
   PMUX_COMP_MODE_CTRL_0 = 0;
   PMUX_FUNC_MUX_CTRL_D=(PMUX_FUNC_MUX_CTRL_D&~0x7)|0;   //0xFFFFFFF8;
   //PMUX_MOD_CONF_CTRL_1=PMUX_MOD_CONF_CTRL_1&~0x18|0;   //0xE7FFFFFF;
   PMUX_COMP_MODE_CTRL_0=0x0000EAEF;
   clkrst_init();
}


void  disable_watchdog()
{   static CSL_WdtHandle hWdt;
    static CSL_WdtObj   wdtObj;
    CSL_Status          status;
    CSL_wdtInit(NULL);
    hWdt = CSL_wdtOpen (&wdtObj, CSL_WDT, NULL,&status);
    if ((hWdt == NULL) || (status != CSL_SOK)) {

        printf ("Watchdog timer module open failed\n");
    
        return;

    }
	CSL_wdtHwControl(hWdt,CSL_WDT_CMD_DISABLE,NULL);
	CSL_wdtClose(hWdt);
	WDT_WSPR = 0xAAAA;
    while ( WDT_WWPS & WDT_WWPS_W_PEND_WSPR );
    WDT_WSPR = 0x5555;
    while ( WDT_WWPS & WDT_WWPS_W_PEND_WSPR );
	
	return;
}


void setDpll(Uint16 freq)
{   CSL_DpllHandle  hDpll;
	//CSL_DpllObj     dpllObj;
	CSL_Status      status;
	Uint16	        i;
    CSL_DpllLock    response;
    
    //CSL_DpllHwSetup dpllsetup1 = CSL_DPLL_HWSETUP_DEFAULTS;//must put it outside the function,make it to a gloable variable
    dpllsetup1.pllMode =  CSL_DPLL_MODE_LOCK ;
    dpllsetup1.pllmult =  16;
    dpllsetup1.plldiv =   0;
    dpllsetup1.bypassdiv = 2;


    
	

    status= CSL_dpllInit(NULL);
    	/* Check whether the status returned is correct. If not return with error */
    	if(status != CSL_SOK)
                return ;

		/* Open the DPLL Handle */
        hDpll = CSL_dpllOpen(&dpllObj,CSL_DPLL_1,NULL,&status);

    	/* Check whether the status returned is correct. If not return with error */
    	if(status != CSL_SOK)
                return ;

		/* Perform the Setup. */
        CSL_dpllHwSetup(hDpll,&dpllsetup1);

		for(i=0;i<100;i++)
		{
		}  

        do{
			CSL_dpllGetHwStatus(hDpll, CSL_DPLL_QUERY_LOCK_STATUS, &response);
		}while(response != CSL_DPLL_LOCK_ON );


		/* Close the dpll HANDLE */
		if(CSL_dpllClose(hDpll) != CSL_SOK)
			return ;

		//return ;

}


void clkrst_init()
{  //Uint16 i,a=0;
   #define ENABLE(CLK) (CSL_CLKRST_MODULE_##CLK)
/*
 * *********************************************************************
 * To Enable the Desired Clock through CLKRST CSL
 * *********************************************************************
 */ Uint16            clkEn = 0;
	Uint16            mpuperEn=0;
    CSL_Status        status;
	
    //CSL_ClkrstObj     clkrstObj;
	CSL_ClkrstHandle  hClkrst = NULL;
	CSL_ClkrstHwSetup clkSetup;//= CSL_CLKRST_HWSETUP_DEFAULTS ;
    
	CSL_ClkrstHwSetupClk   setupclk;
	
	CSL_ClkrstHwSetupClkClkScheme clkSchemep;
	//clkSchemep=CSL_CLKRST_HWSETUP_CLK_CLKSCHEME_DEFAULTS;
    //setupclk.clkSchemePtr=&clkSchemep;
	//clkSetup.clkPtr=&setupclk;
	//CSL_ClkrstClkDiv     clkDiv;
	clkSchemep.clkScheme=CSL_CLKRST_CLKSCHEME_SYNCSCAL ;
    clkSchemep.clkDiv.tcDiv=2;
	clkSchemep.clkDiv.dspDiv=1;
	clkSchemep.clkDiv.mpuDiv=1;
	clkSchemep.clkDiv.perDiv=3;
	clkSchemep.clkDiv.lcdDiv=3;
	clkSchemep.clkDiv.dspmmuDiv=1;
    setupclk.clkSchemePtr=&clkSchemep;
	setupclk.clkSourcePtr=NULL;
    setupclk.mpuInthCkPtr=NULL;
    setupclk.clkIdleEntryPtr=NULL;
    setupclk.ckoutPtr=NULL;
    clkSetup.clkPtr=&setupclk;
	//clkSetup={&setupclk,NULL,NULL};
    clkSetup.pwrctlPtr=NULL;
	clkSetup.wkupModePtr=NULL;


    /* Pin Multiplexing 
    FUNC_MUX_CTRL_7 |= 0x3;
    FUNC_MUX_CTRL_7 |= 0x0010000;
    COMP_MODE_CTRL_0 = 0xEAEF;*/
    
/* ******************--- Clock Cofiguration---*******************/

	/* To Initialise Clkrst CSL */
	CSL_clkrstInit(NULL);

	/* To Open Clkrst CSL */
	hClkrst = CSL_clkrstOpen(&clkrstObj, CSL_CLKRST, NULL, &status );
	/*for(i=0;i<=20;i++)
	{a++;
	}
    a=a+1;
	a=a+2;*/
	/* To Setup the Clkrst CSL */
	CSL_clkrstHwSetup(hClkrst, &clkSetup );

	/* Variable to Enable the Desired Clock */
	clkEn = ENABLE(TIM) | ENABLE(XORP) ;

	/* To Enable the Clocks */
	CSL_clkrstHwControl (hClkrst, CSL_CLKRST_CMD_CLK_ENABLE, ((Uint16 *) &clkEn) );
    mpuperEn=CSL_CLKRST_ARM_RSTCT2_PER_EN_PER_ENABLED;
    CSL_clkrstHwControl (hClkrst, CSL_CLKRST_CMD_RESET_OUT, ((Uint16 *) &mpuperEn) );
    CSL_clkrstClose(hClkrst);
/* ******************---End of Clock Cofiguration---*******************/
}