bench.vcd

SPI 总线协议源码SPI 总线协议源码SPI 总线协议源码

$date
	Sat Aug 18 17:54:39 2007
$end
$version
	ModelSim Version 5.8c
$end
$timescale
	10ps
$end
$scope module tb_spi_top $end
$var parameter 5 ! SPI_RX_0 $end
$var parameter 5 " SPI_RX_1 $end
$var parameter 5 # SPI_RX_2 $end
$var parameter 5 $ SPI_RX_3 $end
$var parameter 5 % SPI_TX_0 $end
$var parameter 5 & SPI_TX_1 $end
$var parameter 5 ' SPI_TX_2 $end
$var parameter 5 ( SPI_TX_3 $end
$var parameter 5 ) SPI_CTRL $end
$var parameter 5 * SPI_DIVIDE $end
$var parameter 5 + SPI_SS $end
$var reg 1 , clk $end
$var reg 1 - rst $end
$var wire 1 . adr [31] $end
$var wire 1 / adr [30] $end
$var wire 1 0 adr [29] $end
$var wire 1 1 adr [28] $end
$var wire 1 2 adr [27] $end
$var wire 1 3 adr [26] $end
$var wire 1 4 adr [25] $end
$var wire 1 5 adr [24] $end
$var wire 1 6 adr [23] $end
$var wire 1 7 adr [22] $end
$var wire 1 8 adr [21] $end
$var wire 1 9 adr [20] $end
$var wire 1 : adr [19] $end
$var wire 1 ; adr [18] $end
$var wire 1 < adr [17] $end
$var wire 1 = adr [16] $end
$var wire 1 > adr [15] $end
$var wire 1 ? adr [14] $end
$var wire 1 @ adr [13] $end
$var wire 1 A adr [12] $end
$var wire 1 B adr [11] $end
$var wire 1 C adr [10] $end
$var wire 1 D adr [9] $end
$var wire 1 E adr [8] $end
$var wire 1 F adr [7] $end
$var wire 1 G adr [6] $end
$var wire 1 H adr [5] $end
$var wire 1 I adr [4] $end
$var wire 1 J adr [3] $end
$var wire 1 K adr [2] $end
$var wire 1 L adr [1] $end
$var wire 1 M adr [0] $end
$var wire 1 N dat_i [31] $end
$var wire 1 O dat_i [30] $end
$var wire 1 P dat_i [29] $end
$var wire 1 Q dat_i [28] $end
$var wire 1 R dat_i [27] $end
$var wire 1 S dat_i [26] $end
$var wire 1 T dat_i [25] $end
$var wire 1 U dat_i [24] $end
$var wire 1 V dat_i [23] $end
$var wire 1 W dat_i [22] $end
$var wire 1 X dat_i [21] $end
$var wire 1 Y dat_i [20] $end
$var wire 1 Z dat_i [19] $end
$var wire 1 [ dat_i [18] $end
$var wire 1 \ dat_i [17] $end
$var wire 1 ] dat_i [16] $end
$var wire 1 ^ dat_i [15] $end
$var wire 1 _ dat_i [14] $end
$var wire 1 ` dat_i [13] $end
$var wire 1 a dat_i [12] $end
$var wire 1 b dat_i [11] $end
$var wire 1 c dat_i [10] $end
$var wire 1 d dat_i [9] $end
$var wire 1 e dat_i [8] $end
$var wire 1 f dat_i [7] $end
$var wire 1 g dat_i [6] $end
$var wire 1 h dat_i [5] $end
$var wire 1 i dat_i [4] $end
$var wire 1 j dat_i [3] $end
$var wire 1 k dat_i [2] $end
$var wire 1 l dat_i [1] $end
$var wire 1 m dat_i [0] $end
$var wire 1 n dat_o [31] $end
$var wire 1 o dat_o [30] $end
$var wire 1 p dat_o [29] $end
$var wire 1 q dat_o [28] $end
$var wire 1 r dat_o [27] $end
$var wire 1 s dat_o [26] $end
$var wire 1 t dat_o [25] $end
$var wire 1 u dat_o [24] $end
$var wire 1 v dat_o [23] $end
$var wire 1 w dat_o [22] $end
$var wire 1 x dat_o [21] $end
$var wire 1 y dat_o [20] $end
$var wire 1 z dat_o [19] $end
$var wire 1 { dat_o [18] $end
$var wire 1 | dat_o [17] $end
$var wire 1 } dat_o [16] $end
$var wire 1 ~ dat_o [15] $end
$var wire 1 !! dat_o [14] $end
$var wire 1 "! dat_o [13] $end
$var wire 1 #! dat_o [12] $end
$var wire 1 $! dat_o [11] $end
$var wire 1 %! dat_o [10] $end
$var wire 1 &! dat_o [9] $end
$var wire 1 '! dat_o [8] $end
$var wire 1 (! dat_o [7] $end
$var wire 1 )! dat_o [6] $end
$var wire 1 *! dat_o [5] $end
$var wire 1 +! dat_o [4] $end
$var wire 1 ,! dat_o [3] $end
$var wire 1 -! dat_o [2] $end
$var wire 1 .! dat_o [1] $end
$var wire 1 /! dat_o [0] $end
$var wire 1 0! we $end
$var wire 1 1! sel [3] $end
$var wire 1 2! sel [2] $end
$var wire 1 3! sel [1] $end
$var wire 1 4! sel [0] $end
$var wire 1 5! stb $end
$var wire 1 6! cyc $end
$var wire 1 7! ack $end
$var wire 1 8! err $end
$var wire 1 9! int $end
$var wire 1 :! ss [7] $end
$var wire 1 ;! ss [6] $end
$var wire 1 <! ss [5] $end
$var wire 1 =! ss [4] $end
$var wire 1 >! ss [3] $end
$var wire 1 ?! ss [2] $end
$var wire 1 @! ss [1] $end
$var wire 1 A! ss [0] $end
$var wire 1 B! sclk $end
$var wire 1 C! mosi $end
$var wire 1 D! miso $end
$var reg 32 E! q [31:0] $end
$var reg 32 F! q1 [31:0] $end
$var reg 32 G! q2 [31:0] $end
$var reg 32 H! q3 [31:0] $end
$var reg 32 I! result [31:0] $end
$scope module i_spi_slave $end
$var parameter 32 J! Tp $end
$var wire 1 K! rst $end
$var wire 1 A! ss $end
$var wire 1 B! sclk $end
$var wire 1 C! mosi $end
$var reg 1 L! miso $end
$var reg 1 M! rx_negedge $end
$var reg 1 N! tx_negedge $end
$var reg 32 O! data [31:0] $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
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$end
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