_primary.vhd

来自「SPI 总线协议源码SPI 总线协议源码SPI 总线协议源码」· VHDL 代码 · 共 18 行

library verilog;
use verilog.vl_types.all;
entity tb_spi_top is
    generic(
        spi_rx_0        : integer := 0;
        spi_rx_1        : integer := 4;
        spi_rx_2        : integer := 8;
        spi_rx_3        : integer := 12;
        spi_tx_0        : integer := 0;
        spi_tx_1        : integer := 4;
        spi_tx_2        : integer := 8;
        spi_tx_3        : integer := 12;
        spi_ctrl        : integer := 16;
        spi_divide      : integer := 20;
        spi_ss          : integer := 24
    );
end tb_spi_top;