_primary.vhd

来自「SPI 总线协议源码SPI 总线协议源码SPI 总线协议源码」· VHDL 代码 · 共 19 行

library verilog;
use verilog.vl_types.all;
entity spi_clgen is
    generic(
        tp              : integer := 1
    );
    port(
        clk_in          : in     vl_logic;
        rst             : in     vl_logic;
        go              : in     vl_logic;
        enable          : in     vl_logic;
        last_clk        : in     vl_logic;
        divider         : in     vl_logic_vector(15 downto 0);
        clk_out         : out    vl_logic;
        pos_edge        : out    vl_logic;
        neg_edge        : out    vl_logic
    );
end spi_clgen;